| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) ST-Ericsson SA 2010 |
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| 4 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson. |
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| 5 | */ |
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| 6 | #ifndef __AB8500_SYSCTRL_H |
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| 7 | #define __AB8500_SYSCTRL_H |
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| 8 | |
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| 9 | #include <linux/bitops.h> |
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| 10 | |
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| 11 | #ifdef CONFIG_AB8500_CORE |
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| 12 | |
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| 13 | int ab8500_sysctrl_read(u16 reg, u8 *value); |
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| 14 | int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value); |
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| 15 | |
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| 16 | #else |
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| 17 | |
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| 18 | static inline int ab8500_sysctrl_read(u16 reg, u8 *value) |
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| 19 | { |
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| 20 | return 0; |
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| 21 | } |
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| 22 | |
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| 23 | static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value) |
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| 24 | { |
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| 25 | return 0; |
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| 26 | } |
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| 27 | |
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| 28 | #endif /* CONFIG_AB8500_CORE */ |
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| 29 | |
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| 30 | static inline int ab8500_sysctrl_set(u16 reg, u8 bits) |
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| 31 | { |
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| 32 | return ab8500_sysctrl_write(reg, mask: bits, value: bits); |
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| 33 | } |
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| 34 | |
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| 35 | static inline int ab8500_sysctrl_clear(u16 reg, u8 bits) |
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| 36 | { |
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| 37 | return ab8500_sysctrl_write(reg, mask: bits, value: 0); |
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| 38 | } |
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| 39 | |
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| 40 | /* Registers */ |
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| 41 | #define AB8500_TURNONSTATUS 0x100 |
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| 42 | #define AB8500_RESETSTATUS 0x101 |
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| 43 | #define AB8500_PONKEY1PRESSSTATUS 0x102 |
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| 44 | #define AB8500_SYSCLKREQSTATUS 0x142 |
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| 45 | #define AB8500_STW4500CTRL1 0x180 |
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| 46 | #define AB8500_STW4500CTRL2 0x181 |
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| 47 | #define AB8500_STW4500CTRL3 0x200 |
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| 48 | #define AB8500_MAINWDOGCTRL 0x201 |
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| 49 | #define AB8500_MAINWDOGTIMER 0x202 |
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| 50 | #define AB8500_LOWBAT 0x203 |
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| 51 | #define AB8500_BATTOK 0x204 |
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| 52 | #define AB8500_SYSCLKTIMER 0x205 |
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| 53 | #define AB8500_SMPSCLKCTRL 0x206 |
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| 54 | #define AB8500_SMPSCLKSEL1 0x207 |
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| 55 | #define AB8500_SMPSCLKSEL2 0x208 |
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| 56 | #define AB8500_SMPSCLKSEL3 0x209 |
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| 57 | #define AB8500_SYSULPCLKCONF 0x20A |
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| 58 | #define AB8500_SYSULPCLKCTRL1 0x20B |
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| 59 | #define AB8500_SYSCLKCTRL 0x20C |
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| 60 | #define AB8500_SYSCLKREQ1VALID 0x20D |
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| 61 | #define AB8500_SYSTEMCTRLSUP 0x20F |
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| 62 | #define AB8500_SYSCLKREQ1RFCLKBUF 0x210 |
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| 63 | #define AB8500_SYSCLKREQ2RFCLKBUF 0x211 |
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| 64 | #define AB8500_SYSCLKREQ3RFCLKBUF 0x212 |
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| 65 | #define AB8500_SYSCLKREQ4RFCLKBUF 0x213 |
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| 66 | #define AB8500_SYSCLKREQ5RFCLKBUF 0x214 |
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| 67 | #define AB8500_SYSCLKREQ6RFCLKBUF 0x215 |
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| 68 | #define AB8500_SYSCLKREQ7RFCLKBUF 0x216 |
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| 69 | #define AB8500_SYSCLKREQ8RFCLKBUF 0x217 |
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| 70 | #define AB8500_DITHERCLKCTRL 0x220 |
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| 71 | #define AB8500_SWATCTRL 0x230 |
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| 72 | #define AB8500_HIQCLKCTRL 0x232 |
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| 73 | #define AB8500_VSIMSYSCLKCTRL 0x233 |
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| 74 | #define AB9540_SYSCLK12BUFCTRL 0x234 |
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| 75 | #define AB9540_SYSCLK12CONFCTRL 0x235 |
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| 76 | #define AB9540_SYSCLK12BUFCTRL2 0x236 |
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| 77 | #define AB9540_SYSCLK12BUF1VALID 0x237 |
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| 78 | #define AB9540_SYSCLK12BUF2VALID 0x238 |
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| 79 | #define AB9540_SYSCLK12BUF3VALID 0x239 |
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| 80 | #define AB9540_SYSCLK12BUF4VALID 0x23A |
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| 81 | |
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| 82 | /* Bits */ |
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| 83 | #define AB8500_TURNONSTATUS_PORNVBAT BIT(0) |
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| 84 | #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1) |
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| 85 | #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2) |
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| 86 | #define AB8500_TURNONSTATUS_RTCALARM BIT(3) |
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| 87 | #define AB8500_TURNONSTATUS_MAINCHDET BIT(4) |
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| 88 | #define AB8500_TURNONSTATUS_VBUSDET BIT(5) |
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| 89 | #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6) |
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| 90 | |
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| 91 | #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0) |
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| 92 | #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2) |
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| 93 | |
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| 94 | #define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F |
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| 95 | #define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0 |
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| 96 | |
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| 97 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0) |
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| 98 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1) |
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| 99 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2) |
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| 100 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3) |
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| 101 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4) |
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| 102 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5) |
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| 103 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6) |
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| 104 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7) |
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| 105 | |
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| 106 | #define AB8500_STW4500CTRL1_SWOFF BIT(0) |
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| 107 | #define AB8500_STW4500CTRL1_SWRESET4500N BIT(1) |
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| 108 | #define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2) |
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| 109 | |
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| 110 | #define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0) |
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| 111 | #define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1) |
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| 112 | #define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2) |
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| 113 | #define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3) |
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| 114 | #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4) |
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| 115 | #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5) |
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| 116 | #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6) |
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| 117 | #define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7) |
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| 118 | |
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| 119 | #define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0) |
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| 120 | #define AB8500_STW4500CTRL3_RESETAUDN BIT(1) |
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| 121 | #define AB8500_STW4500CTRL3_RESETDENCN BIT(2) |
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| 122 | #define AB8500_STW4500CTRL3_THSDENA BIT(3) |
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| 123 | |
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| 124 | #define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0) |
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| 125 | #define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1) |
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| 126 | #define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4) |
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| 127 | |
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| 128 | #define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F |
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| 129 | #define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0 |
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| 130 | |
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| 131 | #define AB8500_LOWBAT_LOWBATENA BIT(0) |
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| 132 | #define AB8500_LOWBAT_LOWBAT_MASK 0x7E |
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| 133 | #define AB8500_LOWBAT_LOWBAT_SHIFT 1 |
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| 134 | |
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| 135 | #define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F |
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| 136 | #define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0 |
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| 137 | #define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0 |
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| 138 | #define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4 |
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| 139 | |
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| 140 | #define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F |
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| 141 | #define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0 |
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| 142 | #define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0 |
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| 143 | #define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4 |
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| 144 | |
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| 145 | #define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03 |
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| 146 | #define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0 |
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| 147 | #define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2) |
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| 148 | |
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| 149 | #define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07 |
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| 150 | #define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0 |
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| 151 | #define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38 |
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| 152 | #define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3 |
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| 153 | |
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| 154 | #define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07 |
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| 155 | #define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0 |
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| 156 | #define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38 |
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| 157 | #define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3 |
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| 158 | |
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| 159 | #define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07 |
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| 160 | #define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0 |
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| 161 | #define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38 |
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| 162 | #define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3 |
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| 163 | |
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| 164 | #define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03 |
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| 165 | #define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0 |
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| 166 | #define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2) |
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| 167 | #define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3) |
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| 168 | #define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4) |
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| 169 | #define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5) |
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| 170 | #define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6) |
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| 171 | #define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7) |
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| 172 | |
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| 173 | #define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03 |
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| 174 | #define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0 |
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| 175 | #define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2) |
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| 176 | #define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3) |
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| 177 | #define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4) |
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| 178 | #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5) |
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| 179 | #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6) |
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| 180 | #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7) |
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| 181 | |
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| 182 | #define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0) |
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| 183 | #define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1) |
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| 184 | #define AB8500_SYSCLKCTRL_USBCLKENA BIT(2) |
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| 185 | |
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| 186 | #define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0) |
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| 187 | #define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1) |
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| 188 | #define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2) |
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| 189 | |
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| 190 | #define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03 |
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| 191 | #define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0 |
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| 192 | #define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C |
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| 193 | #define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2 |
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| 194 | #define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4) |
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| 195 | |
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| 196 | #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2) |
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| 197 | #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3) |
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| 198 | #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4) |
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| 199 | |
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| 200 | #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2) |
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| 201 | #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3) |
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| 202 | #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4) |
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| 203 | |
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| 204 | #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2) |
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| 205 | #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3) |
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| 206 | #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4) |
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| 207 | |
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| 208 | #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2) |
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| 209 | #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3) |
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| 210 | #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4) |
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| 211 | |
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| 212 | #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2) |
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| 213 | #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3) |
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| 214 | #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4) |
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| 215 | |
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| 216 | #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2) |
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| 217 | #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3) |
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| 218 | #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4) |
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| 219 | |
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| 220 | #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2) |
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| 221 | #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3) |
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| 222 | #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4) |
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| 223 | |
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| 224 | #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2) |
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| 225 | #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3) |
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| 226 | #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4) |
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| 227 | |
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| 228 | #define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0) |
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| 229 | #define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1) |
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| 230 | #define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2) |
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| 231 | #define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3) |
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| 232 | #define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4) |
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| 233 | #define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5) |
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| 234 | #define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0 |
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| 235 | #define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6 |
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| 236 | |
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| 237 | #define AB8500_SWATCTRL_UPDATERF BIT(0) |
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| 238 | #define AB8500_SWATCTRL_SWATENABLE BIT(1) |
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| 239 | #define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C |
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| 240 | #define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2 |
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| 241 | #define AB8500_SWATCTRL_SWATBIT5 BIT(6) |
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| 242 | |
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| 243 | #define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0) |
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| 244 | #define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1) |
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| 245 | #define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2) |
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| 246 | #define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3) |
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| 247 | #define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4) |
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| 248 | #define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5) |
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| 249 | #define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6) |
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| 250 | #define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7) |
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| 251 | |
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| 252 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0) |
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| 253 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1) |
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| 254 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2) |
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| 255 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3) |
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| 256 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4) |
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| 257 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5) |
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| 258 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6) |
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| 259 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7) |
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| 260 | |
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| 261 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0) |
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| 262 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1) |
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| 263 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2) |
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| 264 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3) |
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| 265 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F |
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| 266 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4) |
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| 267 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5) |
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| 268 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6) |
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| 269 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7) |
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| 270 | #define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0 |
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| 271 | |
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| 272 | #define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0) |
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| 273 | #define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1) |
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| 274 | #define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2) |
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| 275 | #define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3) |
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| 276 | #define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4) |
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| 277 | #define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5) |
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| 278 | #define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6) |
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| 279 | |
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| 280 | #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0) |
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| 281 | #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1) |
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| 282 | #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2) |
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| 283 | #define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3) |
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| 284 | |
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| 285 | #define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF |
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| 286 | #define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0 |
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| 287 | |
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| 288 | #define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF |
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| 289 | #define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0 |
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| 290 | |
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| 291 | #define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF |
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| 292 | #define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0 |
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| 293 | |
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| 294 | #define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF |
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| 295 | #define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0 |
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| 296 | |
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| 297 | #define AB8500_ENABLE_WD 0x1 |
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| 298 | #define AB8500_KICK_WD 0x2 |
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| 299 | #define AB8500_WD_RESTART_ON_EXPIRE 0x10 |
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| 300 | |
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| 301 | #endif /* __AB8500_SYSCTRL_H */ |
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| 302 | |
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