| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * as3722 definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2013 ams |
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| 6 | * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. |
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| 7 | * |
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| 8 | * Author: Florian Lobmaier <florian.lobmaier@ams.com> |
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| 9 | * Author: Laxman Dewangan <ldewangan@nvidia.com> |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __LINUX_MFD_AS3722_H__ |
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| 13 | #define __LINUX_MFD_AS3722_H__ |
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| 14 | |
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| 15 | #include <linux/regmap.h> |
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| 16 | |
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| 17 | /* AS3722 registers */ |
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| 18 | #define AS3722_SD0_VOLTAGE_REG 0x00 |
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| 19 | #define AS3722_SD1_VOLTAGE_REG 0x01 |
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| 20 | #define AS3722_SD2_VOLTAGE_REG 0x02 |
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| 21 | #define AS3722_SD3_VOLTAGE_REG 0x03 |
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| 22 | #define AS3722_SD4_VOLTAGE_REG 0x04 |
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| 23 | #define AS3722_SD5_VOLTAGE_REG 0x05 |
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| 24 | #define AS3722_SD6_VOLTAGE_REG 0x06 |
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| 25 | #define AS3722_GPIO0_CONTROL_REG 0x08 |
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| 26 | #define AS3722_GPIO1_CONTROL_REG 0x09 |
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| 27 | #define AS3722_GPIO2_CONTROL_REG 0x0A |
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| 28 | #define AS3722_GPIO3_CONTROL_REG 0x0B |
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| 29 | #define AS3722_GPIO4_CONTROL_REG 0x0C |
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| 30 | #define AS3722_GPIO5_CONTROL_REG 0x0D |
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| 31 | #define AS3722_GPIO6_CONTROL_REG 0x0E |
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| 32 | #define AS3722_GPIO7_CONTROL_REG 0x0F |
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| 33 | #define AS3722_LDO0_VOLTAGE_REG 0x10 |
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| 34 | #define AS3722_LDO1_VOLTAGE_REG 0x11 |
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| 35 | #define AS3722_LDO2_VOLTAGE_REG 0x12 |
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| 36 | #define AS3722_LDO3_VOLTAGE_REG 0x13 |
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| 37 | #define AS3722_LDO4_VOLTAGE_REG 0x14 |
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| 38 | #define AS3722_LDO5_VOLTAGE_REG 0x15 |
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| 39 | #define AS3722_LDO6_VOLTAGE_REG 0x16 |
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| 40 | #define AS3722_LDO7_VOLTAGE_REG 0x17 |
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| 41 | #define AS3722_LDO9_VOLTAGE_REG 0x19 |
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| 42 | #define AS3722_LDO10_VOLTAGE_REG 0x1A |
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| 43 | #define AS3722_LDO11_VOLTAGE_REG 0x1B |
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| 44 | #define AS3722_GPIO_DEB1_REG 0x1E |
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| 45 | #define AS3722_GPIO_DEB2_REG 0x1F |
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| 46 | #define AS3722_GPIO_SIGNAL_OUT_REG 0x20 |
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| 47 | #define AS3722_GPIO_SIGNAL_IN_REG 0x21 |
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| 48 | #define AS3722_REG_SEQU_MOD1_REG 0x22 |
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| 49 | #define AS3722_REG_SEQU_MOD2_REG 0x23 |
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| 50 | #define AS3722_REG_SEQU_MOD3_REG 0x24 |
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| 51 | #define AS3722_SD_PHSW_CTRL_REG 0x27 |
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| 52 | #define AS3722_SD_PHSW_STATUS 0x28 |
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| 53 | #define AS3722_SD0_CONTROL_REG 0x29 |
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| 54 | #define AS3722_SD1_CONTROL_REG 0x2A |
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| 55 | #define AS3722_SDmph_CONTROL_REG 0x2B |
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| 56 | #define AS3722_SD23_CONTROL_REG 0x2C |
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| 57 | #define AS3722_SD4_CONTROL_REG 0x2D |
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| 58 | #define AS3722_SD5_CONTROL_REG 0x2E |
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| 59 | #define AS3722_SD6_CONTROL_REG 0x2F |
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| 60 | #define AS3722_SD_DVM_REG 0x30 |
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| 61 | #define AS3722_RESET_REASON_REG 0x31 |
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| 62 | #define AS3722_BATTERY_VOLTAGE_MONITOR_REG 0x32 |
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| 63 | #define AS3722_STARTUP_CONTROL_REG 0x33 |
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| 64 | #define AS3722_RESET_TIMER_REG 0x34 |
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| 65 | #define AS3722_REFERENCE_CONTROL_REG 0x35 |
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| 66 | #define AS3722_RESET_CONTROL_REG 0x36 |
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| 67 | #define AS3722_OVER_TEMP_CONTROL_REG 0x37 |
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| 68 | #define AS3722_WATCHDOG_CONTROL_REG 0x38 |
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| 69 | #define AS3722_REG_STANDBY_MOD1_REG 0x39 |
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| 70 | #define AS3722_REG_STANDBY_MOD2_REG 0x3A |
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| 71 | #define AS3722_REG_STANDBY_MOD3_REG 0x3B |
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| 72 | #define AS3722_ENABLE_CTRL1_REG 0x3C |
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| 73 | #define AS3722_ENABLE_CTRL2_REG 0x3D |
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| 74 | #define AS3722_ENABLE_CTRL3_REG 0x3E |
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| 75 | #define AS3722_ENABLE_CTRL4_REG 0x3F |
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| 76 | #define AS3722_ENABLE_CTRL5_REG 0x40 |
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| 77 | #define AS3722_PWM_CONTROL_L_REG 0x41 |
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| 78 | #define AS3722_PWM_CONTROL_H_REG 0x42 |
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| 79 | #define AS3722_WATCHDOG_TIMER_REG 0x46 |
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| 80 | #define AS3722_WATCHDOG_SOFTWARE_SIGNAL_REG 0x48 |
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| 81 | #define AS3722_IOVOLTAGE_REG 0x49 |
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| 82 | #define AS3722_BATTERY_VOLTAGE_MONITOR2_REG 0x4A |
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| 83 | #define AS3722_SD_CONTROL_REG 0x4D |
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| 84 | #define AS3722_LDOCONTROL0_REG 0x4E |
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| 85 | #define AS3722_LDOCONTROL1_REG 0x4F |
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| 86 | #define AS3722_SD0_PROTECT_REG 0x50 |
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| 87 | #define AS3722_SD6_PROTECT_REG 0x51 |
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| 88 | #define AS3722_PWM_VCONTROL1_REG 0x52 |
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| 89 | #define AS3722_PWM_VCONTROL2_REG 0x53 |
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| 90 | #define AS3722_PWM_VCONTROL3_REG 0x54 |
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| 91 | #define AS3722_PWM_VCONTROL4_REG 0x55 |
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| 92 | #define AS3722_BB_CHARGER_REG 0x57 |
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| 93 | #define AS3722_CTRL_SEQU1_REG 0x58 |
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| 94 | #define AS3722_CTRL_SEQU2_REG 0x59 |
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| 95 | #define AS3722_OVCURRENT_REG 0x5A |
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| 96 | #define AS3722_OVCURRENT_DEB_REG 0x5B |
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| 97 | #define AS3722_SDLV_DEB_REG 0x5C |
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| 98 | #define AS3722_OC_PG_CTRL_REG 0x5D |
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| 99 | #define AS3722_OC_PG_CTRL2_REG 0x5E |
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| 100 | #define AS3722_CTRL_STATUS 0x5F |
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| 101 | #define AS3722_RTC_CONTROL_REG 0x60 |
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| 102 | #define AS3722_RTC_SECOND_REG 0x61 |
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| 103 | #define AS3722_RTC_MINUTE_REG 0x62 |
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| 104 | #define AS3722_RTC_HOUR_REG 0x63 |
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| 105 | #define AS3722_RTC_DAY_REG 0x64 |
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| 106 | #define AS3722_RTC_MONTH_REG 0x65 |
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| 107 | #define AS3722_RTC_YEAR_REG 0x66 |
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| 108 | #define AS3722_RTC_ALARM_SECOND_REG 0x67 |
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| 109 | #define AS3722_RTC_ALARM_MINUTE_REG 0x68 |
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| 110 | #define AS3722_RTC_ALARM_HOUR_REG 0x69 |
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| 111 | #define AS3722_RTC_ALARM_DAY_REG 0x6A |
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| 112 | #define AS3722_RTC_ALARM_MONTH_REG 0x6B |
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| 113 | #define AS3722_RTC_ALARM_YEAR_REG 0x6C |
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| 114 | #define AS3722_SRAM_REG 0x6D |
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| 115 | #define AS3722_RTC_ACCESS_REG 0x6F |
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| 116 | #define AS3722_RTC_STATUS_REG 0x73 |
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| 117 | #define AS3722_INTERRUPT_MASK1_REG 0x74 |
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| 118 | #define AS3722_INTERRUPT_MASK2_REG 0x75 |
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| 119 | #define AS3722_INTERRUPT_MASK3_REG 0x76 |
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| 120 | #define AS3722_INTERRUPT_MASK4_REG 0x77 |
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| 121 | #define AS3722_INTERRUPT_STATUS1_REG 0x78 |
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| 122 | #define AS3722_INTERRUPT_STATUS2_REG 0x79 |
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| 123 | #define AS3722_INTERRUPT_STATUS3_REG 0x7A |
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| 124 | #define AS3722_INTERRUPT_STATUS4_REG 0x7B |
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| 125 | #define AS3722_TEMP_STATUS_REG 0x7D |
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| 126 | #define AS3722_ADC0_CONTROL_REG 0x80 |
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| 127 | #define AS3722_ADC1_CONTROL_REG 0x81 |
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| 128 | #define AS3722_ADC0_MSB_RESULT_REG 0x82 |
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| 129 | #define AS3722_ADC0_LSB_RESULT_REG 0x83 |
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| 130 | #define AS3722_ADC1_MSB_RESULT_REG 0x84 |
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| 131 | #define AS3722_ADC1_LSB_RESULT_REG 0x85 |
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| 132 | #define AS3722_ADC1_THRESHOLD_HI_MSB_REG 0x86 |
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| 133 | #define AS3722_ADC1_THRESHOLD_HI_LSB_REG 0x87 |
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| 134 | #define AS3722_ADC1_THRESHOLD_LO_MSB_REG 0x88 |
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| 135 | #define AS3722_ADC1_THRESHOLD_LO_LSB_REG 0x89 |
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| 136 | #define AS3722_ADC_CONFIGURATION_REG 0x8A |
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| 137 | #define AS3722_ASIC_ID1_REG 0x90 |
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| 138 | #define AS3722_ASIC_ID2_REG 0x91 |
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| 139 | #define AS3722_LOCK_REG 0x9E |
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| 140 | #define AS3722_FUSE7_REG 0xA7 |
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| 141 | #define AS3722_MAX_REGISTER 0xF4 |
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| 142 | |
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| 143 | #define AS3722_SD0_EXT_ENABLE_MASK 0x03 |
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| 144 | #define AS3722_SD1_EXT_ENABLE_MASK 0x0C |
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| 145 | #define AS3722_SD2_EXT_ENABLE_MASK 0x30 |
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| 146 | #define AS3722_SD3_EXT_ENABLE_MASK 0xC0 |
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| 147 | #define AS3722_SD4_EXT_ENABLE_MASK 0x03 |
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| 148 | #define AS3722_SD5_EXT_ENABLE_MASK 0x0C |
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| 149 | #define AS3722_SD6_EXT_ENABLE_MASK 0x30 |
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| 150 | #define AS3722_LDO0_EXT_ENABLE_MASK 0x03 |
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| 151 | #define AS3722_LDO1_EXT_ENABLE_MASK 0x0C |
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| 152 | #define AS3722_LDO2_EXT_ENABLE_MASK 0x30 |
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| 153 | #define AS3722_LDO3_EXT_ENABLE_MASK 0xC0 |
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| 154 | #define AS3722_LDO4_EXT_ENABLE_MASK 0x03 |
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| 155 | #define AS3722_LDO5_EXT_ENABLE_MASK 0x0C |
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| 156 | #define AS3722_LDO6_EXT_ENABLE_MASK 0x30 |
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| 157 | #define AS3722_LDO7_EXT_ENABLE_MASK 0xC0 |
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| 158 | #define AS3722_LDO9_EXT_ENABLE_MASK 0x0C |
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| 159 | #define AS3722_LDO10_EXT_ENABLE_MASK 0x30 |
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| 160 | #define AS3722_LDO11_EXT_ENABLE_MASK 0xC0 |
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| 161 | |
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| 162 | #define AS3722_OVCURRENT_SD0_ALARM_MASK 0x07 |
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| 163 | #define AS3722_OVCURRENT_SD0_ALARM_SHIFT 0x01 |
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| 164 | #define AS3722_OVCURRENT_SD0_TRIP_MASK 0x18 |
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| 165 | #define AS3722_OVCURRENT_SD0_TRIP_SHIFT 0x03 |
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| 166 | #define AS3722_OVCURRENT_SD1_TRIP_MASK 0x60 |
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| 167 | #define AS3722_OVCURRENT_SD1_TRIP_SHIFT 0x05 |
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| 168 | |
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| 169 | #define AS3722_OVCURRENT_SD6_ALARM_MASK 0x07 |
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| 170 | #define AS3722_OVCURRENT_SD6_ALARM_SHIFT 0x01 |
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| 171 | #define AS3722_OVCURRENT_SD6_TRIP_MASK 0x18 |
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| 172 | #define AS3722_OVCURRENT_SD6_TRIP_SHIFT 0x03 |
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| 173 | |
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| 174 | /* AS3722 register bits and bit masks */ |
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| 175 | #define AS3722_LDO_ILIMIT_MASK BIT(7) |
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| 176 | #define AS3722_LDO_ILIMIT_BIT BIT(7) |
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| 177 | #define AS3722_LDO0_VSEL_MASK 0x1F |
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| 178 | #define AS3722_LDO0_VSEL_MIN 0x01 |
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| 179 | #define AS3722_LDO0_VSEL_MAX 0x12 |
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| 180 | #define AS3722_LDO0_NUM_VOLT 0x12 |
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| 181 | #define AS3722_LDO3_VSEL_MASK 0x3F |
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| 182 | #define AS3722_LDO3_VSEL_MIN 0x01 |
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| 183 | #define AS3722_LDO3_VSEL_MAX 0x2D |
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| 184 | #define AS3722_LDO3_NUM_VOLT 0x2D |
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| 185 | #define AS3722_LDO6_VSEL_BYPASS 0x3F |
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| 186 | #define AS3722_LDO_VSEL_MASK 0x7F |
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| 187 | #define AS3722_LDO_VSEL_MIN 0x01 |
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| 188 | #define AS3722_LDO_VSEL_MAX 0x7F |
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| 189 | #define AS3722_LDO_VSEL_DNU_MIN 0x25 |
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| 190 | #define AS3722_LDO_VSEL_DNU_MAX 0x3F |
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| 191 | #define AS3722_LDO_NUM_VOLT 0x80 |
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| 192 | |
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| 193 | #define AS3722_LDO0_CTRL BIT(0) |
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| 194 | #define AS3722_LDO1_CTRL BIT(1) |
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| 195 | #define AS3722_LDO2_CTRL BIT(2) |
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| 196 | #define AS3722_LDO3_CTRL BIT(3) |
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| 197 | #define AS3722_LDO4_CTRL BIT(4) |
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| 198 | #define AS3722_LDO5_CTRL BIT(5) |
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| 199 | #define AS3722_LDO6_CTRL BIT(6) |
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| 200 | #define AS3722_LDO7_CTRL BIT(7) |
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| 201 | #define AS3722_LDO9_CTRL BIT(1) |
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| 202 | #define AS3722_LDO10_CTRL BIT(2) |
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| 203 | #define AS3722_LDO11_CTRL BIT(3) |
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| 204 | |
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| 205 | #define AS3722_LDO3_MODE_MASK (3 << 6) |
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| 206 | #define AS3722_LDO3_MODE_VAL(n) (((n) & 0x3) << 6) |
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| 207 | #define AS3722_LDO3_MODE_PMOS AS3722_LDO3_MODE_VAL(0) |
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| 208 | #define AS3722_LDO3_MODE_PMOS_TRACKING AS3722_LDO3_MODE_VAL(1) |
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| 209 | #define AS3722_LDO3_MODE_NMOS AS3722_LDO3_MODE_VAL(2) |
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| 210 | #define AS3722_LDO3_MODE_SWITCH AS3722_LDO3_MODE_VAL(3) |
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| 211 | |
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| 212 | #define AS3722_SD_VSEL_MASK 0x7F |
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| 213 | #define AS3722_SD0_VSEL_MIN 0x01 |
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| 214 | #define AS3722_SD0_VSEL_MAX 0x5A |
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| 215 | #define AS3722_SD0_VSEL_LOW_VOL_MAX 0x6E |
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| 216 | #define AS3722_SD2_VSEL_MIN 0x01 |
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| 217 | #define AS3722_SD2_VSEL_MAX 0x7F |
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| 218 | |
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| 219 | #define AS3722_SDn_CTRL(n) BIT(n) |
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| 220 | |
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| 221 | #define AS3722_SD0_MODE_FAST BIT(4) |
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| 222 | #define AS3722_SD1_MODE_FAST BIT(4) |
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| 223 | #define AS3722_SD2_MODE_FAST BIT(2) |
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| 224 | #define AS3722_SD3_MODE_FAST BIT(6) |
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| 225 | #define AS3722_SD4_MODE_FAST BIT(2) |
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| 226 | #define AS3722_SD5_MODE_FAST BIT(2) |
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| 227 | #define AS3722_SD6_MODE_FAST BIT(4) |
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| 228 | |
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| 229 | #define AS3722_POWER_OFF BIT(1) |
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| 230 | |
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| 231 | #define AS3722_INTERRUPT_MASK1_LID BIT(0) |
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| 232 | #define AS3722_INTERRUPT_MASK1_ACOK BIT(1) |
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| 233 | #define AS3722_INTERRUPT_MASK1_ENABLE1 BIT(2) |
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| 234 | #define AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0 BIT(3) |
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| 235 | #define AS3722_INTERRUPT_MASK1_ONKEY_LONG BIT(4) |
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| 236 | #define AS3722_INTERRUPT_MASK1_ONKEY BIT(5) |
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| 237 | #define AS3722_INTERRUPT_MASK1_OVTMP BIT(6) |
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| 238 | #define AS3722_INTERRUPT_MASK1_LOWBAT BIT(7) |
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| 239 | |
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| 240 | #define AS3722_INTERRUPT_MASK2_SD0_LV BIT(0) |
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| 241 | #define AS3722_INTERRUPT_MASK2_SD1_LV BIT(1) |
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| 242 | #define AS3722_INTERRUPT_MASK2_SD2345_LV BIT(2) |
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| 243 | #define AS3722_INTERRUPT_MASK2_PWM1_OV_PROT BIT(3) |
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| 244 | #define AS3722_INTERRUPT_MASK2_PWM2_OV_PROT BIT(4) |
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| 245 | #define AS3722_INTERRUPT_MASK2_ENABLE2 BIT(5) |
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| 246 | #define AS3722_INTERRUPT_MASK2_SD6_LV BIT(6) |
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| 247 | #define AS3722_INTERRUPT_MASK2_RTC_REP BIT(7) |
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| 248 | |
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| 249 | #define AS3722_INTERRUPT_MASK3_RTC_ALARM BIT(0) |
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| 250 | #define AS3722_INTERRUPT_MASK3_GPIO1 BIT(1) |
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| 251 | #define AS3722_INTERRUPT_MASK3_GPIO2 BIT(2) |
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| 252 | #define AS3722_INTERRUPT_MASK3_GPIO3 BIT(3) |
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| 253 | #define AS3722_INTERRUPT_MASK3_GPIO4 BIT(4) |
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| 254 | #define AS3722_INTERRUPT_MASK3_GPIO5 BIT(5) |
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| 255 | #define AS3722_INTERRUPT_MASK3_WATCHDOG BIT(6) |
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| 256 | #define AS3722_INTERRUPT_MASK3_ENABLE3 BIT(7) |
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| 257 | |
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| 258 | #define AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN BIT(0) |
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| 259 | #define AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN BIT(1) |
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| 260 | #define AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN BIT(2) |
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| 261 | #define AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM BIT(3) |
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| 262 | #define AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM BIT(4) |
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| 263 | #define AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM BIT(5) |
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| 264 | #define AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6 BIT(6) |
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| 265 | #define AS3722_INTERRUPT_MASK4_ADC BIT(7) |
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| 266 | |
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| 267 | #define AS3722_ADC1_INTERVAL_TIME BIT(0) |
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| 268 | #define AS3722_ADC1_INT_MODE_ON BIT(1) |
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| 269 | #define AS3722_ADC_BUF_ON BIT(2) |
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| 270 | #define AS3722_ADC1_LOW_VOLTAGE_RANGE BIT(5) |
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| 271 | #define AS3722_ADC1_INTEVAL_SCAN BIT(6) |
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| 272 | #define AS3722_ADC1_INT_MASK BIT(7) |
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| 273 | |
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| 274 | #define AS3722_ADC_MSB_VAL_MASK 0x7F |
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| 275 | #define AS3722_ADC_LSB_VAL_MASK 0x07 |
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| 276 | |
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| 277 | #define AS3722_ADC0_CONV_START BIT(7) |
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| 278 | #define AS3722_ADC0_CONV_NOTREADY BIT(7) |
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| 279 | #define AS3722_ADC0_SOURCE_SELECT_MASK 0x1F |
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| 280 | |
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| 281 | #define AS3722_ADC1_CONV_START BIT(7) |
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| 282 | #define AS3722_ADC1_CONV_NOTREADY BIT(7) |
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| 283 | #define AS3722_ADC1_SOURCE_SELECT_MASK 0x1F |
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| 284 | |
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| 285 | #define AS3722_CTRL_SEQU1_AC_OK_PWR_ON BIT(0) |
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| 286 | |
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| 287 | /* GPIO modes */ |
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| 288 | #define AS3722_GPIO_MODE_MASK 0x07 |
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| 289 | #define AS3722_GPIO_MODE_INPUT 0x00 |
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| 290 | #define AS3722_GPIO_MODE_OUTPUT_VDDH 0x01 |
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| 291 | #define AS3722_GPIO_MODE_IO_OPEN_DRAIN 0x02 |
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| 292 | #define AS3722_GPIO_MODE_ADC_IN 0x03 |
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| 293 | #define AS3722_GPIO_MODE_INPUT_PULL_UP 0x04 |
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| 294 | #define AS3722_GPIO_MODE_INPUT_PULL_DOWN 0x05 |
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| 295 | #define AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP 0x06 |
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| 296 | #define AS3722_GPIO_MODE_OUTPUT_VDDL 0x07 |
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| 297 | #define AS3722_GPIO_MODE_VAL(n) ((n) & AS3722_GPIO_MODE_MASK) |
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| 298 | |
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| 299 | #define AS3722_GPIO_INV BIT(7) |
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| 300 | #define AS3722_GPIO_IOSF_MASK 0x78 |
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| 301 | #define AS3722_GPIO_IOSF_VAL(n) (((n) & 0xF) << 3) |
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| 302 | #define AS3722_GPIO_IOSF_NORMAL AS3722_GPIO_IOSF_VAL(0) |
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| 303 | #define AS3722_GPIO_IOSF_INTERRUPT_OUT AS3722_GPIO_IOSF_VAL(1) |
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| 304 | #define AS3722_GPIO_IOSF_VSUP_LOW_OUT AS3722_GPIO_IOSF_VAL(2) |
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| 305 | #define AS3722_GPIO_IOSF_GPIO_INTERRUPT_IN AS3722_GPIO_IOSF_VAL(3) |
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| 306 | #define AS3722_GPIO_IOSF_ISINK_PWM_IN AS3722_GPIO_IOSF_VAL(4) |
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| 307 | #define AS3722_GPIO_IOSF_VOLTAGE_STBY AS3722_GPIO_IOSF_VAL(5) |
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| 308 | #define AS3722_GPIO_IOSF_SD0_OUT AS3722_GPIO_IOSF_VAL(6) |
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| 309 | #define AS3722_GPIO_IOSF_PWR_GOOD_OUT AS3722_GPIO_IOSF_VAL(7) |
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| 310 | #define AS3722_GPIO_IOSF_Q32K_OUT AS3722_GPIO_IOSF_VAL(8) |
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| 311 | #define AS3722_GPIO_IOSF_WATCHDOG_IN AS3722_GPIO_IOSF_VAL(9) |
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| 312 | #define AS3722_GPIO_IOSF_SOFT_RESET_IN AS3722_GPIO_IOSF_VAL(11) |
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| 313 | #define AS3722_GPIO_IOSF_PWM_OUT AS3722_GPIO_IOSF_VAL(12) |
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| 314 | #define AS3722_GPIO_IOSF_VSUP_LOW_DEB_OUT AS3722_GPIO_IOSF_VAL(13) |
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| 315 | #define AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW AS3722_GPIO_IOSF_VAL(14) |
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| 316 | |
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| 317 | #define AS3722_GPIOn_SIGNAL(n) BIT(n) |
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| 318 | #define AS3722_GPIOn_CONTROL_REG(n) (AS3722_GPIO0_CONTROL_REG + n) |
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| 319 | #define AS3722_I2C_PULL_UP BIT(4) |
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| 320 | #define AS3722_INT_PULL_UP BIT(5) |
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| 321 | |
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| 322 | #define AS3722_RTC_REP_WAKEUP_EN BIT(0) |
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| 323 | #define AS3722_RTC_ALARM_WAKEUP_EN BIT(1) |
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| 324 | #define AS3722_RTC_ON BIT(2) |
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| 325 | #define AS3722_RTC_IRQMODE BIT(3) |
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| 326 | #define AS3722_RTC_CLK32K_OUT_EN BIT(5) |
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| 327 | |
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| 328 | #define AS3722_WATCHDOG_TIMER_MAX 0x7F |
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| 329 | #define AS3722_WATCHDOG_ON BIT(0) |
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| 330 | #define AS3722_WATCHDOG_SW_SIG BIT(0) |
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| 331 | |
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| 332 | #define AS3722_EXT_CONTROL_ENABLE1 0x1 |
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| 333 | #define AS3722_EXT_CONTROL_ENABLE2 0x2 |
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| 334 | #define AS3722_EXT_CONTROL_ENABLE3 0x3 |
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| 335 | |
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| 336 | #define AS3722_FUSE7_SD0_LOW_VOLTAGE BIT(4) |
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| 337 | |
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| 338 | /* Interrupt IDs */ |
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| 339 | enum as3722_irq { |
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| 340 | AS3722_IRQ_LID, |
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| 341 | AS3722_IRQ_ACOK, |
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| 342 | AS3722_IRQ_ENABLE1, |
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| 343 | AS3722_IRQ_OCCUR_ALARM_SD0, |
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| 344 | AS3722_IRQ_ONKEY_LONG_PRESS, |
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| 345 | AS3722_IRQ_ONKEY, |
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| 346 | AS3722_IRQ_OVTMP, |
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| 347 | AS3722_IRQ_LOWBAT, |
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| 348 | AS3722_IRQ_SD0_LV, |
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| 349 | AS3722_IRQ_SD1_LV, |
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| 350 | AS3722_IRQ_SD2_LV, |
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| 351 | AS3722_IRQ_PWM1_OV_PROT, |
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| 352 | AS3722_IRQ_PWM2_OV_PROT, |
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| 353 | AS3722_IRQ_ENABLE2, |
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| 354 | AS3722_IRQ_SD6_LV, |
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| 355 | AS3722_IRQ_RTC_REP, |
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| 356 | AS3722_IRQ_RTC_ALARM, |
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| 357 | AS3722_IRQ_GPIO1, |
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| 358 | AS3722_IRQ_GPIO2, |
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| 359 | AS3722_IRQ_GPIO3, |
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| 360 | AS3722_IRQ_GPIO4, |
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| 361 | AS3722_IRQ_GPIO5, |
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| 362 | AS3722_IRQ_WATCHDOG, |
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| 363 | AS3722_IRQ_ENABLE3, |
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| 364 | AS3722_IRQ_TEMP_SD0_SHUTDOWN, |
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| 365 | AS3722_IRQ_TEMP_SD1_SHUTDOWN, |
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| 366 | AS3722_IRQ_TEMP_SD2_SHUTDOWN, |
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| 367 | AS3722_IRQ_TEMP_SD0_ALARM, |
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| 368 | AS3722_IRQ_TEMP_SD1_ALARM, |
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| 369 | AS3722_IRQ_TEMP_SD6_ALARM, |
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| 370 | AS3722_IRQ_OCCUR_ALARM_SD6, |
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| 371 | AS3722_IRQ_ADC, |
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| 372 | AS3722_IRQ_MAX, |
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| 373 | }; |
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| 374 | |
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| 375 | struct as3722 { |
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| 376 | struct device *dev; |
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| 377 | struct regmap *regmap; |
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| 378 | int chip_irq; |
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| 379 | unsigned long irq_flags; |
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| 380 | bool en_intern_int_pullup; |
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| 381 | bool en_intern_i2c_pullup; |
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| 382 | bool en_ac_ok_pwr_on; |
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| 383 | struct regmap_irq_chip_data *irq_data; |
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| 384 | }; |
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| 385 | |
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| 386 | static inline int as3722_read(struct as3722 *as3722, u32 reg, u32 *dest) |
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| 387 | { |
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| 388 | return regmap_read(map: as3722->regmap, reg, val: dest); |
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| 389 | } |
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| 390 | |
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| 391 | static inline int as3722_write(struct as3722 *as3722, u32 reg, u32 value) |
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| 392 | { |
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| 393 | return regmap_write(map: as3722->regmap, reg, val: value); |
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| 394 | } |
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| 395 | |
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| 396 | static inline int as3722_block_read(struct as3722 *as3722, u32 reg, |
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| 397 | int count, u8 *buf) |
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| 398 | { |
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| 399 | return regmap_bulk_read(map: as3722->regmap, reg, val: buf, val_count: count); |
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| 400 | } |
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| 401 | |
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| 402 | static inline int as3722_block_write(struct as3722 *as3722, u32 reg, |
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| 403 | int count, u8 *data) |
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| 404 | { |
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| 405 | return regmap_bulk_write(map: as3722->regmap, reg, val: data, val_count: count); |
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| 406 | } |
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| 407 | |
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| 408 | static inline int as3722_update_bits(struct as3722 *as3722, u32 reg, |
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| 409 | u32 mask, u8 val) |
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| 410 | { |
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| 411 | return regmap_update_bits(map: as3722->regmap, reg, mask, val); |
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| 412 | } |
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| 413 | |
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| 414 | static inline int as3722_irq_get_virq(struct as3722 *as3722, int irq) |
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| 415 | { |
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| 416 | return regmap_irq_get_virq(data: as3722->irq_data, irq); |
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| 417 | } |
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| 418 | #endif /* __LINUX_MFD_AS3722_H__ */ |
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| 419 | |
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