| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * DA9150 MFD Driver - Registers |
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| 4 | * |
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| 5 | * Copyright (c) 2014 Dialog Semiconductor |
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| 6 | * |
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| 7 | * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __DA9150_REGISTERS_H |
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| 11 | #define __DA9150_REGISTERS_H |
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| 12 | |
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| 13 | #include <linux/bitops.h> |
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| 14 | |
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| 15 | /* Registers */ |
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| 16 | #define DA9150_PAGE_CON 0x000 |
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| 17 | #define DA9150_STATUS_A 0x068 |
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| 18 | #define DA9150_STATUS_B 0x069 |
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| 19 | #define DA9150_STATUS_C 0x06A |
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| 20 | #define DA9150_STATUS_D 0x06B |
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| 21 | #define DA9150_STATUS_E 0x06C |
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| 22 | #define DA9150_STATUS_F 0x06D |
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| 23 | #define DA9150_STATUS_G 0x06E |
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| 24 | #define DA9150_STATUS_H 0x06F |
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| 25 | #define DA9150_STATUS_I 0x070 |
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| 26 | #define DA9150_STATUS_J 0x071 |
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| 27 | #define DA9150_STATUS_K 0x072 |
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| 28 | #define DA9150_STATUS_L 0x073 |
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| 29 | #define DA9150_STATUS_N 0x074 |
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| 30 | #define DA9150_FAULT_LOG_A 0x076 |
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| 31 | #define DA9150_FAULT_LOG_B 0x077 |
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| 32 | #define DA9150_EVENT_E 0x078 |
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| 33 | #define DA9150_EVENT_F 0x079 |
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| 34 | #define DA9150_EVENT_G 0x07A |
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| 35 | #define DA9150_EVENT_H 0x07B |
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| 36 | #define DA9150_IRQ_MASK_E 0x07C |
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| 37 | #define DA9150_IRQ_MASK_F 0x07D |
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| 38 | #define DA9150_IRQ_MASK_G 0x07E |
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| 39 | #define DA9150_IRQ_MASK_H 0x07F |
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| 40 | #define DA9150_PAGE_CON_1 0x080 |
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| 41 | #define DA9150_CONFIG_A 0x0E0 |
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| 42 | #define DA9150_CONFIG_B 0x0E1 |
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| 43 | #define DA9150_CONFIG_C 0x0E2 |
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| 44 | #define DA9150_CONFIG_D 0x0E3 |
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| 45 | #define DA9150_CONFIG_E 0x0E4 |
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| 46 | #define DA9150_CONTROL_A 0x0E5 |
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| 47 | #define DA9150_CONTROL_B 0x0E6 |
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| 48 | #define DA9150_CONTROL_C 0x0E7 |
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| 49 | #define DA9150_GPIO_A_B 0x0E8 |
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| 50 | #define DA9150_GPIO_C_D 0x0E9 |
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| 51 | #define DA9150_GPIO_MODE_CONT 0x0EA |
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| 52 | #define DA9150_GPIO_CTRL_B 0x0EB |
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| 53 | #define DA9150_GPIO_CTRL_A 0x0EC |
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| 54 | #define DA9150_GPIO_CTRL_C 0x0ED |
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| 55 | #define DA9150_GPIO_CFG_A 0x0EE |
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| 56 | #define DA9150_GPIO_CFG_B 0x0EF |
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| 57 | #define DA9150_GPIO_CFG_C 0x0F0 |
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| 58 | #define DA9150_GPADC_MAN 0x0F2 |
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| 59 | #define DA9150_GPADC_RES_A 0x0F4 |
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| 60 | #define DA9150_GPADC_RES_B 0x0F5 |
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| 61 | #define DA9150_PAGE_CON_2 0x100 |
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| 62 | #define DA9150_OTP_CONT_SHARED 0x101 |
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| 63 | #define DA9150_INTERFACE_SHARED 0x105 |
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| 64 | #define DA9150_CONFIG_A_SHARED 0x106 |
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| 65 | #define DA9150_CONFIG_D_SHARED 0x109 |
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| 66 | #define DA9150_ADETVB_CFG_C 0x150 |
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| 67 | #define DA9150_ADETD_STAT 0x151 |
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| 68 | #define DA9150_ADET_CMPSTAT 0x152 |
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| 69 | #define DA9150_ADET_CTRL_A 0x153 |
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| 70 | #define DA9150_ADETVB_CFG_B 0x154 |
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| 71 | #define DA9150_ADETVB_CFG_A 0x155 |
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| 72 | #define DA9150_ADETAC_CFG_A 0x156 |
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| 73 | #define DA9150_ADDETAC_CFG_B 0x157 |
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| 74 | #define DA9150_ADETAC_CFG_C 0x158 |
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| 75 | #define DA9150_ADETAC_CFG_D 0x159 |
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| 76 | #define DA9150_ADETVB_CFG_D 0x15A |
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| 77 | #define DA9150_ADETID_CFG_A 0x15B |
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| 78 | #define DA9150_ADET_RID_PT_CHG_H 0x15C |
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| 79 | #define DA9150_ADET_RID_PT_CHG_L 0x15D |
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| 80 | #define DA9150_PPR_TCTR_B 0x160 |
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| 81 | #define DA9150_PPR_BKCTRL_A 0x163 |
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| 82 | #define DA9150_PPR_BKCFG_A 0x164 |
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| 83 | #define DA9150_PPR_BKCFG_B 0x165 |
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| 84 | #define DA9150_PPR_CHGCTRL_A 0x166 |
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| 85 | #define DA9150_PPR_CHGCTRL_B 0x167 |
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| 86 | #define DA9150_PPR_CHGCTRL_C 0x168 |
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| 87 | #define DA9150_PPR_TCTR_A 0x169 |
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| 88 | #define DA9150_PPR_CHGCTRL_D 0x16A |
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| 89 | #define DA9150_PPR_CHGCTRL_E 0x16B |
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| 90 | #define DA9150_PPR_CHGCTRL_F 0x16C |
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| 91 | #define DA9150_PPR_CHGCTRL_G 0x16D |
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| 92 | #define DA9150_PPR_CHGCTRL_H 0x16E |
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| 93 | #define DA9150_PPR_CHGCTRL_I 0x16F |
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| 94 | #define DA9150_PPR_CHGCTRL_J 0x170 |
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| 95 | #define DA9150_PPR_CHGCTRL_K 0x171 |
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| 96 | #define DA9150_PPR_CHGCTRL_L 0x172 |
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| 97 | #define DA9150_PPR_CHGCTRL_M 0x173 |
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| 98 | #define DA9150_PPR_THYST_A 0x174 |
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| 99 | #define DA9150_PPR_THYST_B 0x175 |
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| 100 | #define DA9150_PPR_THYST_C 0x176 |
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| 101 | #define DA9150_PPR_THYST_D 0x177 |
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| 102 | #define DA9150_PPR_THYST_E 0x178 |
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| 103 | #define DA9150_PPR_THYST_F 0x179 |
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| 104 | #define DA9150_PPR_THYST_G 0x17A |
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| 105 | #define DA9150_PAGE_CON_3 0x180 |
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| 106 | #define DA9150_PAGE_CON_4 0x200 |
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| 107 | #define DA9150_PAGE_CON_5 0x280 |
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| 108 | #define DA9150_PAGE_CON_6 0x300 |
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| 109 | #define DA9150_COREBTLD_STAT_A 0x302 |
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| 110 | #define DA9150_COREBTLD_CTRL_A 0x303 |
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| 111 | #define DA9150_CORE_CONFIG_A 0x304 |
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| 112 | #define DA9150_CORE_CONFIG_C 0x305 |
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| 113 | #define DA9150_CORE_CONFIG_B 0x306 |
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| 114 | #define DA9150_CORE_CFG_DATA_A 0x307 |
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| 115 | #define DA9150_CORE_CFG_DATA_B 0x308 |
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| 116 | #define DA9150_CORE_CMD_A 0x309 |
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| 117 | #define DA9150_CORE_DATA_A 0x30A |
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| 118 | #define DA9150_CORE_DATA_B 0x30B |
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| 119 | #define DA9150_CORE_DATA_C 0x30C |
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| 120 | #define DA9150_CORE_DATA_D 0x30D |
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| 121 | #define DA9150_CORE2WIRE_STAT_A 0x310 |
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| 122 | #define DA9150_CORE2WIRE_CTRL_A 0x311 |
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| 123 | #define DA9150_FW_CTRL_A 0x312 |
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| 124 | #define DA9150_FW_CTRL_C 0x313 |
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| 125 | #define DA9150_FW_CTRL_D 0x314 |
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| 126 | #define DA9150_FG_CTRL_A 0x315 |
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| 127 | #define DA9150_FG_CTRL_B 0x316 |
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| 128 | #define DA9150_FW_CTRL_E 0x317 |
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| 129 | #define DA9150_FW_CTRL_B 0x318 |
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| 130 | #define DA9150_GPADC_CMAN 0x320 |
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| 131 | #define DA9150_GPADC_CRES_A 0x322 |
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| 132 | #define DA9150_GPADC_CRES_B 0x323 |
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| 133 | #define DA9150_CC_CFG_A 0x328 |
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| 134 | #define DA9150_CC_CFG_B 0x329 |
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| 135 | #define DA9150_CC_ICHG_RES_A 0x32A |
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| 136 | #define DA9150_CC_ICHG_RES_B 0x32B |
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| 137 | #define DA9150_CC_IAVG_RES_A 0x32C |
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| 138 | #define DA9150_CC_IAVG_RES_B 0x32D |
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| 139 | #define DA9150_TAUX_CTRL_A 0x330 |
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| 140 | #define DA9150_TAUX_RELOAD_H 0x332 |
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| 141 | #define DA9150_TAUX_RELOAD_L 0x333 |
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| 142 | #define DA9150_TAUX_VALUE_H 0x334 |
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| 143 | #define DA9150_TAUX_VALUE_L 0x335 |
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| 144 | #define DA9150_AUX_DATA_0 0x338 |
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| 145 | #define DA9150_AUX_DATA_1 0x339 |
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| 146 | #define DA9150_AUX_DATA_2 0x33A |
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| 147 | #define DA9150_AUX_DATA_3 0x33B |
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| 148 | #define DA9150_BIF_CTRL 0x340 |
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| 149 | #define DA9150_TBAT_CTRL_A 0x342 |
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| 150 | #define DA9150_TBAT_CTRL_B 0x343 |
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| 151 | #define DA9150_TBAT_RES_A 0x344 |
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| 152 | #define DA9150_TBAT_RES_B 0x345 |
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| 153 | |
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| 154 | /* DA9150_PAGE_CON = 0x000 */ |
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| 155 | #define DA9150_PAGE_SHIFT 0 |
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| 156 | #define DA9150_PAGE_MASK (0x3f << 0) |
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| 157 | #define DA9150_I2C_PAGE_SHIFT 1 |
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| 158 | #define DA9150_I2C_PAGE_MASK (0x1f << 1) |
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| 159 | #define DA9150_WRITE_MODE_SHIFT 6 |
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| 160 | #define DA9150_WRITE_MODE_MASK BIT(6) |
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| 161 | #define DA9150_REVERT_SHIFT 7 |
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| 162 | #define DA9150_REVERT_MASK BIT(7) |
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| 163 | |
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| 164 | /* DA9150_STATUS_A = 0x068 */ |
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| 165 | #define DA9150_WKUP_STAT_SHIFT 2 |
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| 166 | #define DA9150_WKUP_STAT_MASK (0x0f << 2) |
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| 167 | #define DA9150_SLEEP_STAT_SHIFT 6 |
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| 168 | #define DA9150_SLEEP_STAT_MASK (0x03 << 6) |
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| 169 | |
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| 170 | /* DA9150_STATUS_B = 0x069 */ |
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| 171 | #define DA9150_VFAULT_STAT_SHIFT 0 |
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| 172 | #define DA9150_VFAULT_STAT_MASK BIT(0) |
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| 173 | #define DA9150_TFAULT_STAT_SHIFT 1 |
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| 174 | #define DA9150_TFAULT_STAT_MASK BIT(1) |
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| 175 | |
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| 176 | /* DA9150_STATUS_C = 0x06A */ |
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| 177 | #define DA9150_VDD33_STAT_SHIFT 0 |
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| 178 | #define DA9150_VDD33_STAT_MASK BIT(0) |
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| 179 | #define DA9150_VDD33_SLEEP_SHIFT 1 |
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| 180 | #define DA9150_VDD33_SLEEP_MASK BIT(1) |
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| 181 | #define DA9150_LFOSC_STAT_SHIFT 7 |
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| 182 | #define DA9150_LFOSC_STAT_MASK BIT(7) |
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| 183 | |
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| 184 | /* DA9150_STATUS_D = 0x06B */ |
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| 185 | #define DA9150_GPIOA_STAT_SHIFT 0 |
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| 186 | #define DA9150_GPIOA_STAT_MASK BIT(0) |
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| 187 | #define DA9150_GPIOB_STAT_SHIFT 1 |
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| 188 | #define DA9150_GPIOB_STAT_MASK BIT(1) |
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| 189 | #define DA9150_GPIOC_STAT_SHIFT 2 |
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| 190 | #define DA9150_GPIOC_STAT_MASK BIT(2) |
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| 191 | #define DA9150_GPIOD_STAT_SHIFT 3 |
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| 192 | #define DA9150_GPIOD_STAT_MASK BIT(3) |
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| 193 | |
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| 194 | /* DA9150_STATUS_E = 0x06C */ |
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| 195 | #define DA9150_DTYPE_SHIFT 0 |
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| 196 | #define DA9150_DTYPE_MASK (0x1f << 0) |
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| 197 | #define DA9150_DTYPE_DT_NIL (0x00 << 0) |
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| 198 | #define DA9150_DTYPE_DT_USB_OTG BIT(0) |
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| 199 | #define DA9150_DTYPE_DT_USB_STD (0x02 << 0) |
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| 200 | #define DA9150_DTYPE_DT_USB_CHG (0x03 << 0) |
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| 201 | #define DA9150_DTYPE_DT_ACA_CHG (0x04 << 0) |
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| 202 | #define DA9150_DTYPE_DT_ACA_OTG (0x05 << 0) |
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| 203 | #define DA9150_DTYPE_DT_ACA_DOC (0x06 << 0) |
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| 204 | #define DA9150_DTYPE_DT_DED_CHG (0x07 << 0) |
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| 205 | #define DA9150_DTYPE_DT_CR5_CHG (0x08 << 0) |
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| 206 | #define DA9150_DTYPE_DT_CR4_CHG (0x0c << 0) |
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| 207 | #define DA9150_DTYPE_DT_PT_CHG (0x11 << 0) |
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| 208 | #define DA9150_DTYPE_DT_NN_ACC (0x16 << 0) |
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| 209 | #define DA9150_DTYPE_DT_NN_CHG (0x17 << 0) |
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| 210 | |
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| 211 | /* DA9150_STATUS_F = 0x06D */ |
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| 212 | #define DA9150_SESS_VLD_SHIFT 0 |
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| 213 | #define DA9150_SESS_VLD_MASK BIT(0) |
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| 214 | #define DA9150_ID_ERR_SHIFT 1 |
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| 215 | #define DA9150_ID_ERR_MASK BIT(1) |
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| 216 | #define DA9150_PT_CHG_SHIFT 2 |
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| 217 | #define DA9150_PT_CHG_MASK BIT(2) |
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| 218 | |
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| 219 | /* DA9150_STATUS_G = 0x06E */ |
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| 220 | #define DA9150_RID_SHIFT 0 |
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| 221 | #define DA9150_RID_MASK (0xff << 0) |
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| 222 | |
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| 223 | /* DA9150_STATUS_H = 0x06F */ |
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| 224 | #define DA9150_VBUS_STAT_SHIFT 0 |
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| 225 | #define DA9150_VBUS_STAT_MASK (0x07 << 0) |
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| 226 | #define DA9150_VBUS_STAT_OFF (0x00 << 0) |
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| 227 | #define DA9150_VBUS_STAT_WAIT BIT(0) |
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| 228 | #define DA9150_VBUS_STAT_CHG (0x02 << 0) |
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| 229 | #define DA9150_VBUS_TRED_SHIFT 3 |
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| 230 | #define DA9150_VBUS_TRED_MASK BIT(3) |
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| 231 | #define DA9150_VBUS_DROP_STAT_SHIFT 4 |
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| 232 | #define DA9150_VBUS_DROP_STAT_MASK (0x0f << 4) |
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| 233 | |
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| 234 | /* DA9150_STATUS_I = 0x070 */ |
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| 235 | #define DA9150_VBUS_ISET_STAT_SHIFT 0 |
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| 236 | #define DA9150_VBUS_ISET_STAT_MASK (0x1f << 0) |
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| 237 | #define DA9150_VBUS_OT_SHIFT 7 |
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| 238 | #define DA9150_VBUS_OT_MASK BIT(7) |
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| 239 | |
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| 240 | /* DA9150_STATUS_J = 0x071 */ |
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| 241 | #define DA9150_CHG_STAT_SHIFT 0 |
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| 242 | #define DA9150_CHG_STAT_MASK (0x0f << 0) |
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| 243 | #define DA9150_CHG_STAT_OFF (0x00 << 0) |
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| 244 | #define DA9150_CHG_STAT_SUSP BIT(0) |
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| 245 | #define DA9150_CHG_STAT_ACT (0x02 << 0) |
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| 246 | #define DA9150_CHG_STAT_PRE (0x03 << 0) |
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| 247 | #define DA9150_CHG_STAT_CC (0x04 << 0) |
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| 248 | #define DA9150_CHG_STAT_CV (0x05 << 0) |
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| 249 | #define DA9150_CHG_STAT_FULL (0x06 << 0) |
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| 250 | #define DA9150_CHG_STAT_TEMP (0x07 << 0) |
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| 251 | #define DA9150_CHG_STAT_TIME (0x08 << 0) |
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| 252 | #define DA9150_CHG_STAT_BAT (0x09 << 0) |
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| 253 | #define DA9150_CHG_TEMP_SHIFT 4 |
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| 254 | #define DA9150_CHG_TEMP_MASK (0x07 << 4) |
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| 255 | #define DA9150_CHG_TEMP_UNDER (0x06 << 4) |
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| 256 | #define DA9150_CHG_TEMP_OVER (0x07 << 4) |
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| 257 | #define DA9150_CHG_IEND_STAT_SHIFT 7 |
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| 258 | #define DA9150_CHG_IEND_STAT_MASK BIT(7) |
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| 259 | |
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| 260 | /* DA9150_STATUS_K = 0x072 */ |
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| 261 | #define DA9150_CHG_IAV_H_SHIFT 0 |
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| 262 | #define DA9150_CHG_IAV_H_MASK (0xff << 0) |
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| 263 | |
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| 264 | /* DA9150_STATUS_L = 0x073 */ |
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| 265 | #define DA9150_CHG_IAV_L_SHIFT 5 |
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| 266 | #define DA9150_CHG_IAV_L_MASK (0x07 << 5) |
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| 267 | |
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| 268 | /* DA9150_STATUS_N = 0x074 */ |
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| 269 | #define DA9150_CHG_TIME_SHIFT 1 |
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| 270 | #define DA9150_CHG_TIME_MASK BIT(1) |
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| 271 | #define DA9150_CHG_TRED_SHIFT 2 |
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| 272 | #define DA9150_CHG_TRED_MASK BIT(2) |
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| 273 | #define DA9150_CHG_TJUNC_CLASS_SHIFT 3 |
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| 274 | #define DA9150_CHG_TJUNC_CLASS_MASK (0x07 << 3) |
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| 275 | #define DA9150_CHG_TJUNC_CLASS_6 (0x06 << 3) |
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| 276 | #define DA9150_EBS_STAT_SHIFT 6 |
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| 277 | #define DA9150_EBS_STAT_MASK BIT(6) |
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| 278 | #define DA9150_CHG_BAT_REMOVED_SHIFT 7 |
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| 279 | #define DA9150_CHG_BAT_REMOVED_MASK BIT(7) |
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| 280 | |
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| 281 | /* DA9150_FAULT_LOG_A = 0x076 */ |
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| 282 | #define DA9150_TEMP_FAULT_SHIFT 0 |
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| 283 | #define DA9150_TEMP_FAULT_MASK BIT(0) |
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| 284 | #define DA9150_VSYS_FAULT_SHIFT 1 |
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| 285 | #define DA9150_VSYS_FAULT_MASK BIT(1) |
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| 286 | #define DA9150_START_FAULT_SHIFT 2 |
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| 287 | #define DA9150_START_FAULT_MASK BIT(2) |
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| 288 | #define DA9150_EXT_FAULT_SHIFT 3 |
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| 289 | #define DA9150_EXT_FAULT_MASK BIT(3) |
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| 290 | #define DA9150_POR_FAULT_SHIFT 4 |
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| 291 | #define DA9150_POR_FAULT_MASK BIT(4) |
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| 292 | |
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| 293 | /* DA9150_FAULT_LOG_B = 0x077 */ |
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| 294 | #define DA9150_VBUS_FAULT_SHIFT 0 |
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| 295 | #define DA9150_VBUS_FAULT_MASK BIT(0) |
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| 296 | #define DA9150_OTG_FAULT_SHIFT 1 |
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| 297 | #define DA9150_OTG_FAULT_MASK BIT(1) |
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| 298 | |
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| 299 | /* DA9150_EVENT_E = 0x078 */ |
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| 300 | #define DA9150_E_VBUS_SHIFT 0 |
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| 301 | #define DA9150_E_VBUS_MASK BIT(0) |
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| 302 | #define DA9150_E_CHG_SHIFT 1 |
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| 303 | #define DA9150_E_CHG_MASK BIT(1) |
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| 304 | #define DA9150_E_TCLASS_SHIFT 2 |
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| 305 | #define DA9150_E_TCLASS_MASK BIT(2) |
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| 306 | #define DA9150_E_TJUNC_SHIFT 3 |
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| 307 | #define DA9150_E_TJUNC_MASK BIT(3) |
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| 308 | #define DA9150_E_VFAULT_SHIFT 4 |
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| 309 | #define DA9150_E_VFAULT_MASK BIT(4) |
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| 310 | #define DA9150_EVENTS_H_SHIFT 5 |
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| 311 | #define DA9150_EVENTS_H_MASK BIT(5) |
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| 312 | #define DA9150_EVENTS_G_SHIFT 6 |
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| 313 | #define DA9150_EVENTS_G_MASK BIT(6) |
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| 314 | #define DA9150_EVENTS_F_SHIFT 7 |
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| 315 | #define DA9150_EVENTS_F_MASK BIT(7) |
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| 316 | |
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| 317 | /* DA9150_EVENT_F = 0x079 */ |
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| 318 | #define DA9150_E_CONF_SHIFT 0 |
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| 319 | #define DA9150_E_CONF_MASK BIT(0) |
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| 320 | #define DA9150_E_DAT_SHIFT 1 |
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| 321 | #define DA9150_E_DAT_MASK BIT(1) |
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| 322 | #define DA9150_E_DTYPE_SHIFT 3 |
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| 323 | #define DA9150_E_DTYPE_MASK BIT(3) |
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| 324 | #define DA9150_E_ID_SHIFT 4 |
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| 325 | #define DA9150_E_ID_MASK BIT(4) |
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| 326 | #define DA9150_E_ADP_SHIFT 5 |
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| 327 | #define DA9150_E_ADP_MASK BIT(5) |
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| 328 | #define DA9150_E_SESS_END_SHIFT 6 |
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| 329 | #define DA9150_E_SESS_END_MASK BIT(6) |
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| 330 | #define DA9150_E_SESS_VLD_SHIFT 7 |
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| 331 | #define DA9150_E_SESS_VLD_MASK BIT(7) |
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| 332 | |
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| 333 | /* DA9150_EVENT_G = 0x07A */ |
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| 334 | #define DA9150_E_FG_SHIFT 0 |
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| 335 | #define DA9150_E_FG_MASK BIT(0) |
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| 336 | #define DA9150_E_GP_SHIFT 1 |
|---|
| 337 | #define DA9150_E_GP_MASK BIT(1) |
|---|
| 338 | #define DA9150_E_TBAT_SHIFT 2 |
|---|
| 339 | #define DA9150_E_TBAT_MASK BIT(2) |
|---|
| 340 | #define DA9150_E_GPIOA_SHIFT 3 |
|---|
| 341 | #define DA9150_E_GPIOA_MASK BIT(3) |
|---|
| 342 | #define DA9150_E_GPIOB_SHIFT 4 |
|---|
| 343 | #define DA9150_E_GPIOB_MASK BIT(4) |
|---|
| 344 | #define DA9150_E_GPIOC_SHIFT 5 |
|---|
| 345 | #define DA9150_E_GPIOC_MASK BIT(5) |
|---|
| 346 | #define DA9150_E_GPIOD_SHIFT 6 |
|---|
| 347 | #define DA9150_E_GPIOD_MASK BIT(6) |
|---|
| 348 | #define DA9150_E_GPADC_SHIFT 7 |
|---|
| 349 | #define DA9150_E_GPADC_MASK BIT(7) |
|---|
| 350 | |
|---|
| 351 | /* DA9150_EVENT_H = 0x07B */ |
|---|
| 352 | #define DA9150_E_WKUP_SHIFT 0 |
|---|
| 353 | #define DA9150_E_WKUP_MASK BIT(0) |
|---|
| 354 | |
|---|
| 355 | /* DA9150_IRQ_MASK_E = 0x07C */ |
|---|
| 356 | #define DA9150_M_VBUS_SHIFT 0 |
|---|
| 357 | #define DA9150_M_VBUS_MASK BIT(0) |
|---|
| 358 | #define DA9150_M_CHG_SHIFT 1 |
|---|
| 359 | #define DA9150_M_CHG_MASK BIT(1) |
|---|
| 360 | #define DA9150_M_TJUNC_SHIFT 3 |
|---|
| 361 | #define DA9150_M_TJUNC_MASK BIT(3) |
|---|
| 362 | #define DA9150_M_VFAULT_SHIFT 4 |
|---|
| 363 | #define DA9150_M_VFAULT_MASK BIT(4) |
|---|
| 364 | |
|---|
| 365 | /* DA9150_IRQ_MASK_F = 0x07D */ |
|---|
| 366 | #define DA9150_M_CONF_SHIFT 0 |
|---|
| 367 | #define DA9150_M_CONF_MASK BIT(0) |
|---|
| 368 | #define DA9150_M_DAT_SHIFT 1 |
|---|
| 369 | #define DA9150_M_DAT_MASK BIT(1) |
|---|
| 370 | #define DA9150_M_DTYPE_SHIFT 3 |
|---|
| 371 | #define DA9150_M_DTYPE_MASK BIT(3) |
|---|
| 372 | #define DA9150_M_ID_SHIFT 4 |
|---|
| 373 | #define DA9150_M_ID_MASK BIT(4) |
|---|
| 374 | #define DA9150_M_ADP_SHIFT 5 |
|---|
| 375 | #define DA9150_M_ADP_MASK BIT(5) |
|---|
| 376 | #define DA9150_M_SESS_END_SHIFT 6 |
|---|
| 377 | #define DA9150_M_SESS_END_MASK BIT(6) |
|---|
| 378 | #define DA9150_M_SESS_VLD_SHIFT 7 |
|---|
| 379 | #define DA9150_M_SESS_VLD_MASK BIT(7) |
|---|
| 380 | |
|---|
| 381 | /* DA9150_IRQ_MASK_G = 0x07E */ |
|---|
| 382 | #define DA9150_M_FG_SHIFT 0 |
|---|
| 383 | #define DA9150_M_FG_MASK BIT(0) |
|---|
| 384 | #define DA9150_M_GP_SHIFT 1 |
|---|
| 385 | #define DA9150_M_GP_MASK BIT(1) |
|---|
| 386 | #define DA9150_M_TBAT_SHIFT 2 |
|---|
| 387 | #define DA9150_M_TBAT_MASK BIT(2) |
|---|
| 388 | #define DA9150_M_GPIOA_SHIFT 3 |
|---|
| 389 | #define DA9150_M_GPIOA_MASK BIT(3) |
|---|
| 390 | #define DA9150_M_GPIOB_SHIFT 4 |
|---|
| 391 | #define DA9150_M_GPIOB_MASK BIT(4) |
|---|
| 392 | #define DA9150_M_GPIOC_SHIFT 5 |
|---|
| 393 | #define DA9150_M_GPIOC_MASK BIT(5) |
|---|
| 394 | #define DA9150_M_GPIOD_SHIFT 6 |
|---|
| 395 | #define DA9150_M_GPIOD_MASK BIT(6) |
|---|
| 396 | #define DA9150_M_GPADC_SHIFT 7 |
|---|
| 397 | #define DA9150_M_GPADC_MASK BIT(7) |
|---|
| 398 | |
|---|
| 399 | /* DA9150_IRQ_MASK_H = 0x07F */ |
|---|
| 400 | #define DA9150_M_WKUP_SHIFT 0 |
|---|
| 401 | #define DA9150_M_WKUP_MASK BIT(0) |
|---|
| 402 | |
|---|
| 403 | /* DA9150_PAGE_CON_1 = 0x080 */ |
|---|
| 404 | #define DA9150_PAGE_SHIFT 0 |
|---|
| 405 | #define DA9150_PAGE_MASK (0x3f << 0) |
|---|
| 406 | #define DA9150_WRITE_MODE_SHIFT 6 |
|---|
| 407 | #define DA9150_WRITE_MODE_MASK BIT(6) |
|---|
| 408 | #define DA9150_REVERT_SHIFT 7 |
|---|
| 409 | #define DA9150_REVERT_MASK BIT(7) |
|---|
| 410 | |
|---|
| 411 | /* DA9150_CONFIG_A = 0x0E0 */ |
|---|
| 412 | #define DA9150_RESET_DUR_SHIFT 0 |
|---|
| 413 | #define DA9150_RESET_DUR_MASK (0x03 << 0) |
|---|
| 414 | #define DA9150_RESET_EXT_SHIFT 2 |
|---|
| 415 | #define DA9150_RESET_EXT_MASK (0x03 << 2) |
|---|
| 416 | #define DA9150_START_MAX_SHIFT 4 |
|---|
| 417 | #define DA9150_START_MAX_MASK (0x03 << 4) |
|---|
| 418 | #define DA9150_PS_WAIT_EN_SHIFT 6 |
|---|
| 419 | #define DA9150_PS_WAIT_EN_MASK BIT(6) |
|---|
| 420 | #define DA9150_PS_DISABLE_DIRECT_SHIFT 7 |
|---|
| 421 | #define DA9150_PS_DISABLE_DIRECT_MASK BIT(7) |
|---|
| 422 | |
|---|
| 423 | /* DA9150_CONFIG_B = 0x0E1 */ |
|---|
| 424 | #define DA9150_VFAULT_ADJ_SHIFT 0 |
|---|
| 425 | #define DA9150_VFAULT_ADJ_MASK (0x0f << 0) |
|---|
| 426 | #define DA9150_VFAULT_HYST_SHIFT 4 |
|---|
| 427 | #define DA9150_VFAULT_HYST_MASK (0x07 << 4) |
|---|
| 428 | #define DA9150_VFAULT_EN_SHIFT 7 |
|---|
| 429 | #define DA9150_VFAULT_EN_MASK BIT(7) |
|---|
| 430 | |
|---|
| 431 | /* DA9150_CONFIG_C = 0x0E2 */ |
|---|
| 432 | #define DA9150_VSYS_MIN_SHIFT 3 |
|---|
| 433 | #define DA9150_VSYS_MIN_MASK (0x1f << 3) |
|---|
| 434 | |
|---|
| 435 | /* DA9150_CONFIG_D = 0x0E3 */ |
|---|
| 436 | #define DA9150_LFOSC_EXT_SHIFT 0 |
|---|
| 437 | #define DA9150_LFOSC_EXT_MASK BIT(0) |
|---|
| 438 | #define DA9150_VDD33_DWN_SHIFT 1 |
|---|
| 439 | #define DA9150_VDD33_DWN_MASK BIT(1) |
|---|
| 440 | #define DA9150_WKUP_PM_EN_SHIFT 2 |
|---|
| 441 | #define DA9150_WKUP_PM_EN_MASK BIT(2) |
|---|
| 442 | #define DA9150_WKUP_CE_SEL_SHIFT 3 |
|---|
| 443 | #define DA9150_WKUP_CE_SEL_MASK (0x03 << 3) |
|---|
| 444 | #define DA9150_WKUP_CLK32K_EN_SHIFT 5 |
|---|
| 445 | #define DA9150_WKUP_CLK32K_EN_MASK BIT(5) |
|---|
| 446 | #define DA9150_DISABLE_DEL_SHIFT 7 |
|---|
| 447 | #define DA9150_DISABLE_DEL_MASK BIT(7) |
|---|
| 448 | |
|---|
| 449 | /* DA9150_CONFIG_E = 0x0E4 */ |
|---|
| 450 | #define DA9150_PM_SPKSUP_DIS_SHIFT 0 |
|---|
| 451 | #define DA9150_PM_SPKSUP_DIS_MASK BIT(0) |
|---|
| 452 | #define DA9150_PM_MERGE_SHIFT 1 |
|---|
| 453 | #define DA9150_PM_MERGE_MASK BIT(1) |
|---|
| 454 | #define DA9150_PM_SR_OFF_SHIFT 2 |
|---|
| 455 | #define DA9150_PM_SR_OFF_MASK BIT(2) |
|---|
| 456 | #define DA9150_PM_TIMEOUT_EN_SHIFT 3 |
|---|
| 457 | #define DA9150_PM_TIMEOUT_EN_MASK BIT(3) |
|---|
| 458 | #define DA9150_PM_DLY_SEL_SHIFT 4 |
|---|
| 459 | #define DA9150_PM_DLY_SEL_MASK (0x07 << 4) |
|---|
| 460 | #define DA9150_PM_OUT_DLY_SEL_SHIFT 7 |
|---|
| 461 | #define DA9150_PM_OUT_DLY_SEL_MASK BIT(7) |
|---|
| 462 | |
|---|
| 463 | /* DA9150_CONTROL_A = 0x0E5 */ |
|---|
| 464 | #define DA9150_VDD33_SL_SHIFT 0 |
|---|
| 465 | #define DA9150_VDD33_SL_MASK BIT(0) |
|---|
| 466 | #define DA9150_VDD33_LPM_SHIFT 1 |
|---|
| 467 | #define DA9150_VDD33_LPM_MASK (0x03 << 1) |
|---|
| 468 | #define DA9150_VDD33_EN_SHIFT 3 |
|---|
| 469 | #define DA9150_VDD33_EN_MASK BIT(3) |
|---|
| 470 | #define DA9150_GPI_LPM_SHIFT 6 |
|---|
| 471 | #define DA9150_GPI_LPM_MASK BIT(6) |
|---|
| 472 | #define DA9150_PM_IF_LPM_SHIFT 7 |
|---|
| 473 | #define DA9150_PM_IF_LPM_MASK BIT(7) |
|---|
| 474 | |
|---|
| 475 | /* DA9150_CONTROL_B = 0x0E6 */ |
|---|
| 476 | #define DA9150_LPM_SHIFT 0 |
|---|
| 477 | #define DA9150_LPM_MASK BIT(0) |
|---|
| 478 | #define DA9150_RESET_SHIFT 1 |
|---|
| 479 | #define DA9150_RESET_MASK BIT(1) |
|---|
| 480 | #define DA9150_RESET_USRCONF_EN_SHIFT 2 |
|---|
| 481 | #define DA9150_RESET_USRCONF_EN_MASK BIT(2) |
|---|
| 482 | |
|---|
| 483 | /* DA9150_CONTROL_C = 0x0E7 */ |
|---|
| 484 | #define DA9150_DISABLE_SHIFT 0 |
|---|
| 485 | #define DA9150_DISABLE_MASK BIT(0) |
|---|
| 486 | |
|---|
| 487 | /* DA9150_GPIO_A_B = 0x0E8 */ |
|---|
| 488 | #define DA9150_GPIOA_PIN_SHIFT 0 |
|---|
| 489 | #define DA9150_GPIOA_PIN_MASK (0x07 << 0) |
|---|
| 490 | #define DA9150_GPIOA_PIN_GPI (0x00 << 0) |
|---|
| 491 | #define DA9150_GPIOA_PIN_GPO_OD BIT(0) |
|---|
| 492 | #define DA9150_GPIOA_TYPE_SHIFT 3 |
|---|
| 493 | #define DA9150_GPIOA_TYPE_MASK BIT(3) |
|---|
| 494 | #define DA9150_GPIOB_PIN_SHIFT 4 |
|---|
| 495 | #define DA9150_GPIOB_PIN_MASK (0x07 << 4) |
|---|
| 496 | #define DA9150_GPIOB_PIN_GPI (0x00 << 4) |
|---|
| 497 | #define DA9150_GPIOB_PIN_GPO_OD BIT(4) |
|---|
| 498 | #define DA9150_GPIOB_TYPE_SHIFT 7 |
|---|
| 499 | #define DA9150_GPIOB_TYPE_MASK BIT(7) |
|---|
| 500 | |
|---|
| 501 | /* DA9150_GPIO_C_D = 0x0E9 */ |
|---|
| 502 | #define DA9150_GPIOC_PIN_SHIFT 0 |
|---|
| 503 | #define DA9150_GPIOC_PIN_MASK (0x07 << 0) |
|---|
| 504 | #define DA9150_GPIOC_PIN_GPI (0x00 << 0) |
|---|
| 505 | #define DA9150_GPIOC_PIN_GPO_OD BIT(0) |
|---|
| 506 | #define DA9150_GPIOC_TYPE_SHIFT 3 |
|---|
| 507 | #define DA9150_GPIOC_TYPE_MASK BIT(3) |
|---|
| 508 | #define DA9150_GPIOD_PIN_SHIFT 4 |
|---|
| 509 | #define DA9150_GPIOD_PIN_MASK (0x07 << 4) |
|---|
| 510 | #define DA9150_GPIOD_PIN_GPI (0x00 << 4) |
|---|
| 511 | #define DA9150_GPIOD_PIN_GPO_OD BIT(4) |
|---|
| 512 | #define DA9150_GPIOD_TYPE_SHIFT 7 |
|---|
| 513 | #define DA9150_GPIOD_TYPE_MASK BIT(7) |
|---|
| 514 | |
|---|
| 515 | /* DA9150_GPIO_MODE_CONT = 0x0EA */ |
|---|
| 516 | #define DA9150_GPIOA_MODE_SHIFT 0 |
|---|
| 517 | #define DA9150_GPIOA_MODE_MASK BIT(0) |
|---|
| 518 | #define DA9150_GPIOB_MODE_SHIFT 1 |
|---|
| 519 | #define DA9150_GPIOB_MODE_MASK BIT(1) |
|---|
| 520 | #define DA9150_GPIOC_MODE_SHIFT 2 |
|---|
| 521 | #define DA9150_GPIOC_MODE_MASK BIT(2) |
|---|
| 522 | #define DA9150_GPIOD_MODE_SHIFT 3 |
|---|
| 523 | #define DA9150_GPIOD_MODE_MASK BIT(3) |
|---|
| 524 | #define DA9150_GPIOA_CONT_SHIFT 4 |
|---|
| 525 | #define DA9150_GPIOA_CONT_MASK BIT(4) |
|---|
| 526 | #define DA9150_GPIOB_CONT_SHIFT 5 |
|---|
| 527 | #define DA9150_GPIOB_CONT_MASK BIT(5) |
|---|
| 528 | #define DA9150_GPIOC_CONT_SHIFT 6 |
|---|
| 529 | #define DA9150_GPIOC_CONT_MASK BIT(6) |
|---|
| 530 | #define DA9150_GPIOD_CONT_SHIFT 7 |
|---|
| 531 | #define DA9150_GPIOD_CONT_MASK BIT(7) |
|---|
| 532 | |
|---|
| 533 | /* DA9150_GPIO_CTRL_B = 0x0EB */ |
|---|
| 534 | #define DA9150_WAKE_PIN_SHIFT 0 |
|---|
| 535 | #define DA9150_WAKE_PIN_MASK (0x03 << 0) |
|---|
| 536 | #define DA9150_WAKE_MODE_SHIFT 2 |
|---|
| 537 | #define DA9150_WAKE_MODE_MASK BIT(2) |
|---|
| 538 | #define DA9150_WAKE_CONT_SHIFT 3 |
|---|
| 539 | #define DA9150_WAKE_CONT_MASK BIT(3) |
|---|
| 540 | #define DA9150_WAKE_DLY_SHIFT 4 |
|---|
| 541 | #define DA9150_WAKE_DLY_MASK BIT(4) |
|---|
| 542 | |
|---|
| 543 | /* DA9150_GPIO_CTRL_A = 0x0EC */ |
|---|
| 544 | #define DA9150_GPIOA_ANAEN_SHIFT 0 |
|---|
| 545 | #define DA9150_GPIOA_ANAEN_MASK BIT(0) |
|---|
| 546 | #define DA9150_GPIOB_ANAEN_SHIFT 1 |
|---|
| 547 | #define DA9150_GPIOB_ANAEN_MASK BIT(1) |
|---|
| 548 | #define DA9150_GPIOC_ANAEN_SHIFT 2 |
|---|
| 549 | #define DA9150_GPIOC_ANAEN_MASK BIT(2) |
|---|
| 550 | #define DA9150_GPIOD_ANAEN_SHIFT 3 |
|---|
| 551 | #define DA9150_GPIOD_ANAEN_MASK BIT(3) |
|---|
| 552 | #define DA9150_GPIO_ANAEN 0x01 |
|---|
| 553 | #define DA9150_GPIO_ANAEN_MASK 0x0F |
|---|
| 554 | #define DA9150_CHGLED_PIN_SHIFT 5 |
|---|
| 555 | #define DA9150_CHGLED_PIN_MASK (0x07 << 5) |
|---|
| 556 | |
|---|
| 557 | /* DA9150_GPIO_CTRL_C = 0x0ED */ |
|---|
| 558 | #define DA9150_CHGBL_DUR_SHIFT 0 |
|---|
| 559 | #define DA9150_CHGBL_DUR_MASK (0x03 << 0) |
|---|
| 560 | #define DA9150_CHGBL_DBL_SHIFT 2 |
|---|
| 561 | #define DA9150_CHGBL_DBL_MASK BIT(2) |
|---|
| 562 | #define DA9150_CHGBL_FRQ_SHIFT 3 |
|---|
| 563 | #define DA9150_CHGBL_FRQ_MASK (0x03 << 3) |
|---|
| 564 | #define DA9150_CHGBL_FLKR_SHIFT 5 |
|---|
| 565 | #define DA9150_CHGBL_FLKR_MASK BIT(5) |
|---|
| 566 | |
|---|
| 567 | /* DA9150_GPIO_CFG_A = 0x0EE */ |
|---|
| 568 | #define DA9150_CE_LPM_DEB_SHIFT 0 |
|---|
| 569 | #define DA9150_CE_LPM_DEB_MASK (0x07 << 0) |
|---|
| 570 | |
|---|
| 571 | /* DA9150_GPIO_CFG_B = 0x0EF */ |
|---|
| 572 | #define DA9150_GPIOA_PUPD_SHIFT 0 |
|---|
| 573 | #define DA9150_GPIOA_PUPD_MASK BIT(0) |
|---|
| 574 | #define DA9150_GPIOB_PUPD_SHIFT 1 |
|---|
| 575 | #define DA9150_GPIOB_PUPD_MASK BIT(1) |
|---|
| 576 | #define DA9150_GPIOC_PUPD_SHIFT 2 |
|---|
| 577 | #define DA9150_GPIOC_PUPD_MASK BIT(2) |
|---|
| 578 | #define DA9150_GPIOD_PUPD_SHIFT 3 |
|---|
| 579 | #define DA9150_GPIOD_PUPD_MASK BIT(3) |
|---|
| 580 | #define DA9150_GPIO_PUPD_MASK (0xF << 0) |
|---|
| 581 | #define DA9150_GPI_DEB_SHIFT 4 |
|---|
| 582 | #define DA9150_GPI_DEB_MASK (0x07 << 4) |
|---|
| 583 | #define DA9150_LPM_EN_SHIFT 7 |
|---|
| 584 | #define DA9150_LPM_EN_MASK BIT(7) |
|---|
| 585 | |
|---|
| 586 | /* DA9150_GPIO_CFG_C = 0x0F0 */ |
|---|
| 587 | #define DA9150_GPI_V_SHIFT 0 |
|---|
| 588 | #define DA9150_GPI_V_MASK BIT(0) |
|---|
| 589 | #define DA9150_VDDIO_INT_SHIFT 1 |
|---|
| 590 | #define DA9150_VDDIO_INT_MASK BIT(1) |
|---|
| 591 | #define DA9150_FAULT_PIN_SHIFT 3 |
|---|
| 592 | #define DA9150_FAULT_PIN_MASK (0x07 << 3) |
|---|
| 593 | #define DA9150_FAULT_TYPE_SHIFT 6 |
|---|
| 594 | #define DA9150_FAULT_TYPE_MASK BIT(6) |
|---|
| 595 | #define DA9150_NIRQ_PUPD_SHIFT 7 |
|---|
| 596 | #define DA9150_NIRQ_PUPD_MASK BIT(7) |
|---|
| 597 | |
|---|
| 598 | /* DA9150_GPADC_MAN = 0x0F2 */ |
|---|
| 599 | #define DA9150_GPADC_EN_SHIFT 0 |
|---|
| 600 | #define DA9150_GPADC_EN_MASK BIT(0) |
|---|
| 601 | #define DA9150_GPADC_MUX_SHIFT 1 |
|---|
| 602 | #define DA9150_GPADC_MUX_MASK (0x1f << 1) |
|---|
| 603 | |
|---|
| 604 | /* DA9150_GPADC_RES_A = 0x0F4 */ |
|---|
| 605 | #define DA9150_GPADC_RES_H_SHIFT 0 |
|---|
| 606 | #define DA9150_GPADC_RES_H_MASK (0xff << 0) |
|---|
| 607 | |
|---|
| 608 | /* DA9150_GPADC_RES_B = 0x0F5 */ |
|---|
| 609 | #define DA9150_GPADC_RUN_SHIFT 0 |
|---|
| 610 | #define DA9150_GPADC_RUN_MASK BIT(0) |
|---|
| 611 | #define DA9150_GPADC_RES_L_SHIFT 6 |
|---|
| 612 | #define DA9150_GPADC_RES_L_MASK (0x03 << 6) |
|---|
| 613 | #define DA9150_GPADC_RES_L_BITS 2 |
|---|
| 614 | |
|---|
| 615 | /* DA9150_PAGE_CON_2 = 0x100 */ |
|---|
| 616 | #define DA9150_PAGE_SHIFT 0 |
|---|
| 617 | #define DA9150_PAGE_MASK (0x3f << 0) |
|---|
| 618 | #define DA9150_WRITE_MODE_SHIFT 6 |
|---|
| 619 | #define DA9150_WRITE_MODE_MASK BIT(6) |
|---|
| 620 | #define DA9150_REVERT_SHIFT 7 |
|---|
| 621 | #define DA9150_REVERT_MASK BIT(7) |
|---|
| 622 | |
|---|
| 623 | /* DA9150_OTP_CONT_SHARED = 0x101 */ |
|---|
| 624 | #define DA9150_PC_DONE_SHIFT 3 |
|---|
| 625 | #define DA9150_PC_DONE_MASK BIT(3) |
|---|
| 626 | |
|---|
| 627 | /* DA9150_INTERFACE_SHARED = 0x105 */ |
|---|
| 628 | #define DA9150_IF_BASE_ADDR_SHIFT 4 |
|---|
| 629 | #define DA9150_IF_BASE_ADDR_MASK (0x0f << 4) |
|---|
| 630 | |
|---|
| 631 | /* DA9150_CONFIG_A_SHARED = 0x106 */ |
|---|
| 632 | #define DA9150_NIRQ_VDD_SHIFT 1 |
|---|
| 633 | #define DA9150_NIRQ_VDD_MASK BIT(1) |
|---|
| 634 | #define DA9150_NIRQ_PIN_SHIFT 2 |
|---|
| 635 | #define DA9150_NIRQ_PIN_MASK BIT(2) |
|---|
| 636 | #define DA9150_NIRQ_TYPE_SHIFT 3 |
|---|
| 637 | #define DA9150_NIRQ_TYPE_MASK BIT(3) |
|---|
| 638 | #define DA9150_PM_IF_V_SHIFT 4 |
|---|
| 639 | #define DA9150_PM_IF_V_MASK BIT(4) |
|---|
| 640 | #define DA9150_PM_IF_FMP_SHIFT 5 |
|---|
| 641 | #define DA9150_PM_IF_FMP_MASK BIT(5) |
|---|
| 642 | #define DA9150_PM_IF_HSM_SHIFT 6 |
|---|
| 643 | #define DA9150_PM_IF_HSM_MASK BIT(6) |
|---|
| 644 | |
|---|
| 645 | /* DA9150_CONFIG_D_SHARED = 0x109 */ |
|---|
| 646 | #define DA9150_NIRQ_MODE_SHIFT 1 |
|---|
| 647 | #define DA9150_NIRQ_MODE_MASK BIT(1) |
|---|
| 648 | |
|---|
| 649 | /* DA9150_ADETVB_CFG_C = 0x150 */ |
|---|
| 650 | #define DA9150_TADP_RISE_SHIFT 0 |
|---|
| 651 | #define DA9150_TADP_RISE_MASK (0xff << 0) |
|---|
| 652 | |
|---|
| 653 | /* DA9150_ADETD_STAT = 0x151 */ |
|---|
| 654 | #define DA9150_DCD_STAT_SHIFT 0 |
|---|
| 655 | #define DA9150_DCD_STAT_MASK BIT(0) |
|---|
| 656 | #define DA9150_PCD_STAT_SHIFT 1 |
|---|
| 657 | #define DA9150_PCD_STAT_MASK (0x03 << 1) |
|---|
| 658 | #define DA9150_SCD_STAT_SHIFT 3 |
|---|
| 659 | #define DA9150_SCD_STAT_MASK (0x03 << 3) |
|---|
| 660 | #define DA9150_DP_STAT_SHIFT 5 |
|---|
| 661 | #define DA9150_DP_STAT_MASK BIT(5) |
|---|
| 662 | #define DA9150_DM_STAT_SHIFT 6 |
|---|
| 663 | #define DA9150_DM_STAT_MASK BIT(6) |
|---|
| 664 | |
|---|
| 665 | /* DA9150_ADET_CMPSTAT = 0x152 */ |
|---|
| 666 | #define DA9150_DP_COMP_SHIFT 1 |
|---|
| 667 | #define DA9150_DP_COMP_MASK BIT(1) |
|---|
| 668 | #define DA9150_DM_COMP_SHIFT 2 |
|---|
| 669 | #define DA9150_DM_COMP_MASK BIT(2) |
|---|
| 670 | #define DA9150_ADP_SNS_COMP_SHIFT 3 |
|---|
| 671 | #define DA9150_ADP_SNS_COMP_MASK BIT(3) |
|---|
| 672 | #define DA9150_ADP_PRB_COMP_SHIFT 4 |
|---|
| 673 | #define DA9150_ADP_PRB_COMP_MASK BIT(4) |
|---|
| 674 | #define DA9150_ID_COMP_SHIFT 5 |
|---|
| 675 | #define DA9150_ID_COMP_MASK BIT(5) |
|---|
| 676 | |
|---|
| 677 | /* DA9150_ADET_CTRL_A = 0x153 */ |
|---|
| 678 | #define DA9150_AID_DAT_SHIFT 0 |
|---|
| 679 | #define DA9150_AID_DAT_MASK BIT(0) |
|---|
| 680 | #define DA9150_AID_ID_SHIFT 1 |
|---|
| 681 | #define DA9150_AID_ID_MASK BIT(1) |
|---|
| 682 | #define DA9150_AID_TRIG_SHIFT 2 |
|---|
| 683 | #define DA9150_AID_TRIG_MASK BIT(2) |
|---|
| 684 | |
|---|
| 685 | /* DA9150_ADETVB_CFG_B = 0x154 */ |
|---|
| 686 | #define DA9150_VB_MODE_SHIFT 0 |
|---|
| 687 | #define DA9150_VB_MODE_MASK (0x03 << 0) |
|---|
| 688 | #define DA9150_VB_MODE_VB_SESS BIT(0) |
|---|
| 689 | |
|---|
| 690 | #define DA9150_TADP_PRB_SHIFT 2 |
|---|
| 691 | #define DA9150_TADP_PRB_MASK BIT(2) |
|---|
| 692 | #define DA9150_DAT_RPD_EXT_SHIFT 5 |
|---|
| 693 | #define DA9150_DAT_RPD_EXT_MASK BIT(5) |
|---|
| 694 | #define DA9150_CONF_RPD_SHIFT 6 |
|---|
| 695 | #define DA9150_CONF_RPD_MASK BIT(6) |
|---|
| 696 | #define DA9150_CONF_SRP_SHIFT 7 |
|---|
| 697 | #define DA9150_CONF_SRP_MASK BIT(7) |
|---|
| 698 | |
|---|
| 699 | /* DA9150_ADETVB_CFG_A = 0x155 */ |
|---|
| 700 | #define DA9150_AID_MODE_SHIFT 0 |
|---|
| 701 | #define DA9150_AID_MODE_MASK (0x03 << 0) |
|---|
| 702 | #define DA9150_AID_EXT_POL_SHIFT 2 |
|---|
| 703 | #define DA9150_AID_EXT_POL_MASK BIT(2) |
|---|
| 704 | |
|---|
| 705 | /* DA9150_ADETAC_CFG_A = 0x156 */ |
|---|
| 706 | #define DA9150_ISET_CDP_SHIFT 0 |
|---|
| 707 | #define DA9150_ISET_CDP_MASK (0x1f << 0) |
|---|
| 708 | #define DA9150_CONF_DBP_SHIFT 5 |
|---|
| 709 | #define DA9150_CONF_DBP_MASK BIT(5) |
|---|
| 710 | |
|---|
| 711 | /* DA9150_ADDETAC_CFG_B = 0x157 */ |
|---|
| 712 | #define DA9150_ISET_DCHG_SHIFT 0 |
|---|
| 713 | #define DA9150_ISET_DCHG_MASK (0x1f << 0) |
|---|
| 714 | #define DA9150_CONF_GPIOA_SHIFT 5 |
|---|
| 715 | #define DA9150_CONF_GPIOA_MASK BIT(5) |
|---|
| 716 | #define DA9150_CONF_GPIOB_SHIFT 6 |
|---|
| 717 | #define DA9150_CONF_GPIOB_MASK BIT(6) |
|---|
| 718 | #define DA9150_AID_VB_SHIFT 7 |
|---|
| 719 | #define DA9150_AID_VB_MASK BIT(7) |
|---|
| 720 | |
|---|
| 721 | /* DA9150_ADETAC_CFG_C = 0x158 */ |
|---|
| 722 | #define DA9150_ISET_DEF_SHIFT 0 |
|---|
| 723 | #define DA9150_ISET_DEF_MASK (0x1f << 0) |
|---|
| 724 | #define DA9150_CONF_MODE_SHIFT 5 |
|---|
| 725 | #define DA9150_CONF_MODE_MASK (0x03 << 5) |
|---|
| 726 | #define DA9150_AID_CR_DIS_SHIFT 7 |
|---|
| 727 | #define DA9150_AID_CR_DIS_MASK BIT(7) |
|---|
| 728 | |
|---|
| 729 | /* DA9150_ADETAC_CFG_D = 0x159 */ |
|---|
| 730 | #define DA9150_ISET_UNIT_SHIFT 0 |
|---|
| 731 | #define DA9150_ISET_UNIT_MASK (0x1f << 0) |
|---|
| 732 | #define DA9150_AID_UNCLAMP_SHIFT 5 |
|---|
| 733 | #define DA9150_AID_UNCLAMP_MASK BIT(5) |
|---|
| 734 | |
|---|
| 735 | /* DA9150_ADETVB_CFG_D = 0x15A */ |
|---|
| 736 | #define DA9150_ID_MODE_SHIFT 0 |
|---|
| 737 | #define DA9150_ID_MODE_MASK (0x03 << 0) |
|---|
| 738 | #define DA9150_DAT_MODE_SHIFT 2 |
|---|
| 739 | #define DA9150_DAT_MODE_MASK (0x0f << 2) |
|---|
| 740 | #define DA9150_DAT_SWP_SHIFT 6 |
|---|
| 741 | #define DA9150_DAT_SWP_MASK BIT(6) |
|---|
| 742 | #define DA9150_DAT_CLAMP_EXT_SHIFT 7 |
|---|
| 743 | #define DA9150_DAT_CLAMP_EXT_MASK BIT(7) |
|---|
| 744 | |
|---|
| 745 | /* DA9150_ADETID_CFG_A = 0x15B */ |
|---|
| 746 | #define DA9150_TID_POLL_SHIFT 0 |
|---|
| 747 | #define DA9150_TID_POLL_MASK (0x07 << 0) |
|---|
| 748 | #define DA9150_RID_CONV_SHIFT 3 |
|---|
| 749 | #define DA9150_RID_CONV_MASK BIT(3) |
|---|
| 750 | |
|---|
| 751 | /* DA9150_ADET_RID_PT_CHG_H = 0x15C */ |
|---|
| 752 | #define DA9150_RID_PT_CHG_H_SHIFT 0 |
|---|
| 753 | #define DA9150_RID_PT_CHG_H_MASK (0xff << 0) |
|---|
| 754 | |
|---|
| 755 | /* DA9150_ADET_RID_PT_CHG_L = 0x15D */ |
|---|
| 756 | #define DA9150_RID_PT_CHG_L_SHIFT 6 |
|---|
| 757 | #define DA9150_RID_PT_CHG_L_MASK (0x03 << 6) |
|---|
| 758 | |
|---|
| 759 | /* DA9150_PPR_TCTR_B = 0x160 */ |
|---|
| 760 | #define DA9150_CHG_TCTR_VAL_SHIFT 0 |
|---|
| 761 | #define DA9150_CHG_TCTR_VAL_MASK (0xff << 0) |
|---|
| 762 | |
|---|
| 763 | /* DA9150_PPR_BKCTRL_A = 0x163 */ |
|---|
| 764 | #define DA9150_VBUS_MODE_SHIFT 0 |
|---|
| 765 | #define DA9150_VBUS_MODE_MASK (0x03 << 0) |
|---|
| 766 | #define DA9150_VBUS_MODE_CHG BIT(0) |
|---|
| 767 | #define DA9150_VBUS_MODE_OTG (0x02 << 0) |
|---|
| 768 | #define DA9150_VBUS_LPM_SHIFT 2 |
|---|
| 769 | #define DA9150_VBUS_LPM_MASK (0x03 << 2) |
|---|
| 770 | #define DA9150_VBUS_SUSP_SHIFT 4 |
|---|
| 771 | #define DA9150_VBUS_SUSP_MASK BIT(4) |
|---|
| 772 | #define DA9150_VBUS_PWM_SHIFT 5 |
|---|
| 773 | #define DA9150_VBUS_PWM_MASK BIT(5) |
|---|
| 774 | #define DA9150_VBUS_ISO_SHIFT 6 |
|---|
| 775 | #define DA9150_VBUS_ISO_MASK BIT(6) |
|---|
| 776 | #define DA9150_VBUS_LDO_SHIFT 7 |
|---|
| 777 | #define DA9150_VBUS_LDO_MASK BIT(7) |
|---|
| 778 | |
|---|
| 779 | /* DA9150_PPR_BKCFG_A = 0x164 */ |
|---|
| 780 | #define DA9150_VBUS_ISET_SHIFT 0 |
|---|
| 781 | #define DA9150_VBUS_ISET_MASK (0x1f << 0) |
|---|
| 782 | #define DA9150_VBUS_IMAX_SHIFT 5 |
|---|
| 783 | #define DA9150_VBUS_IMAX_MASK BIT(5) |
|---|
| 784 | #define DA9150_VBUS_IOTG_SHIFT 6 |
|---|
| 785 | #define DA9150_VBUS_IOTG_MASK (0x03 << 6) |
|---|
| 786 | |
|---|
| 787 | /* DA9150_PPR_BKCFG_B = 0x165 */ |
|---|
| 788 | #define DA9150_VBUS_DROP_SHIFT 0 |
|---|
| 789 | #define DA9150_VBUS_DROP_MASK (0x0f << 0) |
|---|
| 790 | #define DA9150_VBUS_FAULT_DIS_SHIFT 6 |
|---|
| 791 | #define DA9150_VBUS_FAULT_DIS_MASK BIT(6) |
|---|
| 792 | #define DA9150_OTG_FAULT_DIS_SHIFT 7 |
|---|
| 793 | #define DA9150_OTG_FAULT_DIS_MASK BIT(7) |
|---|
| 794 | |
|---|
| 795 | /* DA9150_PPR_CHGCTRL_A = 0x166 */ |
|---|
| 796 | #define DA9150_CHG_EN_SHIFT 0 |
|---|
| 797 | #define DA9150_CHG_EN_MASK BIT(0) |
|---|
| 798 | |
|---|
| 799 | /* DA9150_PPR_CHGCTRL_B = 0x167 */ |
|---|
| 800 | #define DA9150_CHG_VBAT_SHIFT 0 |
|---|
| 801 | #define DA9150_CHG_VBAT_MASK (0x1f << 0) |
|---|
| 802 | #define DA9150_CHG_VDROP_SHIFT 6 |
|---|
| 803 | #define DA9150_CHG_VDROP_MASK (0x03 << 6) |
|---|
| 804 | |
|---|
| 805 | /* DA9150_PPR_CHGCTRL_C = 0x168 */ |
|---|
| 806 | #define DA9150_CHG_VFAULT_SHIFT 0 |
|---|
| 807 | #define DA9150_CHG_VFAULT_MASK (0x0f << 0) |
|---|
| 808 | #define DA9150_CHG_IPRE_SHIFT 4 |
|---|
| 809 | #define DA9150_CHG_IPRE_MASK (0x03 << 4) |
|---|
| 810 | |
|---|
| 811 | /* DA9150_PPR_TCTR_A = 0x169 */ |
|---|
| 812 | #define DA9150_CHG_TCTR_SHIFT 0 |
|---|
| 813 | #define DA9150_CHG_TCTR_MASK (0x07 << 0) |
|---|
| 814 | #define DA9150_CHG_TCTR_MODE_SHIFT 4 |
|---|
| 815 | #define DA9150_CHG_TCTR_MODE_MASK BIT(4) |
|---|
| 816 | |
|---|
| 817 | /* DA9150_PPR_CHGCTRL_D = 0x16A */ |
|---|
| 818 | #define DA9150_CHG_IBAT_SHIFT 0 |
|---|
| 819 | #define DA9150_CHG_IBAT_MASK (0xff << 0) |
|---|
| 820 | |
|---|
| 821 | /* DA9150_PPR_CHGCTRL_E = 0x16B */ |
|---|
| 822 | #define DA9150_CHG_IEND_SHIFT 0 |
|---|
| 823 | #define DA9150_CHG_IEND_MASK (0xff << 0) |
|---|
| 824 | |
|---|
| 825 | /* DA9150_PPR_CHGCTRL_F = 0x16C */ |
|---|
| 826 | #define DA9150_CHG_VCOLD_SHIFT 0 |
|---|
| 827 | #define DA9150_CHG_VCOLD_MASK (0x1f << 0) |
|---|
| 828 | #define DA9150_TBAT_TQA_EN_SHIFT 6 |
|---|
| 829 | #define DA9150_TBAT_TQA_EN_MASK BIT(6) |
|---|
| 830 | #define DA9150_TBAT_TDP_EN_SHIFT 7 |
|---|
| 831 | #define DA9150_TBAT_TDP_EN_MASK BIT(7) |
|---|
| 832 | |
|---|
| 833 | /* DA9150_PPR_CHGCTRL_G = 0x16D */ |
|---|
| 834 | #define DA9150_CHG_VWARM_SHIFT 0 |
|---|
| 835 | #define DA9150_CHG_VWARM_MASK (0x1f << 0) |
|---|
| 836 | |
|---|
| 837 | /* DA9150_PPR_CHGCTRL_H = 0x16E */ |
|---|
| 838 | #define DA9150_CHG_VHOT_SHIFT 0 |
|---|
| 839 | #define DA9150_CHG_VHOT_MASK (0x1f << 0) |
|---|
| 840 | |
|---|
| 841 | /* DA9150_PPR_CHGCTRL_I = 0x16F */ |
|---|
| 842 | #define DA9150_CHG_ICOLD_SHIFT 0 |
|---|
| 843 | #define DA9150_CHG_ICOLD_MASK (0xff << 0) |
|---|
| 844 | |
|---|
| 845 | /* DA9150_PPR_CHGCTRL_J = 0x170 */ |
|---|
| 846 | #define DA9150_CHG_IWARM_SHIFT 0 |
|---|
| 847 | #define DA9150_CHG_IWARM_MASK (0xff << 0) |
|---|
| 848 | |
|---|
| 849 | /* DA9150_PPR_CHGCTRL_K = 0x171 */ |
|---|
| 850 | #define DA9150_CHG_IHOT_SHIFT 0 |
|---|
| 851 | #define DA9150_CHG_IHOT_MASK (0xff << 0) |
|---|
| 852 | |
|---|
| 853 | /* DA9150_PPR_CHGCTRL_L = 0x172 */ |
|---|
| 854 | #define DA9150_CHG_IBAT_TRED_SHIFT 0 |
|---|
| 855 | #define DA9150_CHG_IBAT_TRED_MASK (0xff << 0) |
|---|
| 856 | |
|---|
| 857 | /* DA9150_PPR_CHGCTRL_M = 0x173 */ |
|---|
| 858 | #define DA9150_CHG_VFLOAT_SHIFT 0 |
|---|
| 859 | #define DA9150_CHG_VFLOAT_MASK (0x0f << 0) |
|---|
| 860 | #define DA9150_CHG_LPM_SHIFT 5 |
|---|
| 861 | #define DA9150_CHG_LPM_MASK BIT(5) |
|---|
| 862 | #define DA9150_CHG_NBLO_SHIFT 6 |
|---|
| 863 | #define DA9150_CHG_NBLO_MASK BIT(6) |
|---|
| 864 | #define DA9150_EBS_EN_SHIFT 7 |
|---|
| 865 | #define DA9150_EBS_EN_MASK BIT(7) |
|---|
| 866 | |
|---|
| 867 | /* DA9150_PPR_THYST_A = 0x174 */ |
|---|
| 868 | #define DA9150_TBAT_T1_SHIFT 0 |
|---|
| 869 | #define DA9150_TBAT_T1_MASK (0xff << 0) |
|---|
| 870 | |
|---|
| 871 | /* DA9150_PPR_THYST_B = 0x175 */ |
|---|
| 872 | #define DA9150_TBAT_T2_SHIFT 0 |
|---|
| 873 | #define DA9150_TBAT_T2_MASK (0xff << 0) |
|---|
| 874 | |
|---|
| 875 | /* DA9150_PPR_THYST_C = 0x176 */ |
|---|
| 876 | #define DA9150_TBAT_T3_SHIFT 0 |
|---|
| 877 | #define DA9150_TBAT_T3_MASK (0xff << 0) |
|---|
| 878 | |
|---|
| 879 | /* DA9150_PPR_THYST_D = 0x177 */ |
|---|
| 880 | #define DA9150_TBAT_T4_SHIFT 0 |
|---|
| 881 | #define DA9150_TBAT_T4_MASK (0xff << 0) |
|---|
| 882 | |
|---|
| 883 | /* DA9150_PPR_THYST_E = 0x178 */ |
|---|
| 884 | #define DA9150_TBAT_T5_SHIFT 0 |
|---|
| 885 | #define DA9150_TBAT_T5_MASK (0xff << 0) |
|---|
| 886 | |
|---|
| 887 | /* DA9150_PPR_THYST_F = 0x179 */ |
|---|
| 888 | #define DA9150_TBAT_H1_SHIFT 0 |
|---|
| 889 | #define DA9150_TBAT_H1_MASK (0xff << 0) |
|---|
| 890 | |
|---|
| 891 | /* DA9150_PPR_THYST_G = 0x17A */ |
|---|
| 892 | #define DA9150_TBAT_H5_SHIFT 0 |
|---|
| 893 | #define DA9150_TBAT_H5_MASK (0xff << 0) |
|---|
| 894 | |
|---|
| 895 | /* DA9150_PAGE_CON_3 = 0x180 */ |
|---|
| 896 | #define DA9150_PAGE_SHIFT 0 |
|---|
| 897 | #define DA9150_PAGE_MASK (0x3f << 0) |
|---|
| 898 | #define DA9150_WRITE_MODE_SHIFT 6 |
|---|
| 899 | #define DA9150_WRITE_MODE_MASK BIT(6) |
|---|
| 900 | #define DA9150_REVERT_SHIFT 7 |
|---|
| 901 | #define DA9150_REVERT_MASK BIT(7) |
|---|
| 902 | |
|---|
| 903 | /* DA9150_PAGE_CON_4 = 0x200 */ |
|---|
| 904 | #define DA9150_PAGE_SHIFT 0 |
|---|
| 905 | #define DA9150_PAGE_MASK (0x3f << 0) |
|---|
| 906 | #define DA9150_WRITE_MODE_SHIFT 6 |
|---|
| 907 | #define DA9150_WRITE_MODE_MASK BIT(6) |
|---|
| 908 | #define DA9150_REVERT_SHIFT 7 |
|---|
| 909 | #define DA9150_REVERT_MASK BIT(7) |
|---|
| 910 | |
|---|
| 911 | /* DA9150_PAGE_CON_5 = 0x280 */ |
|---|
| 912 | #define DA9150_PAGE_SHIFT 0 |
|---|
| 913 | #define DA9150_PAGE_MASK (0x3f << 0) |
|---|
| 914 | #define DA9150_WRITE_MODE_SHIFT 6 |
|---|
| 915 | #define DA9150_WRITE_MODE_MASK BIT(6) |
|---|
| 916 | #define DA9150_REVERT_SHIFT 7 |
|---|
| 917 | #define DA9150_REVERT_MASK BIT(7) |
|---|
| 918 | |
|---|
| 919 | /* DA9150_PAGE_CON_6 = 0x300 */ |
|---|
| 920 | #define DA9150_PAGE_SHIFT 0 |
|---|
| 921 | #define DA9150_PAGE_MASK (0x3f << 0) |
|---|
| 922 | #define DA9150_WRITE_MODE_SHIFT 6 |
|---|
| 923 | #define DA9150_WRITE_MODE_MASK BIT(6) |
|---|
| 924 | #define DA9150_REVERT_SHIFT 7 |
|---|
| 925 | #define DA9150_REVERT_MASK BIT(7) |
|---|
| 926 | |
|---|
| 927 | /* DA9150_COREBTLD_STAT_A = 0x302 */ |
|---|
| 928 | #define DA9150_BOOTLD_STAT_SHIFT 0 |
|---|
| 929 | #define DA9150_BOOTLD_STAT_MASK (0x03 << 0) |
|---|
| 930 | #define DA9150_CORE_LOCKUP_SHIFT 2 |
|---|
| 931 | #define DA9150_CORE_LOCKUP_MASK BIT(2) |
|---|
| 932 | |
|---|
| 933 | /* DA9150_COREBTLD_CTRL_A = 0x303 */ |
|---|
| 934 | #define DA9150_CORE_RESET_SHIFT 0 |
|---|
| 935 | #define DA9150_CORE_RESET_MASK BIT(0) |
|---|
| 936 | #define DA9150_CORE_STOP_SHIFT 1 |
|---|
| 937 | #define DA9150_CORE_STOP_MASK BIT(1) |
|---|
| 938 | |
|---|
| 939 | /* DA9150_CORE_CONFIG_A = 0x304 */ |
|---|
| 940 | #define DA9150_CORE_MEMMUX_SHIFT 0 |
|---|
| 941 | #define DA9150_CORE_MEMMUX_MASK (0x03 << 0) |
|---|
| 942 | #define DA9150_WDT_AUTO_START_SHIFT 2 |
|---|
| 943 | #define DA9150_WDT_AUTO_START_MASK BIT(2) |
|---|
| 944 | #define DA9150_WDT_AUTO_LOCK_SHIFT 3 |
|---|
| 945 | #define DA9150_WDT_AUTO_LOCK_MASK BIT(3) |
|---|
| 946 | #define DA9150_WDT_HLT_NO_CLK_SHIFT 4 |
|---|
| 947 | #define DA9150_WDT_HLT_NO_CLK_MASK BIT(4) |
|---|
| 948 | |
|---|
| 949 | /* DA9150_CORE_CONFIG_C = 0x305 */ |
|---|
| 950 | #define DA9150_CORE_SW_SIZE_SHIFT 0 |
|---|
| 951 | #define DA9150_CORE_SW_SIZE_MASK (0xff << 0) |
|---|
| 952 | |
|---|
| 953 | /* DA9150_CORE_CONFIG_B = 0x306 */ |
|---|
| 954 | #define DA9150_BOOTLD_EN_SHIFT 0 |
|---|
| 955 | #define DA9150_BOOTLD_EN_MASK BIT(0) |
|---|
| 956 | #define DA9150_CORE_EN_SHIFT 2 |
|---|
| 957 | #define DA9150_CORE_EN_MASK BIT(2) |
|---|
| 958 | #define DA9150_CORE_SW_SRC_SHIFT 3 |
|---|
| 959 | #define DA9150_CORE_SW_SRC_MASK (0x07 << 3) |
|---|
| 960 | #define DA9150_DEEP_SLEEP_EN_SHIFT 7 |
|---|
| 961 | #define DA9150_DEEP_SLEEP_EN_MASK BIT(7) |
|---|
| 962 | |
|---|
| 963 | /* DA9150_CORE_CFG_DATA_A = 0x307 */ |
|---|
| 964 | #define DA9150_CORE_CFG_DT_A_SHIFT 0 |
|---|
| 965 | #define DA9150_CORE_CFG_DT_A_MASK (0xff << 0) |
|---|
| 966 | |
|---|
| 967 | /* DA9150_CORE_CFG_DATA_B = 0x308 */ |
|---|
| 968 | #define DA9150_CORE_CFG_DT_B_SHIFT 0 |
|---|
| 969 | #define DA9150_CORE_CFG_DT_B_MASK (0xff << 0) |
|---|
| 970 | |
|---|
| 971 | /* DA9150_CORE_CMD_A = 0x309 */ |
|---|
| 972 | #define DA9150_CORE_CMD_SHIFT 0 |
|---|
| 973 | #define DA9150_CORE_CMD_MASK (0xff << 0) |
|---|
| 974 | |
|---|
| 975 | /* DA9150_CORE_DATA_A = 0x30A */ |
|---|
| 976 | #define DA9150_CORE_DATA_0_SHIFT 0 |
|---|
| 977 | #define DA9150_CORE_DATA_0_MASK (0xff << 0) |
|---|
| 978 | |
|---|
| 979 | /* DA9150_CORE_DATA_B = 0x30B */ |
|---|
| 980 | #define DA9150_CORE_DATA_1_SHIFT 0 |
|---|
| 981 | #define DA9150_CORE_DATA_1_MASK (0xff << 0) |
|---|
| 982 | |
|---|
| 983 | /* DA9150_CORE_DATA_C = 0x30C */ |
|---|
| 984 | #define DA9150_CORE_DATA_2_SHIFT 0 |
|---|
| 985 | #define DA9150_CORE_DATA_2_MASK (0xff << 0) |
|---|
| 986 | |
|---|
| 987 | /* DA9150_CORE_DATA_D = 0x30D */ |
|---|
| 988 | #define DA9150_CORE_DATA_3_SHIFT 0 |
|---|
| 989 | #define DA9150_CORE_DATA_3_MASK (0xff << 0) |
|---|
| 990 | |
|---|
| 991 | /* DA9150_CORE2WIRE_STAT_A = 0x310 */ |
|---|
| 992 | #define DA9150_FW_FWDL_ERR_SHIFT 7 |
|---|
| 993 | #define DA9150_FW_FWDL_ERR_MASK BIT(7) |
|---|
| 994 | |
|---|
| 995 | /* DA9150_CORE2WIRE_CTRL_A = 0x311 */ |
|---|
| 996 | #define DA9150_FW_FWDL_EN_SHIFT 0 |
|---|
| 997 | #define DA9150_FW_FWDL_EN_MASK BIT(0) |
|---|
| 998 | #define DA9150_FG_QIF_EN_SHIFT 1 |
|---|
| 999 | #define DA9150_FG_QIF_EN_MASK BIT(1) |
|---|
| 1000 | #define DA9150_CORE_BASE_ADDR_SHIFT 4 |
|---|
| 1001 | #define DA9150_CORE_BASE_ADDR_MASK (0x0f << 4) |
|---|
| 1002 | |
|---|
| 1003 | /* DA9150_FW_CTRL_A = 0x312 */ |
|---|
| 1004 | #define DA9150_FW_SEAL_SHIFT 0 |
|---|
| 1005 | #define DA9150_FW_SEAL_MASK (0xff << 0) |
|---|
| 1006 | |
|---|
| 1007 | /* DA9150_FW_CTRL_C = 0x313 */ |
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| 1008 | #define DA9150_FW_FWDL_CRC_SHIFT 0 |
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| 1009 | #define DA9150_FW_FWDL_CRC_MASK (0xff << 0) |
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| 1010 | |
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| 1011 | /* DA9150_FW_CTRL_D = 0x314 */ |
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| 1012 | #define DA9150_FW_FWDL_BASE_SHIFT 0 |
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| 1013 | #define DA9150_FW_FWDL_BASE_MASK (0x0f << 0) |
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| 1014 | |
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| 1015 | /* DA9150_FG_CTRL_A = 0x315 */ |
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| 1016 | #define DA9150_FG_QIF_CODE_SHIFT 0 |
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| 1017 | #define DA9150_FG_QIF_CODE_MASK (0xff << 0) |
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| 1018 | |
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| 1019 | /* DA9150_FG_CTRL_B = 0x316 */ |
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| 1020 | #define DA9150_FG_QIF_VALUE_SHIFT 0 |
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| 1021 | #define DA9150_FG_QIF_VALUE_MASK (0xff << 0) |
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| 1022 | |
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| 1023 | /* DA9150_FW_CTRL_E = 0x317 */ |
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| 1024 | #define DA9150_FW_FWDL_SEG_SHIFT 0 |
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| 1025 | #define DA9150_FW_FWDL_SEG_MASK (0xff << 0) |
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| 1026 | |
|---|
| 1027 | /* DA9150_FW_CTRL_B = 0x318 */ |
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| 1028 | #define DA9150_FW_FWDL_VALUE_SHIFT 0 |
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| 1029 | #define DA9150_FW_FWDL_VALUE_MASK (0xff << 0) |
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| 1030 | |
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| 1031 | /* DA9150_GPADC_CMAN = 0x320 */ |
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| 1032 | #define DA9150_GPADC_CEN_SHIFT 0 |
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| 1033 | #define DA9150_GPADC_CEN_MASK BIT(0) |
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| 1034 | #define DA9150_GPADC_CMUX_SHIFT 1 |
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| 1035 | #define DA9150_GPADC_CMUX_MASK (0x1f << 1) |
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| 1036 | |
|---|
| 1037 | /* DA9150_GPADC_CRES_A = 0x322 */ |
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| 1038 | #define DA9150_GPADC_CRES_H_SHIFT 0 |
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| 1039 | #define DA9150_GPADC_CRES_H_MASK (0xff << 0) |
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| 1040 | |
|---|
| 1041 | /* DA9150_GPADC_CRES_B = 0x323 */ |
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| 1042 | #define DA9150_GPADC_CRUN_SHIFT 0 |
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| 1043 | #define DA9150_GPADC_CRUN_MASK BIT(0) |
|---|
| 1044 | #define DA9150_GPADC_CRES_L_SHIFT 6 |
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| 1045 | #define DA9150_GPADC_CRES_L_MASK (0x03 << 6) |
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| 1046 | |
|---|
| 1047 | /* DA9150_CC_CFG_A = 0x328 */ |
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| 1048 | #define DA9150_CC_EN_SHIFT 0 |
|---|
| 1049 | #define DA9150_CC_EN_MASK BIT(0) |
|---|
| 1050 | #define DA9150_CC_TIMEBASE_SHIFT 1 |
|---|
| 1051 | #define DA9150_CC_TIMEBASE_MASK (0x03 << 1) |
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| 1052 | #define DA9150_CC_CFG_SHIFT 5 |
|---|
| 1053 | #define DA9150_CC_CFG_MASK (0x03 << 5) |
|---|
| 1054 | #define DA9150_CC_ENDLESS_MODE_SHIFT 7 |
|---|
| 1055 | #define DA9150_CC_ENDLESS_MODE_MASK BIT(7) |
|---|
| 1056 | |
|---|
| 1057 | /* DA9150_CC_CFG_B = 0x329 */ |
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| 1058 | #define DA9150_CC_OPT_SHIFT 0 |
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| 1059 | #define DA9150_CC_OPT_MASK (0x03 << 0) |
|---|
| 1060 | #define DA9150_CC_PREAMP_SHIFT 2 |
|---|
| 1061 | #define DA9150_CC_PREAMP_MASK (0x03 << 2) |
|---|
| 1062 | |
|---|
| 1063 | /* DA9150_CC_ICHG_RES_A = 0x32A */ |
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| 1064 | #define DA9150_CC_ICHG_RES_H_SHIFT 0 |
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| 1065 | #define DA9150_CC_ICHG_RES_H_MASK (0xff << 0) |
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| 1066 | |
|---|
| 1067 | /* DA9150_CC_ICHG_RES_B = 0x32B */ |
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| 1068 | #define DA9150_CC_ICHG_RES_L_SHIFT 3 |
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| 1069 | #define DA9150_CC_ICHG_RES_L_MASK (0x1f << 3) |
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| 1070 | |
|---|
| 1071 | /* DA9150_CC_IAVG_RES_A = 0x32C */ |
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| 1072 | #define DA9150_CC_IAVG_RES_H_SHIFT 0 |
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| 1073 | #define DA9150_CC_IAVG_RES_H_MASK (0xff << 0) |
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| 1074 | |
|---|
| 1075 | /* DA9150_CC_IAVG_RES_B = 0x32D */ |
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| 1076 | #define DA9150_CC_IAVG_RES_L_SHIFT 0 |
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| 1077 | #define DA9150_CC_IAVG_RES_L_MASK (0xff << 0) |
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| 1078 | |
|---|
| 1079 | /* DA9150_TAUX_CTRL_A = 0x330 */ |
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| 1080 | #define DA9150_TAUX_EN_SHIFT 0 |
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| 1081 | #define DA9150_TAUX_EN_MASK BIT(0) |
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| 1082 | #define DA9150_TAUX_MOD_SHIFT 1 |
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| 1083 | #define DA9150_TAUX_MOD_MASK BIT(1) |
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| 1084 | #define DA9150_TAUX_UPDATE_SHIFT 2 |
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| 1085 | #define DA9150_TAUX_UPDATE_MASK BIT(2) |
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| 1086 | |
|---|
| 1087 | /* DA9150_TAUX_RELOAD_H = 0x332 */ |
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| 1088 | #define DA9150_TAUX_RLD_H_SHIFT 0 |
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| 1089 | #define DA9150_TAUX_RLD_H_MASK (0xff << 0) |
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| 1090 | |
|---|
| 1091 | /* DA9150_TAUX_RELOAD_L = 0x333 */ |
|---|
| 1092 | #define DA9150_TAUX_RLD_L_SHIFT 3 |
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| 1093 | #define DA9150_TAUX_RLD_L_MASK (0x1f << 3) |
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| 1094 | |
|---|
| 1095 | /* DA9150_TAUX_VALUE_H = 0x334 */ |
|---|
| 1096 | #define DA9150_TAUX_VAL_H_SHIFT 0 |
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| 1097 | #define DA9150_TAUX_VAL_H_MASK (0xff << 0) |
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| 1098 | |
|---|
| 1099 | /* DA9150_TAUX_VALUE_L = 0x335 */ |
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| 1100 | #define DA9150_TAUX_VAL_L_SHIFT 3 |
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| 1101 | #define DA9150_TAUX_VAL_L_MASK (0x1f << 3) |
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| 1102 | |
|---|
| 1103 | /* DA9150_AUX_DATA_0 = 0x338 */ |
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| 1104 | #define DA9150_AUX_DAT_0_SHIFT 0 |
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| 1105 | #define DA9150_AUX_DAT_0_MASK (0xff << 0) |
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| 1106 | |
|---|
| 1107 | /* DA9150_AUX_DATA_1 = 0x339 */ |
|---|
| 1108 | #define DA9150_AUX_DAT_1_SHIFT 0 |
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| 1109 | #define DA9150_AUX_DAT_1_MASK (0xff << 0) |
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| 1110 | |
|---|
| 1111 | /* DA9150_AUX_DATA_2 = 0x33A */ |
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| 1112 | #define DA9150_AUX_DAT_2_SHIFT 0 |
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| 1113 | #define DA9150_AUX_DAT_2_MASK (0xff << 0) |
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| 1114 | |
|---|
| 1115 | /* DA9150_AUX_DATA_3 = 0x33B */ |
|---|
| 1116 | #define DA9150_AUX_DAT_3_SHIFT 0 |
|---|
| 1117 | #define DA9150_AUX_DAT_3_MASK (0xff << 0) |
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| 1118 | |
|---|
| 1119 | /* DA9150_BIF_CTRL = 0x340 */ |
|---|
| 1120 | #define DA9150_BIF_ISRC_EN_SHIFT 0 |
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| 1121 | #define DA9150_BIF_ISRC_EN_MASK BIT(0) |
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| 1122 | |
|---|
| 1123 | /* DA9150_TBAT_CTRL_A = 0x342 */ |
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| 1124 | #define DA9150_TBAT_EN_SHIFT 0 |
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| 1125 | #define DA9150_TBAT_EN_MASK BIT(0) |
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| 1126 | #define DA9150_TBAT_SW1_SHIFT 1 |
|---|
| 1127 | #define DA9150_TBAT_SW1_MASK BIT(1) |
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| 1128 | #define DA9150_TBAT_SW2_SHIFT 2 |
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| 1129 | #define DA9150_TBAT_SW2_MASK BIT(2) |
|---|
| 1130 | |
|---|
| 1131 | /* DA9150_TBAT_CTRL_B = 0x343 */ |
|---|
| 1132 | #define DA9150_TBAT_SW_FRC_SHIFT 0 |
|---|
| 1133 | #define DA9150_TBAT_SW_FRC_MASK BIT(0) |
|---|
| 1134 | #define DA9150_TBAT_STAT_SW1_SHIFT 1 |
|---|
| 1135 | #define DA9150_TBAT_STAT_SW1_MASK BIT(1) |
|---|
| 1136 | #define DA9150_TBAT_STAT_SW2_SHIFT 2 |
|---|
| 1137 | #define DA9150_TBAT_STAT_SW2_MASK BIT(2) |
|---|
| 1138 | #define DA9150_TBAT_HIGH_CURR_SHIFT 3 |
|---|
| 1139 | #define DA9150_TBAT_HIGH_CURR_MASK BIT(3) |
|---|
| 1140 | |
|---|
| 1141 | /* DA9150_TBAT_RES_A = 0x344 */ |
|---|
| 1142 | #define DA9150_TBAT_RES_H_SHIFT 0 |
|---|
| 1143 | #define DA9150_TBAT_RES_H_MASK (0xff << 0) |
|---|
| 1144 | |
|---|
| 1145 | /* DA9150_TBAT_RES_B = 0x345 */ |
|---|
| 1146 | #define DA9150_TBAT_RES_DIS_SHIFT 0 |
|---|
| 1147 | #define DA9150_TBAT_RES_DIS_MASK BIT(0) |
|---|
| 1148 | #define DA9150_TBAT_RES_L_SHIFT 6 |
|---|
| 1149 | #define DA9150_TBAT_RES_L_MASK (0x03 << 6) |
|---|
| 1150 | |
|---|
| 1151 | #endif /* __DA9150_REGISTERS_H */ |
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| 1152 | |
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