| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Header file for device driver Hi6421 PMIC |
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| 4 | * |
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| 5 | * Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd. |
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| 6 | * http://www.hisilicon.com |
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| 7 | * Copyright (c) <2013-2014> Linaro Ltd. |
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| 8 | * https://www.linaro.org |
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| 9 | * |
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| 10 | * Author: Guodong Xu <guodong.xu@linaro.org> |
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| 11 | */ |
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| 12 | |
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| 13 | #ifndef __HI6421_PMIC_H |
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| 14 | #define __HI6421_PMIC_H |
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| 15 | |
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| 16 | /* Hi6421 registers are mapped to memory bus in 4 bytes stride */ |
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| 17 | #define HI6421_REG_TO_BUS_ADDR(x) (x << 2) |
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| 18 | |
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| 19 | /* Hi6421 maximum register number */ |
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| 20 | #define HI6421_REG_MAX 0xFF |
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| 21 | |
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| 22 | /* Hi6421 OCP (over current protection) and DEB (debounce) control register */ |
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| 23 | #define HI6421_OCP_DEB_CTRL_REG HI6421_REG_TO_BUS_ADDR(0x51) |
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| 24 | #define HI6421_OCP_DEB_SEL_MASK 0x0C |
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| 25 | #define HI6421_OCP_DEB_SEL_8MS 0x00 |
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| 26 | #define HI6421_OCP_DEB_SEL_16MS 0x04 |
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| 27 | #define HI6421_OCP_DEB_SEL_32MS 0x08 |
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| 28 | #define HI6421_OCP_DEB_SEL_64MS 0x0C |
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| 29 | #define HI6421_OCP_EN_DEBOUNCE_MASK 0x02 |
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| 30 | #define HI6421_OCP_EN_DEBOUNCE_ENABLE 0x02 |
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| 31 | #define HI6421_OCP_AUTO_STOP_MASK 0x01 |
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| 32 | #define HI6421_OCP_AUTO_STOP_ENABLE 0x01 |
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| 33 | |
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| 34 | struct hi6421_pmic { |
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| 35 | struct regmap *regmap; |
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| 36 | }; |
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| 37 | |
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| 38 | enum hi6421_type { |
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| 39 | HI6421 = 0, |
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| 40 | HI6421_V530, |
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| 41 | }; |
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| 42 | |
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| 43 | #endif /* __HI6421_PMIC_H */ |
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| 44 | |
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