1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Functions to access LP87565 power management chip. |
4 | * |
5 | * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ |
6 | */ |
7 | |
8 | #ifndef __LINUX_MFD_LP87565_H |
9 | #define __LINUX_MFD_LP87565_H |
10 | |
11 | #include <linux/i2c.h> |
12 | #include <linux/regulator/driver.h> |
13 | #include <linux/regulator/machine.h> |
14 | |
15 | enum lp87565_device_type { |
16 | LP87565_DEVICE_TYPE_UNKNOWN = 0, |
17 | LP87565_DEVICE_TYPE_LP87524_Q1, |
18 | LP87565_DEVICE_TYPE_LP87561_Q1, |
19 | LP87565_DEVICE_TYPE_LP87565_Q1, |
20 | }; |
21 | |
22 | /* All register addresses */ |
23 | #define LP87565_REG_DEV_REV 0X00 |
24 | #define LP87565_REG_OTP_REV 0X01 |
25 | #define LP87565_REG_BUCK0_CTRL_1 0X02 |
26 | #define LP87565_REG_BUCK0_CTRL_2 0X03 |
27 | |
28 | #define LP87565_REG_BUCK1_CTRL_1 0X04 |
29 | #define LP87565_REG_BUCK1_CTRL_2 0X05 |
30 | |
31 | #define LP87565_REG_BUCK2_CTRL_1 0X06 |
32 | #define LP87565_REG_BUCK2_CTRL_2 0X07 |
33 | |
34 | #define LP87565_REG_BUCK3_CTRL_1 0X08 |
35 | #define LP87565_REG_BUCK3_CTRL_2 0X09 |
36 | |
37 | #define LP87565_REG_BUCK0_VOUT 0X0A |
38 | #define LP87565_REG_BUCK0_FLOOR_VOUT 0X0B |
39 | |
40 | #define LP87565_REG_BUCK1_VOUT 0X0C |
41 | #define LP87565_REG_BUCK1_FLOOR_VOUT 0X0D |
42 | |
43 | #define LP87565_REG_BUCK2_VOUT 0X0E |
44 | #define LP87565_REG_BUCK2_FLOOR_VOUT 0X0F |
45 | |
46 | #define LP87565_REG_BUCK3_VOUT 0X10 |
47 | #define LP87565_REG_BUCK3_FLOOR_VOUT 0X11 |
48 | |
49 | #define LP87565_REG_BUCK0_DELAY 0X12 |
50 | #define LP87565_REG_BUCK1_DELAY 0X13 |
51 | |
52 | #define LP87565_REG_BUCK2_DELAY 0X14 |
53 | #define LP87565_REG_BUCK3_DELAY 0X15 |
54 | |
55 | #define LP87565_REG_GPO2_DELAY 0X16 |
56 | #define LP87565_REG_GPO3_DELAY 0X17 |
57 | #define LP87565_REG_RESET 0X18 |
58 | #define LP87565_REG_CONFIG 0X19 |
59 | |
60 | #define LP87565_REG_INT_TOP_1 0X1A |
61 | #define LP87565_REG_INT_TOP_2 0X1B |
62 | |
63 | #define LP87565_REG_INT_BUCK_0_1 0X1C |
64 | #define LP87565_REG_INT_BUCK_2_3 0X1D |
65 | #define LP87565_REG_TOP_STAT 0X1E |
66 | #define LP87565_REG_BUCK_0_1_STAT 0X1F |
67 | #define LP87565_REG_BUCK_2_3_STAT 0x20 |
68 | |
69 | #define LP87565_REG_TOP_MASK_1 0x21 |
70 | #define LP87565_REG_TOP_MASK_2 0x22 |
71 | |
72 | #define LP87565_REG_BUCK_0_1_MASK 0x23 |
73 | #define LP87565_REG_BUCK_2_3_MASK 0x24 |
74 | #define LP87565_REG_SEL_I_LOAD 0x25 |
75 | |
76 | #define LP87565_REG_I_LOAD_2 0x26 |
77 | #define LP87565_REG_I_LOAD_1 0x27 |
78 | |
79 | #define LP87565_REG_PGOOD_CTRL1 0x28 |
80 | #define LP87565_REG_PGOOD_CTRL2 0x29 |
81 | #define LP87565_REG_PGOOD_FLT 0x2A |
82 | #define LP87565_REG_PLL_CTRL 0x2B |
83 | #define LP87565_REG_PIN_FUNCTION 0x2C |
84 | #define LP87565_REG_GPIO_CONFIG 0x2D |
85 | #define LP87565_REG_GPIO_IN 0x2E |
86 | #define LP87565_REG_GPIO_OUT 0x2F |
87 | |
88 | #define LP87565_REG_MAX LP87565_REG_GPIO_OUT |
89 | |
90 | /* Register field definitions */ |
91 | #define LP87565_DEV_REV_DEV_ID 0xC0 |
92 | #define LP87565_DEV_REV_ALL_LAYER 0x30 |
93 | #define LP87565_DEV_REV_METAL_LAYER 0x0F |
94 | |
95 | #define LP87565_OTP_REV_OTP_ID 0xFF |
96 | |
97 | #define LP87565_BUCK_CTRL_1_EN BIT(7) |
98 | #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6) |
99 | #define LP87565_BUCK_CTRL_1_PIN_SELECT_EN 0x30 |
100 | |
101 | #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3) |
102 | #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2) |
103 | #define LP87565_BUCK_CTRL_1_FPWM BIT(1) |
104 | /* Bit0 is reserved for BUCK1 and BUCK3 and valid only for BUCK0 and BUCK2 */ |
105 | #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0) |
106 | |
107 | #define LP87565_BUCK_CTRL_2_ILIM 0x38 |
108 | #define LP87565_BUCK_CTRL_2_SLEW_RATE 0x07 |
109 | |
110 | #define LP87565_BUCK_VSET 0xFF |
111 | #define LP87565_BUCK_FLOOR_VSET 0xFF |
112 | |
113 | #define LP87565_BUCK_SHUTDOWN_DELAY 0xF0 |
114 | #define LP87565_BUCK_STARTUP_DELAY 0x0F |
115 | |
116 | #define LP87565_GPIO_SHUTDOWN_DELAY 0xF0 |
117 | #define LP87565_GPIO_STARTUP_DELAY 0x0F |
118 | |
119 | #define LP87565_RESET_SW_RESET BIT(0) |
120 | |
121 | #define LP87565_CONFIG_DOUBLE_DELAY BIT(7) |
122 | #define LP87565_CONFIG_CLKIN_PD BIT(6) |
123 | #define LP87565_CONFIG_EN4_PD BIT(5) |
124 | #define LP87565_CONFIG_EN3_PD BIT(4) |
125 | #define LP87565_CONFIG_TDIE_WARN_LEVEL BIT(3) |
126 | #define LP87565_CONFIG_EN2_PD BIT(2) |
127 | #define LP87565_CONFIG_EN1_PD BIT(1) |
128 | |
129 | #define LP87565_INT_GPIO BIT(7) |
130 | #define LP87565_INT_BUCK23 BIT(6) |
131 | #define LP87565_INT_BUCK01 BIT(5) |
132 | #define LP87565_NO_SYNC_CLK BIT(4) |
133 | #define LP87565_TDIE_SD BIT(3) |
134 | #define LP87565_TDIE_WARN BIT(2) |
135 | #define LP87565_INT_OVP BIT(1) |
136 | #define LP87565_I_LOAD_READY BIT(0) |
137 | |
138 | #define LP87565_INT_TOP2_RESET_REG BIT(0) |
139 | |
140 | #define LP87565_BUCK1_PG_INT BIT(6) |
141 | #define LP87565_BUCK1_SC_INT BIT(5) |
142 | #define LP87565_BUCK1_ILIM_INT BIT(4) |
143 | #define LP87565_BUCK0_PG_INT BIT(2) |
144 | #define LP87565_BUCK0_SC_INT BIT(1) |
145 | #define LP87565_BUCK0_ILIM_INT BIT(0) |
146 | |
147 | #define LP87565_BUCK3_PG_INT BIT(6) |
148 | #define LP87565_BUCK3_SC_INT BIT(5) |
149 | #define LP87565_BUCK3_ILIM_INT BIT(4) |
150 | #define LP87565_BUCK2_PG_INT BIT(2) |
151 | #define LP87565_BUCK2_SC_INT BIT(1) |
152 | #define LP87565_BUCK2_ILIM_INT BIT(0) |
153 | |
154 | #define LP87565_SYNC_CLK_STAT BIT(4) |
155 | #define LP87565_TDIE_SD_STAT BIT(3) |
156 | #define LP87565_TDIE_WARN_STAT BIT(2) |
157 | #define LP87565_OVP_STAT BIT(1) |
158 | |
159 | #define LP87565_BUCK1_STAT BIT(7) |
160 | #define LP87565_BUCK1_PG_STAT BIT(6) |
161 | #define LP87565_BUCK1_ILIM_STAT BIT(4) |
162 | #define LP87565_BUCK0_STAT BIT(3) |
163 | #define LP87565_BUCK0_PG_STAT BIT(2) |
164 | #define LP87565_BUCK0_ILIM_STAT BIT(0) |
165 | |
166 | #define LP87565_BUCK3_STAT BIT(7) |
167 | #define LP87565_BUCK3_PG_STAT BIT(6) |
168 | #define LP87565_BUCK3_ILIM_STAT BIT(4) |
169 | #define LP87565_BUCK2_STAT BIT(3) |
170 | #define LP87565_BUCK2_PG_STAT BIT(2) |
171 | #define LP87565_BUCK2_ILIM_STAT BIT(0) |
172 | |
173 | #define LPL87565_GPIO_MASK BIT(7) |
174 | #define LPL87565_SYNC_CLK_MASK BIT(4) |
175 | #define LPL87565_TDIE_WARN_MASK BIT(2) |
176 | #define LPL87565_I_LOAD_READY_MASK BIT(0) |
177 | |
178 | #define LPL87565_RESET_REG_MASK BIT(0) |
179 | |
180 | #define LPL87565_BUCK1_PG_MASK BIT(6) |
181 | #define LPL87565_BUCK1_ILIM_MASK BIT(4) |
182 | #define LPL87565_BUCK0_PG_MASK BIT(2) |
183 | #define LPL87565_BUCK0_ILIM_MASK BIT(0) |
184 | |
185 | #define LPL87565_BUCK3_PG_MASK BIT(6) |
186 | #define LPL87565_BUCK3_ILIM_MASK BIT(4) |
187 | #define LPL87565_BUCK2_PG_MASK BIT(2) |
188 | #define LPL87565_BUCK2_ILIM_MASK BIT(0) |
189 | |
190 | #define LP87565_LOAD_CURRENT_BUCK_SELECT 0x3 |
191 | |
192 | #define LP87565_I_LOAD2_BUCK_LOAD_CURRENT 0x3 |
193 | #define LP87565_I_LOAD1_BUCK_LOAD_CURRENT 0xFF |
194 | |
195 | #define LP87565_PG3_SEL 0xC0 |
196 | #define LP87565_PG2_SEL 0x30 |
197 | #define LP87565_PG1_SEL 0x0C |
198 | #define LP87565_PG0_SEL 0x03 |
199 | |
200 | #define LP87565_HALF_DAY BIT(7) |
201 | #define LP87565_EN_PG0_NINT BIT(6) |
202 | #define LP87565_PGOOD_SET_DELAY BIT(5) |
203 | #define LP87565_EN_PGFLT_STAT BIT(4) |
204 | #define LP87565_PGOOD_WINDOW BIT(2) |
205 | #define LP87565_PGOOD_OD BIT(1) |
206 | #define LP87565_PGOOD_POL BIT(0) |
207 | |
208 | #define LP87565_PG3_FLT BIT(3) |
209 | #define LP87565_PG2_FLT BIT(2) |
210 | #define LP87565_PG1_FLT BIT(1) |
211 | #define LP87565_PG0_FLT BIT(0) |
212 | |
213 | #define LP87565_PLL_MODE 0xC0 |
214 | #define LP87565_EXT_CLK_FREQ 0x1F |
215 | |
216 | #define LP87565_EN_SPREAD_SPEC BIT(7) |
217 | #define LP87565_EN_PIN_CTRL_GPIO3 BIT(6) |
218 | #define LP87565_EN_PIN_SELECT_GPIO3 BIT(5) |
219 | #define LP87565_EN_PIN_CTRL_GPIO2 BIT(4) |
220 | #define LP87565_EN_PIN_SELECT_GPIO2 BIT(3) |
221 | #define LP87565_GPIO3_SEL BIT(2) |
222 | #define LP87565_GPIO2_SEL BIT(1) |
223 | #define LP87565_GPIO1_SEL BIT(0) |
224 | |
225 | #define LP87565_GPIO3_OD BIT(6) |
226 | #define LP87565_GPIO2_OD BIT(5) |
227 | #define LP87565_GPIO1_OD BIT(4) |
228 | #define LP87565_GPIO3_DIR BIT(2) |
229 | #define LP87565_GPIO2_DIR BIT(1) |
230 | #define LP87565_GPIO1_DIR BIT(0) |
231 | |
232 | #define LP87565_GPIO3_IN BIT(2) |
233 | #define LP87565_GPIO2_IN BIT(1) |
234 | #define LP87565_GPIO1_IN BIT(0) |
235 | |
236 | #define LP87565_GPIO3_OUT BIT(2) |
237 | #define LP87565_GPIO2_OUT BIT(1) |
238 | #define LP87565_GPIO1_OUT BIT(0) |
239 | |
240 | /** |
241 | * struct LP87565 - state holder for the LP87565 driver |
242 | * @dev: struct device pointer for MFD device |
243 | * @rev: revision of the LP87565 |
244 | * @dev_type: The device type for example lp87565-q1 |
245 | * @lock: lock guarding the data structure |
246 | * @regmap: register map of the LP87565 PMIC |
247 | * |
248 | * Device data may be used to access the LP87565 chip |
249 | */ |
250 | struct lp87565 { |
251 | struct device *dev; |
252 | u8 rev; |
253 | u8 dev_type; |
254 | struct regmap *regmap; |
255 | struct gpio_desc *reset_gpio; |
256 | }; |
257 | #endif /* __LINUX_MFD_LP87565_H */ |
258 | |