1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* |
3 | * max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip |
4 | * |
5 | * Copyright (C) 2014 Samsung Electrnoics |
6 | * Chanwoo Choi <cw00.choi@samsung.com> |
7 | * Krzysztof Kozlowski <krzk@kernel.org> |
8 | */ |
9 | |
10 | #ifndef __MAX14577_PRIVATE_H__ |
11 | #define __MAX14577_PRIVATE_H__ |
12 | |
13 | #include <linux/i2c.h> |
14 | #include <linux/regmap.h> |
15 | |
16 | #define I2C_ADDR_PMIC (0x46 >> 1) |
17 | #define I2C_ADDR_MUIC (0x4A >> 1) |
18 | #define I2C_ADDR_FG (0x6C >> 1) |
19 | |
20 | enum maxim_device_type { |
21 | MAXIM_DEVICE_TYPE_UNKNOWN = 0, |
22 | MAXIM_DEVICE_TYPE_MAX14577, |
23 | MAXIM_DEVICE_TYPE_MAX77836, |
24 | |
25 | MAXIM_DEVICE_TYPE_NUM, |
26 | }; |
27 | |
28 | /* Slave addr = 0x4A: MUIC and Charger */ |
29 | enum max14577_reg { |
30 | MAX14577_REG_DEVICEID = 0x00, |
31 | MAX14577_REG_INT1 = 0x01, |
32 | MAX14577_REG_INT2 = 0x02, |
33 | MAX14577_REG_INT3 = 0x03, |
34 | MAX14577_REG_STATUS1 = 0x04, |
35 | MAX14577_REG_STATUS2 = 0x05, |
36 | MAX14577_REG_STATUS3 = 0x06, |
37 | MAX14577_REG_INTMASK1 = 0x07, |
38 | MAX14577_REG_INTMASK2 = 0x08, |
39 | MAX14577_REG_INTMASK3 = 0x09, |
40 | MAX14577_REG_CDETCTRL1 = 0x0A, |
41 | MAX14577_REG_RFU = 0x0B, |
42 | MAX14577_REG_CONTROL1 = 0x0C, |
43 | MAX14577_REG_CONTROL2 = 0x0D, |
44 | MAX14577_REG_CONTROL3 = 0x0E, |
45 | MAX14577_REG_CHGCTRL1 = 0x0F, |
46 | MAX14577_REG_CHGCTRL2 = 0x10, |
47 | MAX14577_REG_CHGCTRL3 = 0x11, |
48 | MAX14577_REG_CHGCTRL4 = 0x12, |
49 | MAX14577_REG_CHGCTRL5 = 0x13, |
50 | MAX14577_REG_CHGCTRL6 = 0x14, |
51 | MAX14577_REG_CHGCTRL7 = 0x15, |
52 | |
53 | MAX14577_REG_END, |
54 | }; |
55 | |
56 | /* Slave addr = 0x4A: MUIC */ |
57 | enum max14577_muic_reg { |
58 | MAX14577_MUIC_REG_STATUS1 = 0x04, |
59 | MAX14577_MUIC_REG_STATUS2 = 0x05, |
60 | MAX14577_MUIC_REG_CONTROL1 = 0x0C, |
61 | MAX14577_MUIC_REG_CONTROL3 = 0x0E, |
62 | |
63 | MAX14577_MUIC_REG_END, |
64 | }; |
65 | |
66 | /* |
67 | * Combined charger types for max14577 and max77836. |
68 | * |
69 | * On max14577 three lower bits map to STATUS2/CHGTYP field. |
70 | * However the max77836 has different two last values of STATUS2/CHGTYP. |
71 | * To indicate the difference enum has two additional values for max77836. |
72 | * These values are just a register value bitwise OR with 0x8. |
73 | */ |
74 | enum max14577_muic_charger_type { |
75 | MAX14577_CHARGER_TYPE_NONE = 0x0, |
76 | MAX14577_CHARGER_TYPE_USB = 0x1, |
77 | MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT = 0x2, |
78 | MAX14577_CHARGER_TYPE_DEDICATED_CHG = 0x3, |
79 | MAX14577_CHARGER_TYPE_SPECIAL_500MA = 0x4, |
80 | /* Special 1A or 2A charger */ |
81 | MAX14577_CHARGER_TYPE_SPECIAL_1A = 0x5, |
82 | /* max14577: reserved, used on max77836 */ |
83 | MAX14577_CHARGER_TYPE_RESERVED = 0x6, |
84 | /* max14577: dead-battery charing with maximum current 100mA */ |
85 | MAX14577_CHARGER_TYPE_DEAD_BATTERY = 0x7, |
86 | /* |
87 | * max77836: special charger (bias on D+/D-), |
88 | * matches register value of 0x6 |
89 | */ |
90 | MAX77836_CHARGER_TYPE_SPECIAL_BIAS = 0xe, |
91 | /* max77836: reserved, register value 0x7 */ |
92 | MAX77836_CHARGER_TYPE_RESERVED = 0xf, |
93 | }; |
94 | |
95 | /* MAX14577 interrupts */ |
96 | #define MAX14577_INT1_ADC_MASK BIT(0) |
97 | #define MAX14577_INT1_ADCLOW_MASK BIT(1) |
98 | #define MAX14577_INT1_ADCERR_MASK BIT(2) |
99 | #define MAX77836_INT1_ADC1K_MASK BIT(3) |
100 | |
101 | #define MAX14577_INT2_CHGTYP_MASK BIT(0) |
102 | #define MAX14577_INT2_CHGDETRUN_MASK BIT(1) |
103 | #define MAX14577_INT2_DCDTMR_MASK BIT(2) |
104 | #define MAX14577_INT2_DBCHG_MASK BIT(3) |
105 | #define MAX14577_INT2_VBVOLT_MASK BIT(4) |
106 | #define MAX77836_INT2_VIDRM_MASK BIT(5) |
107 | |
108 | #define MAX14577_INT3_EOC_MASK BIT(0) |
109 | #define MAX14577_INT3_CGMBC_MASK BIT(1) |
110 | #define MAX14577_INT3_OVP_MASK BIT(2) |
111 | #define MAX14577_INT3_MBCCHGERR_MASK BIT(3) |
112 | |
113 | /* MAX14577 DEVICE ID register */ |
114 | #define DEVID_VENDORID_SHIFT 0 |
115 | #define DEVID_DEVICEID_SHIFT 3 |
116 | #define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT) |
117 | #define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT) |
118 | |
119 | /* MAX14577 STATUS1 register */ |
120 | #define STATUS1_ADC_SHIFT 0 |
121 | #define STATUS1_ADCLOW_SHIFT 5 |
122 | #define STATUS1_ADCERR_SHIFT 6 |
123 | #define MAX77836_STATUS1_ADC1K_SHIFT 7 |
124 | #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT) |
125 | #define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT) |
126 | #define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT) |
127 | #define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT) |
128 | |
129 | /* MAX14577 STATUS2 register */ |
130 | #define STATUS2_CHGTYP_SHIFT 0 |
131 | #define STATUS2_CHGDETRUN_SHIFT 3 |
132 | #define STATUS2_DCDTMR_SHIFT 4 |
133 | #define MAX14577_STATUS2_DBCHG_SHIFT 5 |
134 | #define MAX77836_STATUS2_DXOVP_SHIFT 5 |
135 | #define STATUS2_VBVOLT_SHIFT 6 |
136 | #define MAX77836_STATUS2_VIDRM_SHIFT 7 |
137 | #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT) |
138 | #define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT) |
139 | #define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT) |
140 | #define MAX14577_STATUS2_DBCHG_MASK BIT(MAX14577_STATUS2_DBCHG_SHIFT) |
141 | #define MAX77836_STATUS2_DXOVP_MASK BIT(MAX77836_STATUS2_DXOVP_SHIFT) |
142 | #define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT) |
143 | #define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT) |
144 | |
145 | /* MAX14577 CONTROL1 register */ |
146 | #define COMN1SW_SHIFT 0 |
147 | #define COMP2SW_SHIFT 3 |
148 | #define MICEN_SHIFT 6 |
149 | #define IDBEN_SHIFT 7 |
150 | #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT) |
151 | #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT) |
152 | #define MICEN_MASK BIT(MICEN_SHIFT) |
153 | #define IDBEN_MASK BIT(IDBEN_SHIFT) |
154 | #define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK) |
155 | #define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \ |
156 | | (1 << COMN1SW_SHIFT)) |
157 | #define CTRL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ |
158 | | (2 << COMN1SW_SHIFT)) |
159 | #define CTRL1_SW_UART ((3 << COMP2SW_SHIFT) \ |
160 | | (3 << COMN1SW_SHIFT)) |
161 | #define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ |
162 | | (0 << COMN1SW_SHIFT)) |
163 | |
164 | /* MAX14577 CONTROL2 register */ |
165 | #define CTRL2_LOWPWR_SHIFT (0) |
166 | #define CTRL2_ADCEN_SHIFT (1) |
167 | #define CTRL2_CPEN_SHIFT (2) |
168 | #define CTRL2_SFOUTASRT_SHIFT (3) |
169 | #define CTRL2_SFOUTORD_SHIFT (4) |
170 | #define CTRL2_ACCDET_SHIFT (5) |
171 | #define CTRL2_USBCPINT_SHIFT (6) |
172 | #define CTRL2_RCPS_SHIFT (7) |
173 | #define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT) |
174 | #define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT) |
175 | #define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT) |
176 | #define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT) |
177 | #define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT) |
178 | #define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT) |
179 | #define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT) |
180 | #define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT) |
181 | |
182 | #define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \ |
183 | (0 << CTRL2_LOWPWR_SHIFT)) |
184 | #define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \ |
185 | (1 << CTRL2_LOWPWR_SHIFT)) |
186 | |
187 | /* MAX14577 CONTROL3 register */ |
188 | #define CTRL3_JIGSET_SHIFT 0 |
189 | #define CTRL3_BOOTSET_SHIFT 2 |
190 | #define CTRL3_ADCDBSET_SHIFT 4 |
191 | #define CTRL3_WBTH_SHIFT 6 |
192 | #define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT) |
193 | #define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT) |
194 | #define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT) |
195 | #define CTRL3_WBTH_MASK (0x3 << CTRL3_WBTH_SHIFT) |
196 | |
197 | /* Slave addr = 0x4A: Charger */ |
198 | enum max14577_charger_reg { |
199 | MAX14577_CHG_REG_STATUS3 = 0x06, |
200 | MAX14577_CHG_REG_CHG_CTRL1 = 0x0F, |
201 | MAX14577_CHG_REG_CHG_CTRL2 = 0x10, |
202 | MAX14577_CHG_REG_CHG_CTRL3 = 0x11, |
203 | MAX14577_CHG_REG_CHG_CTRL4 = 0x12, |
204 | MAX14577_CHG_REG_CHG_CTRL5 = 0x13, |
205 | MAX14577_CHG_REG_CHG_CTRL6 = 0x14, |
206 | MAX14577_CHG_REG_CHG_CTRL7 = 0x15, |
207 | |
208 | MAX14577_CHG_REG_END, |
209 | }; |
210 | |
211 | /* MAX14577 STATUS3 register */ |
212 | #define STATUS3_EOC_SHIFT 0 |
213 | #define STATUS3_CGMBC_SHIFT 1 |
214 | #define STATUS3_OVP_SHIFT 2 |
215 | #define STATUS3_MBCCHGERR_SHIFT 3 |
216 | #define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT) |
217 | #define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT) |
218 | #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT) |
219 | #define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT) |
220 | |
221 | /* MAX14577 CDETCTRL1 register */ |
222 | #define CDETCTRL1_CHGDETEN_SHIFT 0 |
223 | #define CDETCTRL1_CHGTYPMAN_SHIFT 1 |
224 | #define CDETCTRL1_DCDEN_SHIFT 2 |
225 | #define CDETCTRL1_DCD2SCT_SHIFT 3 |
226 | #define MAX14577_CDETCTRL1_DCHKTM_SHIFT 4 |
227 | #define MAX77836_CDETCTRL1_CDLY_SHIFT 4 |
228 | #define MAX14577_CDETCTRL1_DBEXIT_SHIFT 5 |
229 | #define MAX77836_CDETCTRL1_DCDCPL_SHIFT 5 |
230 | #define CDETCTRL1_DBIDLE_SHIFT 6 |
231 | #define CDETCTRL1_CDPDET_SHIFT 7 |
232 | #define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT) |
233 | #define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT) |
234 | #define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT) |
235 | #define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT) |
236 | #define MAX14577_CDETCTRL1_DCHKTM_MASK BIT(MAX14577_CDETCTRL1_DCHKTM_SHIFT) |
237 | #define MAX77836_CDETCTRL1_CDDLY_MASK BIT(MAX77836_CDETCTRL1_CDDLY_SHIFT) |
238 | #define MAX14577_CDETCTRL1_DBEXIT_MASK BIT(MAX14577_CDETCTRL1_DBEXIT_SHIFT) |
239 | #define MAX77836_CDETCTRL1_DCDCPL_MASK BIT(MAX77836_CDETCTRL1_DCDCPL_SHIFT) |
240 | #define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT) |
241 | #define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT) |
242 | |
243 | /* MAX14577 CHGCTRL1 register */ |
244 | #define CHGCTRL1_TCHW_SHIFT 4 |
245 | #define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT) |
246 | |
247 | /* MAX14577 CHGCTRL2 register */ |
248 | #define CHGCTRL2_MBCHOSTEN_SHIFT 6 |
249 | #define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT) |
250 | #define CHGCTRL2_VCHGR_RC_SHIFT 7 |
251 | #define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT) |
252 | |
253 | /* MAX14577 CHGCTRL3 register */ |
254 | #define CHGCTRL3_MBCCVWRC_SHIFT 0 |
255 | #define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT) |
256 | |
257 | /* MAX14577 CHGCTRL4 register */ |
258 | #define CHGCTRL4_MBCICHWRCH_SHIFT 0 |
259 | #define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT) |
260 | #define CHGCTRL4_MBCICHWRCL_SHIFT 4 |
261 | #define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT) |
262 | |
263 | /* MAX14577 CHGCTRL5 register */ |
264 | #define CHGCTRL5_EOCS_SHIFT 0 |
265 | #define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT) |
266 | |
267 | /* MAX14577 CHGCTRL6 register */ |
268 | #define CHGCTRL6_AUTOSTOP_SHIFT 5 |
269 | #define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT) |
270 | |
271 | /* MAX14577 CHGCTRL7 register */ |
272 | #define CHGCTRL7_OTPCGHCVS_SHIFT 0 |
273 | #define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT) |
274 | |
275 | /* MAX14577 charger current limits (as in CHGCTRL4 register), uA */ |
276 | #define MAX14577_CHARGER_CURRENT_LIMIT_MIN 90000U |
277 | #define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_START 200000U |
278 | #define MAX14577_CHARGER_CURRENT_LIMIT_HIGH_STEP 50000U |
279 | #define MAX14577_CHARGER_CURRENT_LIMIT_MAX 950000U |
280 | |
281 | /* MAX77836 charger current limits (as in CHGCTRL4 register), uA */ |
282 | #define MAX77836_CHARGER_CURRENT_LIMIT_MIN 45000U |
283 | #define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_START 100000U |
284 | #define MAX77836_CHARGER_CURRENT_LIMIT_HIGH_STEP 25000U |
285 | #define MAX77836_CHARGER_CURRENT_LIMIT_MAX 475000U |
286 | |
287 | /* |
288 | * MAX14577 charger End-Of-Charge current limits |
289 | * (as in CHGCTRL5 register), uA |
290 | */ |
291 | #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MIN 50000U |
292 | #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_STEP 10000U |
293 | #define MAX14577_CHARGER_EOC_CURRENT_LIMIT_MAX 200000U |
294 | |
295 | /* |
296 | * MAX14577/MAX77836 Battery Constant Voltage |
297 | * (as in CHGCTRL3 register), uV |
298 | */ |
299 | #define MAXIM_CHARGER_CONSTANT_VOLTAGE_MIN 4000000U |
300 | #define MAXIM_CHARGER_CONSTANT_VOLTAGE_STEP 20000U |
301 | #define MAXIM_CHARGER_CONSTANT_VOLTAGE_MAX 4350000U |
302 | |
303 | /* Default value for fast charge timer, in hours */ |
304 | #define MAXIM_CHARGER_FAST_CHARGE_TIMER_DEFAULT 5 |
305 | |
306 | /* MAX14577 regulator SFOUT LDO voltage, fixed, uV */ |
307 | #define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000 |
308 | |
309 | /* MAX77836 regulator LDOx voltage, uV */ |
310 | #define MAX77836_REGULATOR_LDO_VOLTAGE_MIN 800000 |
311 | #define MAX77836_REGULATOR_LDO_VOLTAGE_MAX 3950000 |
312 | #define MAX77836_REGULATOR_LDO_VOLTAGE_STEP 50000 |
313 | #define MAX77836_REGULATOR_LDO_VOLTAGE_STEPS_NUM 64 |
314 | |
315 | /* Slave addr = 0x46: PMIC */ |
316 | enum max77836_pmic_reg { |
317 | MAX77836_PMIC_REG_PMIC_ID = 0x20, |
318 | MAX77836_PMIC_REG_PMIC_REV = 0x21, |
319 | MAX77836_PMIC_REG_INTSRC = 0x22, |
320 | MAX77836_PMIC_REG_INTSRC_MASK = 0x23, |
321 | MAX77836_PMIC_REG_TOPSYS_INT = 0x24, |
322 | MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26, |
323 | MAX77836_PMIC_REG_TOPSYS_STAT = 0x28, |
324 | MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A, |
325 | MAX77836_PMIC_REG_LSCNFG = 0x2B, |
326 | |
327 | MAX77836_LDO_REG_CNFG1_LDO1 = 0x51, |
328 | MAX77836_LDO_REG_CNFG2_LDO1 = 0x52, |
329 | MAX77836_LDO_REG_CNFG1_LDO2 = 0x53, |
330 | MAX77836_LDO_REG_CNFG2_LDO2 = 0x54, |
331 | MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55, |
332 | |
333 | MAX77836_COMP_REG_COMP1 = 0x60, |
334 | |
335 | MAX77836_PMIC_REG_END, |
336 | }; |
337 | |
338 | #define MAX77836_INTSRC_MASK_TOP_INT_SHIFT 1 |
339 | #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3 |
340 | #define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT) |
341 | #define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT) |
342 | |
343 | /* MAX77836 PMIC interrupts */ |
344 | #define MAX77836_TOPSYS_INT_T120C_SHIFT 0 |
345 | #define MAX77836_TOPSYS_INT_T140C_SHIFT 1 |
346 | #define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT) |
347 | #define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT) |
348 | |
349 | /* LDO1/LDO2 CONFIG1 register */ |
350 | #define MAX77836_CNFG1_LDO_PWRMD_SHIFT 6 |
351 | #define MAX77836_CNFG1_LDO_TV_SHIFT 0 |
352 | #define MAX77836_CNFG1_LDO_PWRMD_MASK (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT) |
353 | #define MAX77836_CNFG1_LDO_TV_MASK (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT) |
354 | |
355 | /* LDO1/LDO2 CONFIG2 register */ |
356 | #define MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT 7 |
357 | #define MAX77836_CNFG2_LDO_ALPMEN_SHIFT 6 |
358 | #define MAX77836_CNFG2_LDO_COMP_SHIFT 4 |
359 | #define MAX77836_CNFG2_LDO_POK_SHIFT 3 |
360 | #define MAX77836_CNFG2_LDO_ADE_SHIFT 1 |
361 | #define MAX77836_CNFG2_LDO_SS_SHIFT 0 |
362 | #define MAX77836_CNFG2_LDO_OVCLMPEN_MASK BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT) |
363 | #define MAX77836_CNFG2_LDO_ALPMEN_MASK BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT) |
364 | #define MAX77836_CNFG2_LDO_COMP_MASK (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT) |
365 | #define MAX77836_CNFG2_LDO_POK_MASK BIT(MAX77836_CNFG2_LDO_POK_SHIFT) |
366 | #define MAX77836_CNFG2_LDO_ADE_MASK BIT(MAX77836_CNFG2_LDO_ADE_SHIFT) |
367 | #define MAX77836_CNFG2_LDO_SS_MASK BIT(MAX77836_CNFG2_LDO_SS_SHIFT) |
368 | |
369 | /* Slave addr = 0x6C: Fuel-Gauge/Battery */ |
370 | enum max77836_fg_reg { |
371 | MAX77836_FG_REG_VCELL_MSB = 0x02, |
372 | MAX77836_FG_REG_VCELL_LSB = 0x03, |
373 | MAX77836_FG_REG_SOC_MSB = 0x04, |
374 | MAX77836_FG_REG_SOC_LSB = 0x05, |
375 | MAX77836_FG_REG_MODE_H = 0x06, |
376 | MAX77836_FG_REG_MODE_L = 0x07, |
377 | MAX77836_FG_REG_VERSION_MSB = 0x08, |
378 | MAX77836_FG_REG_VERSION_LSB = 0x09, |
379 | MAX77836_FG_REG_HIBRT_H = 0x0A, |
380 | MAX77836_FG_REG_HIBRT_L = 0x0B, |
381 | MAX77836_FG_REG_CONFIG_H = 0x0C, |
382 | MAX77836_FG_REG_CONFIG_L = 0x0D, |
383 | MAX77836_FG_REG_VALRT_MIN = 0x14, |
384 | MAX77836_FG_REG_VALRT_MAX = 0x15, |
385 | MAX77836_FG_REG_CRATE_MSB = 0x16, |
386 | MAX77836_FG_REG_CRATE_LSB = 0x17, |
387 | MAX77836_FG_REG_VRESET = 0x18, |
388 | MAX77836_FG_REG_FGID = 0x19, |
389 | MAX77836_FG_REG_STATUS_H = 0x1A, |
390 | MAX77836_FG_REG_STATUS_L = 0x1B, |
391 | /* |
392 | * TODO: TABLE registers |
393 | * TODO: CMD register |
394 | */ |
395 | |
396 | MAX77836_FG_REG_END, |
397 | }; |
398 | |
399 | enum max14577_irq { |
400 | /* INT1 */ |
401 | MAX14577_IRQ_INT1_ADC, |
402 | MAX14577_IRQ_INT1_ADCLOW, |
403 | MAX14577_IRQ_INT1_ADCERR, |
404 | MAX77836_IRQ_INT1_ADC1K, |
405 | |
406 | /* INT2 */ |
407 | MAX14577_IRQ_INT2_CHGTYP, |
408 | MAX14577_IRQ_INT2_CHGDETRUN, |
409 | MAX14577_IRQ_INT2_DCDTMR, |
410 | MAX14577_IRQ_INT2_DBCHG, |
411 | MAX14577_IRQ_INT2_VBVOLT, |
412 | MAX77836_IRQ_INT2_VIDRM, |
413 | |
414 | /* INT3 */ |
415 | MAX14577_IRQ_INT3_EOC, |
416 | MAX14577_IRQ_INT3_CGMBC, |
417 | MAX14577_IRQ_INT3_OVP, |
418 | MAX14577_IRQ_INT3_MBCCHGERR, |
419 | |
420 | /* TOPSYS_INT, only MAX77836 */ |
421 | MAX77836_IRQ_TOPSYS_T140C, |
422 | MAX77836_IRQ_TOPSYS_T120C, |
423 | |
424 | MAX14577_IRQ_NUM, |
425 | }; |
426 | |
427 | struct max14577 { |
428 | struct device *dev; |
429 | struct i2c_client *i2c; /* Slave addr = 0x4A */ |
430 | struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */ |
431 | enum maxim_device_type dev_type; |
432 | |
433 | struct regmap *regmap; /* For MUIC and Charger */ |
434 | struct regmap *regmap_pmic; |
435 | |
436 | struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */ |
437 | struct regmap_irq_chip_data *irq_data_pmic; |
438 | int irq; |
439 | }; |
440 | |
441 | /* MAX14577 shared regmap API function */ |
442 | static inline int max14577_read_reg(struct regmap *map, u8 reg, u8 *dest) |
443 | { |
444 | unsigned int val; |
445 | int ret; |
446 | |
447 | ret = regmap_read(map, reg, val: &val); |
448 | *dest = val; |
449 | |
450 | return ret; |
451 | } |
452 | |
453 | static inline int max14577_bulk_read(struct regmap *map, u8 reg, u8 *buf, |
454 | int count) |
455 | { |
456 | return regmap_bulk_read(map, reg, val: buf, val_count: count); |
457 | } |
458 | |
459 | static inline int max14577_write_reg(struct regmap *map, u8 reg, u8 value) |
460 | { |
461 | return regmap_write(map, reg, val: value); |
462 | } |
463 | |
464 | static inline int max14577_bulk_write(struct regmap *map, u8 reg, u8 *buf, |
465 | int count) |
466 | { |
467 | return regmap_bulk_write(map, reg, val: buf, val_count: count); |
468 | } |
469 | |
470 | static inline int max14577_update_reg(struct regmap *map, u8 reg, u8 mask, |
471 | u8 val) |
472 | { |
473 | return regmap_update_bits(map, reg, mask, val); |
474 | } |
475 | |
476 | #endif /* __MAX14577_PRIVATE_H__ */ |
477 | |