1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * TI Palmas
4 *
5 * Copyright 2011-2013 Texas Instruments Inc.
6 *
7 * Author: Graeme Gregory <gg@slimlogic.co.uk>
8 * Author: Ian Lartey <ian@slimlogic.co.uk>
9 */
10
11#ifndef __LINUX_MFD_PALMAS_H
12#define __LINUX_MFD_PALMAS_H
13
14#include <linux/usb/otg.h>
15#include <linux/leds.h>
16#include <linux/regmap.h>
17#include <linux/regulator/driver.h>
18#include <linux/extcon-provider.h>
19#include <linux/usb/phy_companion.h>
20
21#define PALMAS_NUM_CLIENTS 3
22
23/* The ID_REVISION NUMBERS */
24#define PALMAS_CHIP_OLD_ID 0x0000
25#define PALMAS_CHIP_ID 0xC035
26#define PALMAS_CHIP_CHARGER_ID 0xC036
27
28#define TPS65917_RESERVED -1
29
30#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
31 ((a) == PALMAS_CHIP_ID))
32#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
33
34/**
35 * Palmas PMIC feature types
36 *
37 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
38 * regulator.
39 *
40 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
41 * specific feature (above) or not. Return non-zero, if yes.
42 */
43#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
44#define PALMAS_PMIC_HAS(b, f) \
45 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
46
47struct palmas_pmic;
48struct palmas_gpadc;
49struct palmas_resource;
50struct palmas_usb;
51struct palmas_pmic_driver_data;
52struct palmas_pmic_platform_data;
53
54enum palmas_usb_state {
55 PALMAS_USB_STATE_DISCONNECT,
56 PALMAS_USB_STATE_VBUS,
57 PALMAS_USB_STATE_ID,
58};
59
60struct palmas {
61 struct device *dev;
62
63 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
64 struct regmap *regmap[PALMAS_NUM_CLIENTS];
65
66 /* Stored chip id */
67 int id;
68
69 unsigned int features;
70 /* IRQ Data */
71 int irq;
72 u32 irq_mask;
73 struct mutex irq_lock;
74 struct regmap_irq_chip_data *irq_data;
75
76 struct palmas_pmic_driver_data *pmic_ddata;
77
78 /* Child Devices */
79 struct palmas_pmic *pmic;
80 struct palmas_gpadc *gpadc;
81 struct palmas_resource *resource;
82 struct palmas_usb *usb;
83
84 /* GPIO MUXing */
85 u8 gpio_muxed;
86 u8 led_muxed;
87 u8 pwm_muxed;
88};
89
90#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
91 PALMAS_EXT_CONTROL_ENABLE2 | \
92 PALMAS_EXT_CONTROL_NSLEEP)
93
94struct palmas_sleep_requestor_info {
95 int id;
96 int reg_offset;
97 int bit_pos;
98};
99
100struct palmas_regs_info {
101 char *name;
102 char *sname;
103 u8 vsel_addr;
104 u8 ctrl_addr;
105 u8 tstep_addr;
106 int sleep_id;
107};
108
109struct palmas_pmic_driver_data {
110 int smps_start;
111 int smps_end;
112 int ldo_begin;
113 int ldo_end;
114 int max_reg;
115 bool has_regen3;
116 struct palmas_regs_info *palmas_regs_info;
117 struct of_regulator_match *palmas_matches;
118 struct palmas_sleep_requestor_info *sleep_req_info;
119 int (*smps_register)(struct palmas_pmic *pmic,
120 struct palmas_pmic_driver_data *ddata,
121 struct palmas_pmic_platform_data *pdata,
122 const char *pdev_name,
123 struct regulator_config config);
124 int (*ldo_register)(struct palmas_pmic *pmic,
125 struct palmas_pmic_driver_data *ddata,
126 struct palmas_pmic_platform_data *pdata,
127 const char *pdev_name,
128 struct regulator_config config);
129};
130
131struct palmas_gpadc_platform_data {
132 /* Channel 3 current source is only enabled during conversion */
133 int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
134
135 /* Channel 0 current source can be used for battery detection.
136 * If used for battery detection this will cause a permanent current
137 * consumption depending on current level set here.
138 */
139 int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
140 bool extended_delay; /* use extended delay for conversion */
141
142 /* default BAT_REMOVAL_DAT setting on device probe */
143 int bat_removal;
144
145 /* Sets the START_POLARITY bit in the RT_CTRL register */
146 int start_polarity;
147
148 int auto_conversion_period_ms;
149};
150
151struct palmas_reg_init {
152 /* warm_rest controls the voltage levels after a warm reset
153 *
154 * 0: reload default values from OTP on warm reset
155 * 1: maintain voltage from VSEL on warm reset
156 */
157 int warm_reset;
158
159 /* roof_floor controls whether the regulator uses the i2c style
160 * of DVS or uses the method where a GPIO or other control method is
161 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
162 *
163 * For SMPS
164 *
165 * 0: i2c selection of voltage
166 * 1: pin selection of voltage.
167 *
168 * For LDO unused
169 */
170 int roof_floor;
171
172 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
173 * the data sheet.
174 *
175 * For SMPS
176 *
177 * 0: Off
178 * 1: AUTO
179 * 2: ECO
180 * 3: Forced PWM
181 *
182 * For LDO
183 *
184 * 0: Off
185 * 1: On
186 */
187 int mode_sleep;
188
189 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
190 * register. Set this is the default voltage set in OTP needs
191 * to be overridden.
192 */
193 u8 vsel;
194
195};
196
197enum palmas_regulators {
198 /* SMPS regulators */
199 PALMAS_REG_SMPS12,
200 PALMAS_REG_SMPS123,
201 PALMAS_REG_SMPS3,
202 PALMAS_REG_SMPS45,
203 PALMAS_REG_SMPS457,
204 PALMAS_REG_SMPS6,
205 PALMAS_REG_SMPS7,
206 PALMAS_REG_SMPS8,
207 PALMAS_REG_SMPS9,
208 PALMAS_REG_SMPS10_OUT2,
209 PALMAS_REG_SMPS10_OUT1,
210 /* LDO regulators */
211 PALMAS_REG_LDO1,
212 PALMAS_REG_LDO2,
213 PALMAS_REG_LDO3,
214 PALMAS_REG_LDO4,
215 PALMAS_REG_LDO5,
216 PALMAS_REG_LDO6,
217 PALMAS_REG_LDO7,
218 PALMAS_REG_LDO8,
219 PALMAS_REG_LDO9,
220 PALMAS_REG_LDOLN,
221 PALMAS_REG_LDOUSB,
222 /* External regulators */
223 PALMAS_REG_REGEN1,
224 PALMAS_REG_REGEN2,
225 PALMAS_REG_REGEN3,
226 PALMAS_REG_SYSEN1,
227 PALMAS_REG_SYSEN2,
228 /* Total number of regulators */
229 PALMAS_NUM_REGS,
230};
231
232enum tps65917_regulators {
233 /* SMPS regulators */
234 TPS65917_REG_SMPS1,
235 TPS65917_REG_SMPS2,
236 TPS65917_REG_SMPS3,
237 TPS65917_REG_SMPS4,
238 TPS65917_REG_SMPS5,
239 TPS65917_REG_SMPS12,
240 /* LDO regulators */
241 TPS65917_REG_LDO1,
242 TPS65917_REG_LDO2,
243 TPS65917_REG_LDO3,
244 TPS65917_REG_LDO4,
245 TPS65917_REG_LDO5,
246 TPS65917_REG_REGEN1,
247 TPS65917_REG_REGEN2,
248 TPS65917_REG_REGEN3,
249
250 /* Total number of regulators */
251 TPS65917_NUM_REGS,
252};
253
254/* External controll signal name */
255enum {
256 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
257 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
258 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
259};
260
261/*
262 * Palmas device resources can be controlled externally for
263 * enabling/disabling it rather than register write through i2c.
264 * Add the external controlled requestor ID for different resources.
265 */
266enum palmas_external_requestor_id {
267 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
268 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
269 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
270 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
271 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
272 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
273 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
274 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
275 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
276 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
277 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
278 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
279 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
280 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
281 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
282 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
283 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
284 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
285 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
286 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
287 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
288 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
289 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
290 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
291 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
292 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
293
294 /* Last entry */
295 PALMAS_EXTERNAL_REQSTR_ID_MAX,
296};
297
298enum tps65917_external_requestor_id {
299 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
300 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
301 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
302 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
303 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
304 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
305 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
306 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
307 TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
308 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
309 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
310 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
311 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
312 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
313 /* Last entry */
314 TPS65917_EXTERNAL_REQSTR_ID_MAX,
315};
316
317struct palmas_pmic_platform_data {
318 /* An array of pointers to regulator init data indexed by regulator
319 * ID
320 */
321 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
322
323 /* An array of pointers to structures containing sleep mode and DVS
324 * configuration for regulators indexed by ID
325 */
326 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
327
328 /* use LDO6 for vibrator control */
329 int ldo6_vibrator;
330
331 /* Enable tracking mode of LDO8 */
332 bool enable_ldo8_tracking;
333};
334
335struct palmas_usb_platform_data {
336 /* Do we enable the wakeup comparator on probe */
337 int wakeup;
338};
339
340struct palmas_resource_platform_data {
341 int regen1_mode_sleep;
342 int regen2_mode_sleep;
343 int sysen1_mode_sleep;
344 int sysen2_mode_sleep;
345
346 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
347 u8 nsleep_res;
348 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
349 u8 nsleep_smps;
350 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
351 u8 nsleep_ldo1;
352 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
353 u8 nsleep_ldo2;
354
355 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
356 u8 enable1_res;
357 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
358 u8 enable1_smps;
359 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
360 u8 enable1_ldo1;
361 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
362 u8 enable1_ldo2;
363
364 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
365 u8 enable2_res;
366 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
367 u8 enable2_smps;
368 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
369 u8 enable2_ldo1;
370 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
371 u8 enable2_ldo2;
372};
373
374struct palmas_clk_platform_data {
375 int clk32kg_mode_sleep;
376 int clk32kgaudio_mode_sleep;
377};
378
379struct palmas_platform_data {
380 int irq_flags;
381 int gpio_base;
382
383 /* bit value to be loaded to the POWER_CTRL register */
384 u8 power_ctrl;
385
386 /*
387 * boolean to select if we want to configure muxing here
388 * then the two value to load into the registers if true
389 */
390 int mux_from_pdata;
391 u8 pad1, pad2;
392 bool pm_off;
393
394 struct palmas_pmic_platform_data *pmic_pdata;
395 struct palmas_gpadc_platform_data *gpadc_pdata;
396 struct palmas_usb_platform_data *usb_pdata;
397 struct palmas_resource_platform_data *resource_pdata;
398 struct palmas_clk_platform_data *clk_pdata;
399};
400
401struct palmas_gpadc_calibration {
402 s32 gain;
403 s32 gain_error;
404 s32 offset_error;
405};
406
407#define PALMAS_DATASHEET_NAME(_name) "palmas-gpadc-chan-"#_name
408
409struct palmas_gpadc_result {
410 s32 raw_code;
411 s32 corrected_code;
412 s32 result;
413};
414
415#define PALMAS_MAX_CHANNELS 16
416
417/* Define the tps65917 IRQ numbers */
418enum tps65917_irqs {
419 /* INT1 registers */
420 TPS65917_RESERVED1,
421 TPS65917_PWRON_IRQ,
422 TPS65917_LONG_PRESS_KEY_IRQ,
423 TPS65917_RESERVED2,
424 TPS65917_PWRDOWN_IRQ,
425 TPS65917_HOTDIE_IRQ,
426 TPS65917_VSYS_MON_IRQ,
427 TPS65917_RESERVED3,
428 /* INT2 registers */
429 TPS65917_RESERVED4,
430 TPS65917_OTP_ERROR_IRQ,
431 TPS65917_WDT_IRQ,
432 TPS65917_RESERVED5,
433 TPS65917_RESET_IN_IRQ,
434 TPS65917_FSD_IRQ,
435 TPS65917_SHORT_IRQ,
436 TPS65917_RESERVED6,
437 /* INT3 registers */
438 TPS65917_GPADC_AUTO_0_IRQ,
439 TPS65917_GPADC_AUTO_1_IRQ,
440 TPS65917_GPADC_EOC_SW_IRQ,
441 TPS65917_RESREVED6,
442 TPS65917_RESERVED7,
443 TPS65917_RESERVED8,
444 TPS65917_RESERVED9,
445 TPS65917_VBUS_IRQ,
446 /* INT4 registers */
447 TPS65917_GPIO_0_IRQ,
448 TPS65917_GPIO_1_IRQ,
449 TPS65917_GPIO_2_IRQ,
450 TPS65917_GPIO_3_IRQ,
451 TPS65917_GPIO_4_IRQ,
452 TPS65917_GPIO_5_IRQ,
453 TPS65917_GPIO_6_IRQ,
454 TPS65917_RESERVED10,
455 /* Total Number IRQs */
456 TPS65917_NUM_IRQ,
457};
458
459/* Define the palmas IRQ numbers */
460enum palmas_irqs {
461 /* INT1 registers */
462 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
463 PALMAS_PWRON_IRQ,
464 PALMAS_LONG_PRESS_KEY_IRQ,
465 PALMAS_RPWRON_IRQ,
466 PALMAS_PWRDOWN_IRQ,
467 PALMAS_HOTDIE_IRQ,
468 PALMAS_VSYS_MON_IRQ,
469 PALMAS_VBAT_MON_IRQ,
470 /* INT2 registers */
471 PALMAS_RTC_ALARM_IRQ,
472 PALMAS_RTC_TIMER_IRQ,
473 PALMAS_WDT_IRQ,
474 PALMAS_BATREMOVAL_IRQ,
475 PALMAS_RESET_IN_IRQ,
476 PALMAS_FBI_BB_IRQ,
477 PALMAS_SHORT_IRQ,
478 PALMAS_VAC_ACOK_IRQ,
479 /* INT3 registers */
480 PALMAS_GPADC_AUTO_0_IRQ,
481 PALMAS_GPADC_AUTO_1_IRQ,
482 PALMAS_GPADC_EOC_SW_IRQ,
483 PALMAS_GPADC_EOC_RT_IRQ,
484 PALMAS_ID_OTG_IRQ,
485 PALMAS_ID_IRQ,
486 PALMAS_VBUS_OTG_IRQ,
487 PALMAS_VBUS_IRQ,
488 /* INT4 registers */
489 PALMAS_GPIO_0_IRQ,
490 PALMAS_GPIO_1_IRQ,
491 PALMAS_GPIO_2_IRQ,
492 PALMAS_GPIO_3_IRQ,
493 PALMAS_GPIO_4_IRQ,
494 PALMAS_GPIO_5_IRQ,
495 PALMAS_GPIO_6_IRQ,
496 PALMAS_GPIO_7_IRQ,
497 /* Total Number IRQs */
498 PALMAS_NUM_IRQ,
499};
500
501/* Palmas GPADC Channels */
502enum {
503 PALMAS_ADC_CH_IN0,
504 PALMAS_ADC_CH_IN1,
505 PALMAS_ADC_CH_IN2,
506 PALMAS_ADC_CH_IN3,
507 PALMAS_ADC_CH_IN4,
508 PALMAS_ADC_CH_IN5,
509 PALMAS_ADC_CH_IN6,
510 PALMAS_ADC_CH_IN7,
511 PALMAS_ADC_CH_IN8,
512 PALMAS_ADC_CH_IN9,
513 PALMAS_ADC_CH_IN10,
514 PALMAS_ADC_CH_IN11,
515 PALMAS_ADC_CH_IN12,
516 PALMAS_ADC_CH_IN13,
517 PALMAS_ADC_CH_IN14,
518 PALMAS_ADC_CH_IN15,
519 PALMAS_ADC_CH_MAX,
520};
521
522/* Palmas GPADC Channel0 Current Source */
523enum {
524 PALMAS_ADC_CH0_CURRENT_SRC_0,
525 PALMAS_ADC_CH0_CURRENT_SRC_5,
526 PALMAS_ADC_CH0_CURRENT_SRC_15,
527 PALMAS_ADC_CH0_CURRENT_SRC_20,
528};
529
530/* Palmas GPADC Channel3 Current Source */
531enum {
532 PALMAS_ADC_CH3_CURRENT_SRC_0,
533 PALMAS_ADC_CH3_CURRENT_SRC_10,
534 PALMAS_ADC_CH3_CURRENT_SRC_400,
535 PALMAS_ADC_CH3_CURRENT_SRC_800,
536};
537
538struct palmas_pmic {
539 struct palmas *palmas;
540 struct device *dev;
541 struct regulator_desc desc[PALMAS_NUM_REGS];
542 struct mutex mutex;
543
544 int smps123;
545 int smps457;
546 int smps12;
547
548 int range[PALMAS_REG_SMPS10_OUT1];
549 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
550 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
551};
552
553struct palmas_resource {
554 struct palmas *palmas;
555 struct device *dev;
556};
557
558struct palmas_usb {
559 struct palmas *palmas;
560 struct device *dev;
561
562 struct extcon_dev *edev;
563
564 int id_otg_irq;
565 int id_irq;
566 int vbus_otg_irq;
567 int vbus_irq;
568
569 int gpio_id_irq;
570 int gpio_vbus_irq;
571 struct gpio_desc *id_gpiod;
572 struct gpio_desc *vbus_gpiod;
573 unsigned long sw_debounce_jiffies;
574 struct delayed_work wq_detectid;
575
576 enum palmas_usb_state linkstat;
577 int wakeup;
578 bool enable_vbus_detection;
579 bool enable_id_detection;
580 bool enable_gpio_id_detection;
581 bool enable_gpio_vbus_detection;
582};
583
584#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
585
586enum usb_irq_events {
587 /* Wakeup events from INT3 */
588 PALMAS_USB_ID_WAKEPUP,
589 PALMAS_USB_VBUS_WAKEUP,
590
591 /* ID_OTG_EVENTS */
592 PALMAS_USB_ID_GND,
593 N_PALMAS_USB_ID_GND,
594 PALMAS_USB_ID_C,
595 N_PALMAS_USB_ID_C,
596 PALMAS_USB_ID_B,
597 N_PALMAS_USB_ID_B,
598 PALMAS_USB_ID_A,
599 N_PALMAS_USB_ID_A,
600 PALMAS_USB_ID_FLOAT,
601 N_PALMAS_USB_ID_FLOAT,
602
603 /* VBUS_OTG_EVENTS */
604 PALMAS_USB_VB_SESS_END,
605 N_PALMAS_USB_VB_SESS_END,
606 PALMAS_USB_VB_SESS_VLD,
607 N_PALMAS_USB_VB_SESS_VLD,
608 PALMAS_USB_VA_SESS_VLD,
609 N_PALMAS_USB_VA_SESS_VLD,
610 PALMAS_USB_VA_VBUS_VLD,
611 N_PALMAS_USB_VA_VBUS_VLD,
612 PALMAS_USB_VADP_SNS,
613 N_PALMAS_USB_VADP_SNS,
614 PALMAS_USB_VADP_PRB,
615 N_PALMAS_USB_VADP_PRB,
616 PALMAS_USB_VOTG_SESS_VLD,
617 N_PALMAS_USB_VOTG_SESS_VLD,
618};
619
620/* defines so we can store the mux settings */
621#define PALMAS_GPIO_0_MUXED (1 << 0)
622#define PALMAS_GPIO_1_MUXED (1 << 1)
623#define PALMAS_GPIO_2_MUXED (1 << 2)
624#define PALMAS_GPIO_3_MUXED (1 << 3)
625#define PALMAS_GPIO_4_MUXED (1 << 4)
626#define PALMAS_GPIO_5_MUXED (1 << 5)
627#define PALMAS_GPIO_6_MUXED (1 << 6)
628#define PALMAS_GPIO_7_MUXED (1 << 7)
629
630#define PALMAS_LED1_MUXED (1 << 0)
631#define PALMAS_LED2_MUXED (1 << 1)
632
633#define PALMAS_PWM1_MUXED (1 << 0)
634#define PALMAS_PWM2_MUXED (1 << 1)
635
636/* helper macro to get correct slave number */
637#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
638#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
639
640/* Base addresses of IP blocks in Palmas */
641#define PALMAS_SMPS_DVS_BASE 0x020
642#define PALMAS_RTC_BASE 0x100
643#define PALMAS_VALIDITY_BASE 0x118
644#define PALMAS_SMPS_BASE 0x120
645#define PALMAS_LDO_BASE 0x150
646#define PALMAS_DVFS_BASE 0x180
647#define PALMAS_PMU_CONTROL_BASE 0x1A0
648#define PALMAS_RESOURCE_BASE 0x1D4
649#define PALMAS_PU_PD_OD_BASE 0x1F0
650#define PALMAS_LED_BASE 0x200
651#define PALMAS_INTERRUPT_BASE 0x210
652#define PALMAS_USB_OTG_BASE 0x250
653#define PALMAS_VIBRATOR_BASE 0x270
654#define PALMAS_GPIO_BASE 0x280
655#define PALMAS_USB_BASE 0x290
656#define PALMAS_GPADC_BASE 0x2C0
657#define PALMAS_TRIM_GPADC_BASE 0x3CD
658
659/* Registers for function RTC */
660#define PALMAS_SECONDS_REG 0x00
661#define PALMAS_MINUTES_REG 0x01
662#define PALMAS_HOURS_REG 0x02
663#define PALMAS_DAYS_REG 0x03
664#define PALMAS_MONTHS_REG 0x04
665#define PALMAS_YEARS_REG 0x05
666#define PALMAS_WEEKS_REG 0x06
667#define PALMAS_ALARM_SECONDS_REG 0x08
668#define PALMAS_ALARM_MINUTES_REG 0x09
669#define PALMAS_ALARM_HOURS_REG 0x0A
670#define PALMAS_ALARM_DAYS_REG 0x0B
671#define PALMAS_ALARM_MONTHS_REG 0x0C
672#define PALMAS_ALARM_YEARS_REG 0x0D
673#define PALMAS_RTC_CTRL_REG 0x10
674#define PALMAS_RTC_STATUS_REG 0x11
675#define PALMAS_RTC_INTERRUPTS_REG 0x12
676#define PALMAS_RTC_COMP_LSB_REG 0x13
677#define PALMAS_RTC_COMP_MSB_REG 0x14
678#define PALMAS_RTC_RES_PROG_REG 0x15
679#define PALMAS_RTC_RESET_STATUS_REG 0x16
680
681/* Bit definitions for SECONDS_REG */
682#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
683#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
684#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
685#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
686
687/* Bit definitions for MINUTES_REG */
688#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
689#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
690#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
691#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
692
693/* Bit definitions for HOURS_REG */
694#define PALMAS_HOURS_REG_PM_NAM 0x80
695#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
696#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
697#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
698#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
699#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
700
701/* Bit definitions for DAYS_REG */
702#define PALMAS_DAYS_REG_DAY1_MASK 0x30
703#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
704#define PALMAS_DAYS_REG_DAY0_MASK 0x0F
705#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
706
707/* Bit definitions for MONTHS_REG */
708#define PALMAS_MONTHS_REG_MONTH1 0x10
709#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
710#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
711#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
712
713/* Bit definitions for YEARS_REG */
714#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
715#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
716#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
717#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
718
719/* Bit definitions for WEEKS_REG */
720#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
721#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
722
723/* Bit definitions for ALARM_SECONDS_REG */
724#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
725#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
726#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
727#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
728
729/* Bit definitions for ALARM_MINUTES_REG */
730#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
731#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
732#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
733#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
734
735/* Bit definitions for ALARM_HOURS_REG */
736#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
737#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
738#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
739#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
740#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
741#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
742
743/* Bit definitions for ALARM_DAYS_REG */
744#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
745#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
746#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
747#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
748
749/* Bit definitions for ALARM_MONTHS_REG */
750#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
751#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
752#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
753#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
754
755/* Bit definitions for ALARM_YEARS_REG */
756#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
757#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
758#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
759#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
760
761/* Bit definitions for RTC_CTRL_REG */
762#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
763#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
764#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
765#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
766#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
767#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
768#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
769#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
770#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
771#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
772#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
773#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
774#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
775#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
776#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
777#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
778
779/* Bit definitions for RTC_STATUS_REG */
780#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
781#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
782#define PALMAS_RTC_STATUS_REG_ALARM 0x40
783#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
784#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
785#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
786#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
787#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
788#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
789#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
790#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
791#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
792#define PALMAS_RTC_STATUS_REG_RUN 0x02
793#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
794
795/* Bit definitions for RTC_INTERRUPTS_REG */
796#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
797#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
798#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
799#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
800#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
801#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
802#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
803#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
804
805/* Bit definitions for RTC_COMP_LSB_REG */
806#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
807#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
808
809/* Bit definitions for RTC_COMP_MSB_REG */
810#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
811#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
812
813/* Bit definitions for RTC_RES_PROG_REG */
814#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
815#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
816
817/* Bit definitions for RTC_RESET_STATUS_REG */
818#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
819#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
820
821/* Registers for function BACKUP */
822#define PALMAS_BACKUP0 0x00
823#define PALMAS_BACKUP1 0x01
824#define PALMAS_BACKUP2 0x02
825#define PALMAS_BACKUP3 0x03
826#define PALMAS_BACKUP4 0x04
827#define PALMAS_BACKUP5 0x05
828#define PALMAS_BACKUP6 0x06
829#define PALMAS_BACKUP7 0x07
830
831/* Bit definitions for BACKUP0 */
832#define PALMAS_BACKUP0_BACKUP_MASK 0xFF
833#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
834
835/* Bit definitions for BACKUP1 */
836#define PALMAS_BACKUP1_BACKUP_MASK 0xFF
837#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
838
839/* Bit definitions for BACKUP2 */
840#define PALMAS_BACKUP2_BACKUP_MASK 0xFF
841#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
842
843/* Bit definitions for BACKUP3 */
844#define PALMAS_BACKUP3_BACKUP_MASK 0xFF
845#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
846
847/* Bit definitions for BACKUP4 */
848#define PALMAS_BACKUP4_BACKUP_MASK 0xFF
849#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
850
851/* Bit definitions for BACKUP5 */
852#define PALMAS_BACKUP5_BACKUP_MASK 0xFF
853#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
854
855/* Bit definitions for BACKUP6 */
856#define PALMAS_BACKUP6_BACKUP_MASK 0xFF
857#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
858
859/* Bit definitions for BACKUP7 */
860#define PALMAS_BACKUP7_BACKUP_MASK 0xFF
861#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
862
863/* Registers for function SMPS */
864#define PALMAS_SMPS12_CTRL 0x00
865#define PALMAS_SMPS12_TSTEP 0x01
866#define PALMAS_SMPS12_FORCE 0x02
867#define PALMAS_SMPS12_VOLTAGE 0x03
868#define PALMAS_SMPS3_CTRL 0x04
869#define PALMAS_SMPS3_VOLTAGE 0x07
870#define PALMAS_SMPS45_CTRL 0x08
871#define PALMAS_SMPS45_TSTEP 0x09
872#define PALMAS_SMPS45_FORCE 0x0A
873#define PALMAS_SMPS45_VOLTAGE 0x0B
874#define PALMAS_SMPS6_CTRL 0x0C
875#define PALMAS_SMPS6_TSTEP 0x0D
876#define PALMAS_SMPS6_FORCE 0x0E
877#define PALMAS_SMPS6_VOLTAGE 0x0F
878#define PALMAS_SMPS7_CTRL 0x10
879#define PALMAS_SMPS7_VOLTAGE 0x13
880#define PALMAS_SMPS8_CTRL 0x14
881#define PALMAS_SMPS8_TSTEP 0x15
882#define PALMAS_SMPS8_FORCE 0x16
883#define PALMAS_SMPS8_VOLTAGE 0x17
884#define PALMAS_SMPS9_CTRL 0x18
885#define PALMAS_SMPS9_VOLTAGE 0x1B
886#define PALMAS_SMPS10_CTRL 0x1C
887#define PALMAS_SMPS10_STATUS 0x1F
888#define PALMAS_SMPS_CTRL 0x24
889#define PALMAS_SMPS_PD_CTRL 0x25
890#define PALMAS_SMPS_DITHER_EN 0x26
891#define PALMAS_SMPS_THERMAL_EN 0x27
892#define PALMAS_SMPS_THERMAL_STATUS 0x28
893#define PALMAS_SMPS_SHORT_STATUS 0x29
894#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
895#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
896#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
897
898/* Bit definitions for SMPS12_CTRL */
899#define PALMAS_SMPS12_CTRL_WR_S 0x80
900#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
901#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
902#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
903#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
904#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
905#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
906#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
907#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
908#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
909
910/* Bit definitions for SMPS12_TSTEP */
911#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
912#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
913
914/* Bit definitions for SMPS12_FORCE */
915#define PALMAS_SMPS12_FORCE_CMD 0x80
916#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
917#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
918#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
919
920/* Bit definitions for SMPS12_VOLTAGE */
921#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
922#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
923#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
924#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
925
926/* Bit definitions for SMPS3_CTRL */
927#define PALMAS_SMPS3_CTRL_WR_S 0x80
928#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
929#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
930#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
931#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
932#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
933#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
934#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
935
936/* Bit definitions for SMPS3_VOLTAGE */
937#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
938#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
939#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
940#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
941
942/* Bit definitions for SMPS45_CTRL */
943#define PALMAS_SMPS45_CTRL_WR_S 0x80
944#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
945#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
946#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
947#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
948#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
949#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
950#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
951#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
952#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
953
954/* Bit definitions for SMPS45_TSTEP */
955#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
956#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
957
958/* Bit definitions for SMPS45_FORCE */
959#define PALMAS_SMPS45_FORCE_CMD 0x80
960#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
961#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
962#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
963
964/* Bit definitions for SMPS45_VOLTAGE */
965#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
966#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
967#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
968#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
969
970/* Bit definitions for SMPS6_CTRL */
971#define PALMAS_SMPS6_CTRL_WR_S 0x80
972#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
973#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
974#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
975#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
976#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
977#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
978#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
979#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
980#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
981
982/* Bit definitions for SMPS6_TSTEP */
983#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
984#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
985
986/* Bit definitions for SMPS6_FORCE */
987#define PALMAS_SMPS6_FORCE_CMD 0x80
988#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
989#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
990#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
991
992/* Bit definitions for SMPS6_VOLTAGE */
993#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
994#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
995#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
996#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
997
998/* Bit definitions for SMPS7_CTRL */
999#define PALMAS_SMPS7_CTRL_WR_S 0x80
1000#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
1001#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
1002#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
1003#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
1004#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
1005#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
1006#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
1007
1008/* Bit definitions for SMPS7_VOLTAGE */
1009#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
1010#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
1011#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
1012#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
1013
1014/* Bit definitions for SMPS8_CTRL */
1015#define PALMAS_SMPS8_CTRL_WR_S 0x80
1016#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
1017#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
1018#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
1019#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
1020#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
1021#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
1022#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
1023#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
1024#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
1025
1026/* Bit definitions for SMPS8_TSTEP */
1027#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
1028#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
1029
1030/* Bit definitions for SMPS8_FORCE */
1031#define PALMAS_SMPS8_FORCE_CMD 0x80
1032#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
1033#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
1034#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
1035
1036/* Bit definitions for SMPS8_VOLTAGE */
1037#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
1038#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
1039#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
1040#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
1041
1042/* Bit definitions for SMPS9_CTRL */
1043#define PALMAS_SMPS9_CTRL_WR_S 0x80
1044#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
1045#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
1046#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
1047#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
1048#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
1049#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
1050#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
1051
1052/* Bit definitions for SMPS9_VOLTAGE */
1053#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
1054#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
1055#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
1056#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
1057
1058/* Bit definitions for SMPS10_CTRL */
1059#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
1060#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
1061#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
1062#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
1063
1064/* Bit definitions for SMPS10_STATUS */
1065#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
1066#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
1067
1068/* Bit definitions for SMPS_CTRL */
1069#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
1070#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
1071#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
1072#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
1073#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
1074#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
1075#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
1076#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
1077
1078/* Bit definitions for SMPS_PD_CTRL */
1079#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
1080#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
1081#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
1082#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
1083#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
1084#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
1085#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
1086#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
1087#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
1088#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
1089#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
1090#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
1091#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
1092#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
1093
1094/* Bit definitions for SMPS_THERMAL_EN */
1095#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
1096#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
1097#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
1098#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
1099#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
1100#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
1101#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
1102#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
1103#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
1104#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
1105
1106/* Bit definitions for SMPS_THERMAL_STATUS */
1107#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
1108#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
1109#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
1110#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
1111#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
1112#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
1113#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
1114#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
1115#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
1116#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
1117
1118/* Bit definitions for SMPS_SHORT_STATUS */
1119#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
1120#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
1121#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
1122#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
1123#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
1124#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
1125#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
1126#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
1127#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
1128#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
1129#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
1130#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
1131#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
1132#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
1133#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
1134#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
1135
1136/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1137#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
1138#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
1139#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
1140#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
1141#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
1142#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
1143#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
1144#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
1145#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
1146#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
1147#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
1148#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
1149#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
1150#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
1151
1152/* Bit definitions for SMPS_POWERGOOD_MASK1 */
1153#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1154#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1155#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1156#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1157#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1158#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1159#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1160#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1161#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1162#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1163#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1164#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1165#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1166#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1167#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1168#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1169
1170/* Bit definitions for SMPS_POWERGOOD_MASK2 */
1171#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1172#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1173#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1174#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1175#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1176#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1177#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1178#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1179
1180/* Registers for function LDO */
1181#define PALMAS_LDO1_CTRL 0x00
1182#define PALMAS_LDO1_VOLTAGE 0x01
1183#define PALMAS_LDO2_CTRL 0x02
1184#define PALMAS_LDO2_VOLTAGE 0x03
1185#define PALMAS_LDO3_CTRL 0x04
1186#define PALMAS_LDO3_VOLTAGE 0x05
1187#define PALMAS_LDO4_CTRL 0x06
1188#define PALMAS_LDO4_VOLTAGE 0x07
1189#define PALMAS_LDO5_CTRL 0x08
1190#define PALMAS_LDO5_VOLTAGE 0x09
1191#define PALMAS_LDO6_CTRL 0x0A
1192#define PALMAS_LDO6_VOLTAGE 0x0B
1193#define PALMAS_LDO7_CTRL 0x0C
1194#define PALMAS_LDO7_VOLTAGE 0x0D
1195#define PALMAS_LDO8_CTRL 0x0E
1196#define PALMAS_LDO8_VOLTAGE 0x0F
1197#define PALMAS_LDO9_CTRL 0x10
1198#define PALMAS_LDO9_VOLTAGE 0x11
1199#define PALMAS_LDOLN_CTRL 0x12
1200#define PALMAS_LDOLN_VOLTAGE 0x13
1201#define PALMAS_LDOUSB_CTRL 0x14
1202#define PALMAS_LDOUSB_VOLTAGE 0x15
1203#define PALMAS_LDO_CTRL 0x1A
1204#define PALMAS_LDO_PD_CTRL1 0x1B
1205#define PALMAS_LDO_PD_CTRL2 0x1C
1206#define PALMAS_LDO_SHORT_STATUS1 0x1D
1207#define PALMAS_LDO_SHORT_STATUS2 0x1E
1208
1209/* Bit definitions for LDO1_CTRL */
1210#define PALMAS_LDO1_CTRL_WR_S 0x80
1211#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1212#define PALMAS_LDO1_CTRL_STATUS 0x10
1213#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1214#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1215#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1216#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1217#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1218
1219/* Bit definitions for LDO1_VOLTAGE */
1220#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1221#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1222
1223/* Bit definitions for LDO2_CTRL */
1224#define PALMAS_LDO2_CTRL_WR_S 0x80
1225#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1226#define PALMAS_LDO2_CTRL_STATUS 0x10
1227#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1228#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1229#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1230#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1231#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1232
1233/* Bit definitions for LDO2_VOLTAGE */
1234#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1235#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1236
1237/* Bit definitions for LDO3_CTRL */
1238#define PALMAS_LDO3_CTRL_WR_S 0x80
1239#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1240#define PALMAS_LDO3_CTRL_STATUS 0x10
1241#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1242#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1243#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1244#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1245#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1246
1247/* Bit definitions for LDO3_VOLTAGE */
1248#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1249#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1250
1251/* Bit definitions for LDO4_CTRL */
1252#define PALMAS_LDO4_CTRL_WR_S 0x80
1253#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1254#define PALMAS_LDO4_CTRL_STATUS 0x10
1255#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1256#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1257#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1258#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1259#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1260
1261/* Bit definitions for LDO4_VOLTAGE */
1262#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1263#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1264
1265/* Bit definitions for LDO5_CTRL */
1266#define PALMAS_LDO5_CTRL_WR_S 0x80
1267#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1268#define PALMAS_LDO5_CTRL_STATUS 0x10
1269#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1270#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1271#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1272#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1273#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1274
1275/* Bit definitions for LDO5_VOLTAGE */
1276#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1277#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1278
1279/* Bit definitions for LDO6_CTRL */
1280#define PALMAS_LDO6_CTRL_WR_S 0x80
1281#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1282#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1283#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1284#define PALMAS_LDO6_CTRL_STATUS 0x10
1285#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1286#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1287#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1288#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1289#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1290
1291/* Bit definitions for LDO6_VOLTAGE */
1292#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1293#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1294
1295/* Bit definitions for LDO7_CTRL */
1296#define PALMAS_LDO7_CTRL_WR_S 0x80
1297#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1298#define PALMAS_LDO7_CTRL_STATUS 0x10
1299#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1300#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1301#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1302#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1303#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1304
1305/* Bit definitions for LDO7_VOLTAGE */
1306#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1307#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1308
1309/* Bit definitions for LDO8_CTRL */
1310#define PALMAS_LDO8_CTRL_WR_S 0x80
1311#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1312#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1313#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1314#define PALMAS_LDO8_CTRL_STATUS 0x10
1315#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1316#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1317#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1318#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1319#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1320
1321/* Bit definitions for LDO8_VOLTAGE */
1322#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1323#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1324
1325/* Bit definitions for LDO9_CTRL */
1326#define PALMAS_LDO9_CTRL_WR_S 0x80
1327#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1328#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1329#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1330#define PALMAS_LDO9_CTRL_STATUS 0x10
1331#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1332#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1333#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1334#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1335#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1336
1337/* Bit definitions for LDO9_VOLTAGE */
1338#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1339#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1340
1341/* Bit definitions for LDOLN_CTRL */
1342#define PALMAS_LDOLN_CTRL_WR_S 0x80
1343#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1344#define PALMAS_LDOLN_CTRL_STATUS 0x10
1345#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1346#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1347#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1348#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1349#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1350
1351/* Bit definitions for LDOLN_VOLTAGE */
1352#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1353#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1354
1355/* Bit definitions for LDOUSB_CTRL */
1356#define PALMAS_LDOUSB_CTRL_WR_S 0x80
1357#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1358#define PALMAS_LDOUSB_CTRL_STATUS 0x10
1359#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1360#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1361#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1362#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1363#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1364
1365/* Bit definitions for LDOUSB_VOLTAGE */
1366#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1367#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1368
1369/* Bit definitions for LDO_CTRL */
1370#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1371#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1372
1373/* Bit definitions for LDO_PD_CTRL1 */
1374#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1375#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1376#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1377#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1378#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1379#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1380#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1381#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1382#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1383#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1384#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1385#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1386#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1387#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1388#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1389#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1390
1391/* Bit definitions for LDO_PD_CTRL2 */
1392#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1393#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1394#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1395#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1396#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1397#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1398
1399/* Bit definitions for LDO_SHORT_STATUS1 */
1400#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1401#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1402#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1403#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1404#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1405#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1406#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1407#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1408#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1409#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1410#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1411#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1412#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1413#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1414#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1415#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1416
1417/* Bit definitions for LDO_SHORT_STATUS2 */
1418#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1419#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1420#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1421#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1422#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1423#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1424#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1425#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1426
1427/* Registers for function PMU_CONTROL */
1428#define PALMAS_DEV_CTRL 0x00
1429#define PALMAS_POWER_CTRL 0x01
1430#define PALMAS_VSYS_LO 0x02
1431#define PALMAS_VSYS_MON 0x03
1432#define PALMAS_VBAT_MON 0x04
1433#define PALMAS_WATCHDOG 0x05
1434#define PALMAS_BOOT_STATUS 0x06
1435#define PALMAS_BATTERY_BOUNCE 0x07
1436#define PALMAS_BACKUP_BATTERY_CTRL 0x08
1437#define PALMAS_LONG_PRESS_KEY 0x09
1438#define PALMAS_OSC_THERM_CTRL 0x0A
1439#define PALMAS_BATDEBOUNCING 0x0B
1440#define PALMAS_SWOFF_HWRST 0x0F
1441#define PALMAS_SWOFF_COLDRST 0x10
1442#define PALMAS_SWOFF_STATUS 0x11
1443#define PALMAS_PMU_CONFIG 0x12
1444#define PALMAS_SPARE 0x14
1445#define PALMAS_PMU_SECONDARY_INT 0x15
1446#define PALMAS_SW_REVISION 0x17
1447#define PALMAS_EXT_CHRG_CTRL 0x18
1448#define PALMAS_PMU_SECONDARY_INT2 0x19
1449
1450/* Bit definitions for DEV_CTRL */
1451#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1452#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1453#define PALMAS_DEV_CTRL_SW_RST 0x02
1454#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1455#define PALMAS_DEV_CTRL_DEV_ON 0x01
1456#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1457
1458/* Bit definitions for POWER_CTRL */
1459#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1460#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1461#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1462#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1463#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1464#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1465
1466/* Bit definitions for VSYS_LO */
1467#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1468#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1469
1470/* Bit definitions for VSYS_MON */
1471#define PALMAS_VSYS_MON_ENABLE 0x80
1472#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1473#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1474#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1475
1476/* Bit definitions for VBAT_MON */
1477#define PALMAS_VBAT_MON_ENABLE 0x80
1478#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1479#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1480#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1481
1482/* Bit definitions for WATCHDOG */
1483#define PALMAS_WATCHDOG_LOCK 0x20
1484#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1485#define PALMAS_WATCHDOG_ENABLE 0x10
1486#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1487#define PALMAS_WATCHDOG_MODE 0x08
1488#define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1489#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1490#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1491
1492/* Bit definitions for BOOT_STATUS */
1493#define PALMAS_BOOT_STATUS_BOOT1 0x02
1494#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1495#define PALMAS_BOOT_STATUS_BOOT0 0x01
1496#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1497
1498/* Bit definitions for BATTERY_BOUNCE */
1499#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1500#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1501
1502/* Bit definitions for BACKUP_BATTERY_CTRL */
1503#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1504#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1505#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1506#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1507#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1508#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1509#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1510#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1511#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1512#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1513#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1514#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1515#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1516#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1517
1518/* Bit definitions for LONG_PRESS_KEY */
1519#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1520#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1521#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1522#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1523#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1524#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1525#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1526#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1527
1528/* Bit definitions for OSC_THERM_CTRL */
1529#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1530#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1531#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1532#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1533#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1534#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1535#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1536#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1537#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1538#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1539#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1540#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1541#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1542#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1543
1544/* Bit definitions for BATDEBOUNCING */
1545#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1546#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1547#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1548#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1549#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1550#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1551
1552/* Bit definitions for SWOFF_HWRST */
1553#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1554#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1555#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1556#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1557#define PALMAS_SWOFF_HWRST_WTD 0x20
1558#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1559#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1560#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1561#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1562#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1563#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1564#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1565#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1566#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1567#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1568#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1569
1570/* Bit definitions for SWOFF_COLDRST */
1571#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1572#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1573#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1574#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1575#define PALMAS_SWOFF_COLDRST_WTD 0x20
1576#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1577#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1578#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1579#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1580#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1581#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1582#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1583#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1584#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1585#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1586#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1587
1588/* Bit definitions for SWOFF_STATUS */
1589#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1590#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1591#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1592#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1593#define PALMAS_SWOFF_STATUS_WTD 0x20
1594#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1595#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1596#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1597#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1598#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1599#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1600#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1601#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1602#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1603#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1604#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1605
1606/* Bit definitions for PMU_CONFIG */
1607#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1608#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1609#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1610#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1611#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1612#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1613#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1614#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1615#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1616#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1617
1618/* Bit definitions for SPARE */
1619#define PALMAS_SPARE_SPARE_MASK 0xf8
1620#define PALMAS_SPARE_SPARE_SHIFT 0x03
1621#define PALMAS_SPARE_REGEN3_OD 0x04
1622#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1623#define PALMAS_SPARE_REGEN2_OD 0x02
1624#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1625#define PALMAS_SPARE_REGEN1_OD 0x01
1626#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1627
1628/* Bit definitions for PMU_SECONDARY_INT */
1629#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1630#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1631#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1632#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1633#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1634#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1635#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1636#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1637#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1638#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1639#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1640#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1641#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1642#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1643#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1644#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1645
1646/* Bit definitions for SW_REVISION */
1647#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1648#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1649
1650/* Bit definitions for EXT_CHRG_CTRL */
1651#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1652#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1653#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1654#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1655#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1656#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1657#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1658#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1659#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1660#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1661#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1662#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1663
1664/* Bit definitions for PMU_SECONDARY_INT2 */
1665#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1666#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1667#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1668#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1669#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1670#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1671#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1672#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1673
1674/* Registers for function RESOURCE */
1675#define PALMAS_CLK32KG_CTRL 0x00
1676#define PALMAS_CLK32KGAUDIO_CTRL 0x01
1677#define PALMAS_REGEN1_CTRL 0x02
1678#define PALMAS_REGEN2_CTRL 0x03
1679#define PALMAS_SYSEN1_CTRL 0x04
1680#define PALMAS_SYSEN2_CTRL 0x05
1681#define PALMAS_NSLEEP_RES_ASSIGN 0x06
1682#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1683#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1684#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1685#define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1686#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1687#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1688#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1689#define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1690#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1691#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1692#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1693#define PALMAS_REGEN3_CTRL 0x12
1694
1695/* Bit definitions for CLK32KG_CTRL */
1696#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1697#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1698#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1699#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1700#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1701#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1702
1703/* Bit definitions for CLK32KGAUDIO_CTRL */
1704#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1705#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1706#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1707#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1708#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1709#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1710#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1711#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1712
1713/* Bit definitions for REGEN1_CTRL */
1714#define PALMAS_REGEN1_CTRL_STATUS 0x10
1715#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1716#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1717#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1718#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1719#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1720
1721/* Bit definitions for REGEN2_CTRL */
1722#define PALMAS_REGEN2_CTRL_STATUS 0x10
1723#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1724#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1725#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1726#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1727#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1728
1729/* Bit definitions for SYSEN1_CTRL */
1730#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1731#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1732#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1733#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1734#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1735#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1736
1737/* Bit definitions for SYSEN2_CTRL */
1738#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1739#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1740#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1741#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1742#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1743#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1744
1745/* Bit definitions for NSLEEP_RES_ASSIGN */
1746#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1747#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1748#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1749#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1750#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1751#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1752#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1753#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1754#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1755#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1756#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1757#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1758#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1759#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1760
1761/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1762#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1763#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1764#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1765#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1766#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1767#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1768#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1769#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1770#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1771#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1772#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1773#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1774#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1775#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1776#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1777#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1778
1779/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1780#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1781#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1782#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1783#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1784#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1785#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1786#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1787#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1788#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1789#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1790#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1791#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1792#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1793#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1794#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1795#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1796
1797/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1798#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1799#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1800#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1801#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1802#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1803#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1804
1805/* Bit definitions for ENABLE1_RES_ASSIGN */
1806#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1807#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1808#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1809#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1810#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1811#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1812#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1813#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1814#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1815#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1816#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1817#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1818#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1819#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1820
1821/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1822#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1823#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1824#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1825#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1826#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1827#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1828#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1829#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1830#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1831#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1832#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1833#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1834#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1835#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1836#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1837#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1838
1839/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1840#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1841#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1842#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1843#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1844#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1845#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1846#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1847#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1848#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1849#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1850#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1851#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1852#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1853#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1854#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1855#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1856
1857/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1858#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1859#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1860#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1861#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1862#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1863#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1864
1865/* Bit definitions for ENABLE2_RES_ASSIGN */
1866#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1867#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1868#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1869#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1870#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1871#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1872#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1873#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1874#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1875#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1876#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1877#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1878#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1879#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1880
1881/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1882#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1883#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1884#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1885#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1886#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1887#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1888#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1889#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1890#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1891#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1892#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1893#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1894#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1895#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1896#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1897#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1898
1899/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1900#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1901#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1902#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1903#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1904#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1905#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1906#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1907#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1908#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1909#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1910#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1911#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1912#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1913#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1914#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1915#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1916
1917/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1918#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1919#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1920#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1921#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1922#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1923#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1924
1925/* Bit definitions for REGEN3_CTRL */
1926#define PALMAS_REGEN3_CTRL_STATUS 0x10
1927#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1928#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1929#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1930#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1931#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1932
1933/* Registers for function PAD_CONTROL */
1934#define PALMAS_OD_OUTPUT_CTRL2 0x02
1935#define PALMAS_POLARITY_CTRL2 0x03
1936#define PALMAS_PU_PD_INPUT_CTRL1 0x04
1937#define PALMAS_PU_PD_INPUT_CTRL2 0x05
1938#define PALMAS_PU_PD_INPUT_CTRL3 0x06
1939#define PALMAS_PU_PD_INPUT_CTRL5 0x07
1940#define PALMAS_OD_OUTPUT_CTRL 0x08
1941#define PALMAS_POLARITY_CTRL 0x09
1942#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1943#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1944#define PALMAS_I2C_SPI 0x0C
1945#define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1946#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1947#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1948
1949/* Bit definitions for PU_PD_INPUT_CTRL1 */
1950#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1951#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1952#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1953#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1954#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1955#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1956#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1957#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1958#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1959#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1960
1961/* Bit definitions for PU_PD_INPUT_CTRL2 */
1962#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1963#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1964#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1965#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1966#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1967#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1968#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1969#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1970#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1971#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1972#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1973#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1974
1975/* Bit definitions for PU_PD_INPUT_CTRL3 */
1976#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1977#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1978#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1979#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1980#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1981#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1982#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1983#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1984
1985/* Bit definitions for OD_OUTPUT_CTRL */
1986#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1987#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
1988#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1989#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
1990#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1991#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
1992#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1993#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
1994
1995/* Bit definitions for POLARITY_CTRL */
1996#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1997#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
1998#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1999#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
2000#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
2001#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
2002#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
2003#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
2004#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
2005#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
2006#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
2007#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
2008#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
2009#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
2010#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
2011#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
2012
2013/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
2014#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
2015#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
2016#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
2017#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
2018#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
2019#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
2020#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
2021#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
2022#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
2023#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2024#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
2025#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2026
2027/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2028#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
2029#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2030#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
2031#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2032#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
2033#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2034#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
2035#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2036
2037/* Bit definitions for I2C_SPI */
2038#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
2039#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2040#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
2041#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2042#define PALMAS_I2C_SPI_ID_I2C2 0x20
2043#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2044#define PALMAS_I2C_SPI_I2C_SPI 0x10
2045#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
2046#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
2047#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2048
2049/* Bit definitions for PU_PD_INPUT_CTRL4 */
2050#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
2051#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2052#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
2053#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2054#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
2055#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2056#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
2057#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2058
2059/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2060#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
2061#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2062#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
2063#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2064
2065/* Registers for function LED_PWM */
2066#define PALMAS_LED_PERIOD_CTRL 0x00
2067#define PALMAS_LED_CTRL 0x01
2068#define PALMAS_PWM_CTRL1 0x02
2069#define PALMAS_PWM_CTRL2 0x03
2070
2071/* Bit definitions for LED_PERIOD_CTRL */
2072#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
2073#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2074#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
2075#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2076
2077/* Bit definitions for LED_CTRL */
2078#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
2079#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2080#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
2081#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2082#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
2083#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2084#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
2085#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2086
2087/* Bit definitions for PWM_CTRL1 */
2088#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
2089#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2090#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
2091#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2092
2093/* Bit definitions for PWM_CTRL2 */
2094#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2095#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2096
2097/* Registers for function INTERRUPT */
2098#define PALMAS_INT1_STATUS 0x00
2099#define PALMAS_INT1_MASK 0x01
2100#define PALMAS_INT1_LINE_STATE 0x02
2101#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2102#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2103#define PALMAS_INT2_STATUS 0x05
2104#define PALMAS_INT2_MASK 0x06
2105#define PALMAS_INT2_LINE_STATE 0x07
2106#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2107#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2108#define PALMAS_INT3_STATUS 0x0A
2109#define PALMAS_INT3_MASK 0x0B
2110#define PALMAS_INT3_LINE_STATE 0x0C
2111#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2112#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2113#define PALMAS_INT4_STATUS 0x0F
2114#define PALMAS_INT4_MASK 0x10
2115#define PALMAS_INT4_LINE_STATE 0x11
2116#define PALMAS_INT4_EDGE_DETECT1 0x12
2117#define PALMAS_INT4_EDGE_DETECT2 0x13
2118#define PALMAS_INT_CTRL 0x14
2119
2120/* Bit definitions for INT1_STATUS */
2121#define PALMAS_INT1_STATUS_VBAT_MON 0x80
2122#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2123#define PALMAS_INT1_STATUS_VSYS_MON 0x40
2124#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2125#define PALMAS_INT1_STATUS_HOTDIE 0x20
2126#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2127#define PALMAS_INT1_STATUS_PWRDOWN 0x10
2128#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2129#define PALMAS_INT1_STATUS_RPWRON 0x08
2130#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2131#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
2132#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2133#define PALMAS_INT1_STATUS_PWRON 0x02
2134#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2135#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
2136#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2137
2138/* Bit definitions for INT1_MASK */
2139#define PALMAS_INT1_MASK_VBAT_MON 0x80
2140#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2141#define PALMAS_INT1_MASK_VSYS_MON 0x40
2142#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2143#define PALMAS_INT1_MASK_HOTDIE 0x20
2144#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2145#define PALMAS_INT1_MASK_PWRDOWN 0x10
2146#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2147#define PALMAS_INT1_MASK_RPWRON 0x08
2148#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2149#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
2150#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2151#define PALMAS_INT1_MASK_PWRON 0x02
2152#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2153#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2154#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2155
2156/* Bit definitions for INT1_LINE_STATE */
2157#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2158#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2159#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2160#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2161#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2162#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2163#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2164#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2165#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2166#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2167#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2168#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2169#define PALMAS_INT1_LINE_STATE_PWRON 0x02
2170#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2171#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2172#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2173
2174/* Bit definitions for INT2_STATUS */
2175#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2176#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2177#define PALMAS_INT2_STATUS_SHORT 0x40
2178#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2179#define PALMAS_INT2_STATUS_FBI_BB 0x20
2180#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2181#define PALMAS_INT2_STATUS_RESET_IN 0x10
2182#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2183#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2184#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2185#define PALMAS_INT2_STATUS_WDT 0x04
2186#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2187#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2188#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2189#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2190#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2191
2192/* Bit definitions for INT2_MASK */
2193#define PALMAS_INT2_MASK_VAC_ACOK 0x80
2194#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2195#define PALMAS_INT2_MASK_SHORT 0x40
2196#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2197#define PALMAS_INT2_MASK_FBI_BB 0x20
2198#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2199#define PALMAS_INT2_MASK_RESET_IN 0x10
2200#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2201#define PALMAS_INT2_MASK_BATREMOVAL 0x08
2202#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2203#define PALMAS_INT2_MASK_WDT 0x04
2204#define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2205#define PALMAS_INT2_MASK_RTC_TIMER 0x02
2206#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2207#define PALMAS_INT2_MASK_RTC_ALARM 0x01
2208#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2209
2210/* Bit definitions for INT2_LINE_STATE */
2211#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2212#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2213#define PALMAS_INT2_LINE_STATE_SHORT 0x40
2214#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2215#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2216#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2217#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2218#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2219#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2220#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2221#define PALMAS_INT2_LINE_STATE_WDT 0x04
2222#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2223#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2224#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2225#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2226#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2227
2228/* Bit definitions for INT3_STATUS */
2229#define PALMAS_INT3_STATUS_VBUS 0x80
2230#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2231#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2232#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2233#define PALMAS_INT3_STATUS_ID 0x20
2234#define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2235#define PALMAS_INT3_STATUS_ID_OTG 0x10
2236#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2237#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2238#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2239#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2240#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2241#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2242#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2243#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2244#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2245
2246/* Bit definitions for INT3_MASK */
2247#define PALMAS_INT3_MASK_VBUS 0x80
2248#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2249#define PALMAS_INT3_MASK_VBUS_OTG 0x40
2250#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2251#define PALMAS_INT3_MASK_ID 0x20
2252#define PALMAS_INT3_MASK_ID_SHIFT 0x05
2253#define PALMAS_INT3_MASK_ID_OTG 0x10
2254#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2255#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2256#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2257#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2258#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2259#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2260#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2261#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2262#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2263
2264/* Bit definitions for INT3_LINE_STATE */
2265#define PALMAS_INT3_LINE_STATE_VBUS 0x80
2266#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2267#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2268#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2269#define PALMAS_INT3_LINE_STATE_ID 0x20
2270#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2271#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2272#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2273#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2274#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2275#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2276#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2277#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2278#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2279#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2280#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2281
2282/* Bit definitions for INT4_STATUS */
2283#define PALMAS_INT4_STATUS_GPIO_7 0x80
2284#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2285#define PALMAS_INT4_STATUS_GPIO_6 0x40
2286#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2287#define PALMAS_INT4_STATUS_GPIO_5 0x20
2288#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2289#define PALMAS_INT4_STATUS_GPIO_4 0x10
2290#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2291#define PALMAS_INT4_STATUS_GPIO_3 0x08
2292#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2293#define PALMAS_INT4_STATUS_GPIO_2 0x04
2294#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2295#define PALMAS_INT4_STATUS_GPIO_1 0x02
2296#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2297#define PALMAS_INT4_STATUS_GPIO_0 0x01
2298#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2299
2300/* Bit definitions for INT4_MASK */
2301#define PALMAS_INT4_MASK_GPIO_7 0x80
2302#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2303#define PALMAS_INT4_MASK_GPIO_6 0x40
2304#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2305#define PALMAS_INT4_MASK_GPIO_5 0x20
2306#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2307#define PALMAS_INT4_MASK_GPIO_4 0x10
2308#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2309#define PALMAS_INT4_MASK_GPIO_3 0x08
2310#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2311#define PALMAS_INT4_MASK_GPIO_2 0x04
2312#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2313#define PALMAS_INT4_MASK_GPIO_1 0x02
2314#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2315#define PALMAS_INT4_MASK_GPIO_0 0x01
2316#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2317
2318/* Bit definitions for INT4_LINE_STATE */
2319#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2320#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2321#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2322#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2323#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2324#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2325#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2326#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2327#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2328#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2329#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2330#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2331#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2332#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2333#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2334#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2335
2336/* Bit definitions for INT4_EDGE_DETECT1 */
2337#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2338#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2339#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2340#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2341#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2342#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2343#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2344#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2345#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2346#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2347#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2348#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2349#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2350#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2351#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2352#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2353
2354/* Bit definitions for INT4_EDGE_DETECT2 */
2355#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2356#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2357#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2358#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2359#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2360#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2361#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2362#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2363#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2364#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2365#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2366#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2367#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2368#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2369#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2370#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2371
2372/* Bit definitions for INT_CTRL */
2373#define PALMAS_INT_CTRL_INT_PENDING 0x04
2374#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2375#define PALMAS_INT_CTRL_INT_CLEAR 0x01
2376#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2377
2378/* Registers for function USB_OTG */
2379#define PALMAS_USB_WAKEUP 0x03
2380#define PALMAS_USB_VBUS_CTRL_SET 0x04
2381#define PALMAS_USB_VBUS_CTRL_CLR 0x05
2382#define PALMAS_USB_ID_CTRL_SET 0x06
2383#define PALMAS_USB_ID_CTRL_CLEAR 0x07
2384#define PALMAS_USB_VBUS_INT_SRC 0x08
2385#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2386#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2387#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2388#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2389#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2390#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2391#define PALMAS_USB_ID_INT_SRC 0x0F
2392#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2393#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2394#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2395#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2396#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2397#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2398#define PALMAS_USB_OTG_ADP_CTRL 0x16
2399#define PALMAS_USB_OTG_ADP_HIGH 0x17
2400#define PALMAS_USB_OTG_ADP_LOW 0x18
2401#define PALMAS_USB_OTG_ADP_RISE 0x19
2402#define PALMAS_USB_OTG_REVISION 0x1A
2403
2404/* Bit definitions for USB_WAKEUP */
2405#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2406#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2407
2408/* Bit definitions for USB_VBUS_CTRL_SET */
2409#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2410#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2411#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2412#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2413#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2414#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2415#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2416#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2417#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2418#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2419
2420/* Bit definitions for USB_VBUS_CTRL_CLR */
2421#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2422#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2423#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2424#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2425#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2426#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2427#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2428#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2429#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2430#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2431
2432/* Bit definitions for USB_ID_CTRL_SET */
2433#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2434#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2435#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2436#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2437#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2438#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2439#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2440#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2441#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2442#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2443#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2444#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2445
2446/* Bit definitions for USB_ID_CTRL_CLEAR */
2447#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2448#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2449#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2450#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2451#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2452#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2453#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2454#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2455#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2456#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2457#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2458#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2459
2460/* Bit definitions for USB_VBUS_INT_SRC */
2461#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2462#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2463#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2464#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2465#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2466#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2467#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2468#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2469#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2470#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2471#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2472#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2473#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2474#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2475
2476/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2477#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2478#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2479#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2480#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2481#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2482#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2483#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2484#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2485#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2486#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2487#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2488#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2489#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2490#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2491#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2492#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2493
2494/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2495#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2496#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2497#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2498#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2499#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2500#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2501#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2502#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2503#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2504#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2505#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2506#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2507#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2508#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2509#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2510#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2511
2512/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2513#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2514#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2515#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2516#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2517#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2518#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2519#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2520#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2521#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2522#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2523#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2524#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2525#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2526#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2527
2528/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2529#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2530#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2531#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2532#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2533#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2534#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2535#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2536#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2537#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2538#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2539#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2540#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2541#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2542#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2543
2544/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2545#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2546#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2547#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2548#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2549#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2550#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2551#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2552#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2553#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2554#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2555#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2556#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2557#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2558#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2559#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2560#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2561
2562/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2563#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2564#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2565#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2566#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2567#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2568#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2569#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2570#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2571#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2572#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2573#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2574#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2575#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2576#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2577#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2578#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2579
2580/* Bit definitions for USB_ID_INT_SRC */
2581#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2582#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2583#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2584#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2585#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2586#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2587#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2588#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2589#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2590#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2591
2592/* Bit definitions for USB_ID_INT_LATCH_SET */
2593#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2594#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2595#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2596#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2597#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2598#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2599#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2600#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2601#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2602#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2603
2604/* Bit definitions for USB_ID_INT_LATCH_CLR */
2605#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2606#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2607#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2608#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2609#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2610#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2611#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2612#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2613#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2614#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2615
2616/* Bit definitions for USB_ID_INT_EN_LO_SET */
2617#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2618#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2619#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2620#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2621#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2622#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2623#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2624#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2625#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2626#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2627
2628/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2629#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2630#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2631#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2632#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2633#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2634#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2635#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2636#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2637#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2638#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2639
2640/* Bit definitions for USB_ID_INT_EN_HI_SET */
2641#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2642#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2643#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2644#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2645#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2646#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2647#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2648#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2649#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2650#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2651
2652/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2653#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2654#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2655#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2656#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2657#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2658#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2659#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2660#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2661#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2662#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2663
2664/* Bit definitions for USB_OTG_ADP_CTRL */
2665#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2666#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2667#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2668#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2669
2670/* Bit definitions for USB_OTG_ADP_HIGH */
2671#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2672#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2673
2674/* Bit definitions for USB_OTG_ADP_LOW */
2675#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2676#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2677
2678/* Bit definitions for USB_OTG_ADP_RISE */
2679#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2680#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2681
2682/* Bit definitions for USB_OTG_REVISION */
2683#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2684#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2685
2686/* Registers for function VIBRATOR */
2687#define PALMAS_VIBRA_CTRL 0x00
2688
2689/* Bit definitions for VIBRA_CTRL */
2690#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2691#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2692#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2693#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2694
2695/* Registers for function GPIO */
2696#define PALMAS_GPIO_DATA_IN 0x00
2697#define PALMAS_GPIO_DATA_DIR 0x01
2698#define PALMAS_GPIO_DATA_OUT 0x02
2699#define PALMAS_GPIO_DEBOUNCE_EN 0x03
2700#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2701#define PALMAS_GPIO_SET_DATA_OUT 0x05
2702#define PALMAS_PU_PD_GPIO_CTRL1 0x06
2703#define PALMAS_PU_PD_GPIO_CTRL2 0x07
2704#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2705#define PALMAS_GPIO_DATA_IN2 0x09
2706#define PALMAS_GPIO_DATA_DIR2 0x0A
2707#define PALMAS_GPIO_DATA_OUT2 0x0B
2708#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2709#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2710#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2711#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2712#define PALMAS_PU_PD_GPIO_CTRL4 0x10
2713#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2714
2715/* Bit definitions for GPIO_DATA_IN */
2716#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2717#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2718#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2719#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2720#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2721#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2722#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2723#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2724#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2725#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2726#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2727#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2728#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2729#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2730#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2731#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2732
2733/* Bit definitions for GPIO_DATA_DIR */
2734#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2735#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2736#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2737#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2738#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2739#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2740#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2741#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2742#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2743#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2744#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2745#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2746#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2747#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2748#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2749#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2750
2751/* Bit definitions for GPIO_DATA_OUT */
2752#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2753#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2754#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2755#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2756#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2757#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2758#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2759#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2760#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2761#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2762#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2763#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2764#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2765#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2766#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2767#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2768
2769/* Bit definitions for GPIO_DEBOUNCE_EN */
2770#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2771#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2772#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2773#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2774#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2775#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2776#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2777#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2778#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2779#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2780#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2781#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2782#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2783#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2784#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2785#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2786
2787/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2788#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2789#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2790#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2791#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2792#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2793#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2794#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2795#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2796#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2797#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2798#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2799#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2800#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2801#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2802#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2803#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2804
2805/* Bit definitions for GPIO_SET_DATA_OUT */
2806#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2807#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2808#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2809#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2810#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2811#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2812#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2813#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2814#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2815#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2816#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2817#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2818#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2819#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2820#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2821#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2822
2823/* Bit definitions for PU_PD_GPIO_CTRL1 */
2824#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2825#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2826#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2827#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2828#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2829#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2830#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2831#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2832#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2833#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2834#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2835#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2836
2837/* Bit definitions for PU_PD_GPIO_CTRL2 */
2838#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2839#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2840#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2841#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2842#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2843#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2844#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2845#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2846#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2847#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2848#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2849#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2850#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2851#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2852
2853/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2854#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2855#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2856#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2857#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2858#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2859#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2860
2861/* Registers for function GPADC */
2862#define PALMAS_GPADC_CTRL1 0x00
2863#define PALMAS_GPADC_CTRL2 0x01
2864#define PALMAS_GPADC_RT_CTRL 0x02
2865#define PALMAS_GPADC_AUTO_CTRL 0x03
2866#define PALMAS_GPADC_STATUS 0x04
2867#define PALMAS_GPADC_RT_SELECT 0x05
2868#define PALMAS_GPADC_RT_CONV0_LSB 0x06
2869#define PALMAS_GPADC_RT_CONV0_MSB 0x07
2870#define PALMAS_GPADC_AUTO_SELECT 0x08
2871#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2872#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2873#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2874#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2875#define PALMAS_GPADC_SW_SELECT 0x0D
2876#define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2877#define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2878#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2879#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2880#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2881#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2882#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2883#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2884
2885/* Bit definitions for GPADC_CTRL1 */
2886#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2887#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2888#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2889#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2890#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2891#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2892#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2893#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2894#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2895#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2896
2897/* Bit definitions for GPADC_CTRL2 */
2898#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2899#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2900
2901/* Bit definitions for GPADC_RT_CTRL */
2902#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2903#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2904#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2905#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2906
2907/* Bit definitions for GPADC_AUTO_CTRL */
2908#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2909#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2910#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2911#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2912#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2913#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2914#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2915#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2916#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2917#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2918
2919/* Bit definitions for GPADC_STATUS */
2920#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2921#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2922
2923/* Bit definitions for GPADC_RT_SELECT */
2924#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2925#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2926#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2927#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2928
2929/* Bit definitions for GPADC_RT_CONV0_LSB */
2930#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2931#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2932
2933/* Bit definitions for GPADC_RT_CONV0_MSB */
2934#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2935#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2936
2937/* Bit definitions for GPADC_AUTO_SELECT */
2938#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2939#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2940#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2941#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2942
2943/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2944#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2945#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2946
2947/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2948#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2949#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2950
2951/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2952#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2953#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2954
2955/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2956#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2957#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2958
2959/* Bit definitions for GPADC_SW_SELECT */
2960#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2961#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2962#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2963#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2964#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2965#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2966
2967/* Bit definitions for GPADC_SW_CONV0_LSB */
2968#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2969#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2970
2971/* Bit definitions for GPADC_SW_CONV0_MSB */
2972#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2973#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2974
2975/* Bit definitions for GPADC_THRES_CONV0_LSB */
2976#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2977#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2978
2979/* Bit definitions for GPADC_THRES_CONV0_MSB */
2980#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2981#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2982#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2983#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2984
2985/* Bit definitions for GPADC_THRES_CONV1_LSB */
2986#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2987#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2988
2989/* Bit definitions for GPADC_THRES_CONV1_MSB */
2990#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2991#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2992#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2993#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2994
2995/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2996#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2997#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2998#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2999#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
3000#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
3001#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
3002
3003/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
3004#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
3005#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
3006#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
3007#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
3008
3009/* Registers for function GPADC */
3010#define PALMAS_GPADC_TRIM1 0x00
3011#define PALMAS_GPADC_TRIM2 0x01
3012#define PALMAS_GPADC_TRIM3 0x02
3013#define PALMAS_GPADC_TRIM4 0x03
3014#define PALMAS_GPADC_TRIM5 0x04
3015#define PALMAS_GPADC_TRIM6 0x05
3016#define PALMAS_GPADC_TRIM7 0x06
3017#define PALMAS_GPADC_TRIM8 0x07
3018#define PALMAS_GPADC_TRIM9 0x08
3019#define PALMAS_GPADC_TRIM10 0x09
3020#define PALMAS_GPADC_TRIM11 0x0A
3021#define PALMAS_GPADC_TRIM12 0x0B
3022#define PALMAS_GPADC_TRIM13 0x0C
3023#define PALMAS_GPADC_TRIM14 0x0D
3024#define PALMAS_GPADC_TRIM15 0x0E
3025#define PALMAS_GPADC_TRIM16 0x0F
3026
3027/* TPS659038 regen2_ctrl offset iss different from palmas */
3028#define TPS659038_REGEN2_CTRL 0x12
3029
3030/* TPS65917 Interrupt registers */
3031
3032/* Registers for function INTERRUPT */
3033#define TPS65917_INT1_STATUS 0x00
3034#define TPS65917_INT1_MASK 0x01
3035#define TPS65917_INT1_LINE_STATE 0x02
3036#define TPS65917_INT2_STATUS 0x05
3037#define TPS65917_INT2_MASK 0x06
3038#define TPS65917_INT2_LINE_STATE 0x07
3039#define TPS65917_INT3_STATUS 0x0A
3040#define TPS65917_INT3_MASK 0x0B
3041#define TPS65917_INT3_LINE_STATE 0x0C
3042#define TPS65917_INT4_STATUS 0x0F
3043#define TPS65917_INT4_MASK 0x10
3044#define TPS65917_INT4_LINE_STATE 0x11
3045#define TPS65917_INT4_EDGE_DETECT1 0x12
3046#define TPS65917_INT4_EDGE_DETECT2 0x13
3047#define TPS65917_INT_CTRL 0x14
3048
3049/* Bit definitions for INT1_STATUS */
3050#define TPS65917_INT1_STATUS_VSYS_MON 0x40
3051#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
3052#define TPS65917_INT1_STATUS_HOTDIE 0x20
3053#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3054#define TPS65917_INT1_STATUS_PWRDOWN 0x10
3055#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3056#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3057#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3058#define TPS65917_INT1_STATUS_PWRON 0x02
3059#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3060
3061/* Bit definitions for INT1_MASK */
3062#define TPS65917_INT1_MASK_VSYS_MON 0x40
3063#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3064#define TPS65917_INT1_MASK_HOTDIE 0x20
3065#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3066#define TPS65917_INT1_MASK_PWRDOWN 0x10
3067#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3068#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3069#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3070#define TPS65917_INT1_MASK_PWRON 0x02
3071#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3072
3073/* Bit definitions for INT1_LINE_STATE */
3074#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3075#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3076#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3077#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3078#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3079#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3080#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3081#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3082#define TPS65917_INT1_LINE_STATE_PWRON 0x02
3083#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3084
3085/* Bit definitions for INT2_STATUS */
3086#define TPS65917_INT2_STATUS_SHORT 0x40
3087#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3088#define TPS65917_INT2_STATUS_FSD 0x20
3089#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3090#define TPS65917_INT2_STATUS_RESET_IN 0x10
3091#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3092#define TPS65917_INT2_STATUS_WDT 0x04
3093#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3094#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3095#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3096
3097/* Bit definitions for INT2_MASK */
3098#define TPS65917_INT2_MASK_SHORT 0x40
3099#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3100#define TPS65917_INT2_MASK_FSD 0x20
3101#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3102#define TPS65917_INT2_MASK_RESET_IN 0x10
3103#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3104#define TPS65917_INT2_MASK_WDT 0x04
3105#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3106#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3107#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3108
3109/* Bit definitions for INT2_LINE_STATE */
3110#define TPS65917_INT2_LINE_STATE_SHORT 0x40
3111#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3112#define TPS65917_INT2_LINE_STATE_FSD 0x20
3113#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3114#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3115#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3116#define TPS65917_INT2_LINE_STATE_WDT 0x04
3117#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3118#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3119#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3120
3121/* Bit definitions for INT3_STATUS */
3122#define TPS65917_INT3_STATUS_VBUS 0x80
3123#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3124#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3125#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3126#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3127#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3128#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3129#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3130
3131/* Bit definitions for INT3_MASK */
3132#define TPS65917_INT3_MASK_VBUS 0x80
3133#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3134#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3135#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3136#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3137#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3138#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3139#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3140
3141/* Bit definitions for INT3_LINE_STATE */
3142#define TPS65917_INT3_LINE_STATE_VBUS 0x80
3143#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3144#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3145#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3146#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3147#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3148#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3149#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3150
3151/* Bit definitions for INT4_STATUS */
3152#define TPS65917_INT4_STATUS_GPIO_6 0x40
3153#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3154#define TPS65917_INT4_STATUS_GPIO_5 0x20
3155#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3156#define TPS65917_INT4_STATUS_GPIO_4 0x10
3157#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3158#define TPS65917_INT4_STATUS_GPIO_3 0x08
3159#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3160#define TPS65917_INT4_STATUS_GPIO_2 0x04
3161#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3162#define TPS65917_INT4_STATUS_GPIO_1 0x02
3163#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3164#define TPS65917_INT4_STATUS_GPIO_0 0x01
3165#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3166
3167/* Bit definitions for INT4_MASK */
3168#define TPS65917_INT4_MASK_GPIO_6 0x40
3169#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3170#define TPS65917_INT4_MASK_GPIO_5 0x20
3171#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3172#define TPS65917_INT4_MASK_GPIO_4 0x10
3173#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3174#define TPS65917_INT4_MASK_GPIO_3 0x08
3175#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3176#define TPS65917_INT4_MASK_GPIO_2 0x04
3177#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3178#define TPS65917_INT4_MASK_GPIO_1 0x02
3179#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3180#define TPS65917_INT4_MASK_GPIO_0 0x01
3181#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3182
3183/* Bit definitions for INT4_LINE_STATE */
3184#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3185#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3186#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3187#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3188#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3189#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3190#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3191#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3192#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3193#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3194#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3195#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3196#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3197#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3198
3199/* Bit definitions for INT4_EDGE_DETECT1 */
3200#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3201#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3202#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3203#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3204#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3205#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3206#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3207#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3208#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3209#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3210#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3211#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3212#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3213#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3214#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3215#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3216
3217/* Bit definitions for INT4_EDGE_DETECT2 */
3218#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3219#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3220#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3221#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3222#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3223#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3224#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3225#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3226#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3227#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3228#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3229#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3230
3231/* Bit definitions for INT_CTRL */
3232#define TPS65917_INT_CTRL_INT_PENDING 0x04
3233#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3234#define TPS65917_INT_CTRL_INT_CLEAR 0x01
3235#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3236
3237/* TPS65917 SMPS Registers */
3238
3239/* Registers for function SMPS */
3240#define TPS65917_SMPS1_CTRL 0x00
3241#define TPS65917_SMPS1_FORCE 0x02
3242#define TPS65917_SMPS1_VOLTAGE 0x03
3243#define TPS65917_SMPS2_CTRL 0x04
3244#define TPS65917_SMPS2_FORCE 0x06
3245#define TPS65917_SMPS2_VOLTAGE 0x07
3246#define TPS65917_SMPS3_CTRL 0x0C
3247#define TPS65917_SMPS3_FORCE 0x0E
3248#define TPS65917_SMPS3_VOLTAGE 0x0F
3249#define TPS65917_SMPS4_CTRL 0x10
3250#define TPS65917_SMPS4_VOLTAGE 0x13
3251#define TPS65917_SMPS5_CTRL 0x18
3252#define TPS65917_SMPS5_VOLTAGE 0x1B
3253#define TPS65917_SMPS_CTRL 0x24
3254#define TPS65917_SMPS_PD_CTRL 0x25
3255#define TPS65917_SMPS_THERMAL_EN 0x27
3256#define TPS65917_SMPS_THERMAL_STATUS 0x28
3257#define TPS65917_SMPS_SHORT_STATUS 0x29
3258#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3259#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3260#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3261
3262/* Bit definitions for SMPS1_CTRL */
3263#define TPS65917_SMPS1_CTRL_WR_S 0x80
3264#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3265#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3266#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3267#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3268#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3269#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3270#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3271#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3272#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3273
3274/* Bit definitions for SMPS1_FORCE */
3275#define TPS65917_SMPS1_FORCE_CMD 0x80
3276#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3277#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3278#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3279
3280/* Bit definitions for SMPS1_VOLTAGE */
3281#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3282#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3283#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3284#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3285
3286/* Bit definitions for SMPS2_CTRL */
3287#define TPS65917_SMPS2_CTRL_WR_S 0x80
3288#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3289#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3290#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3291#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3292#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3293#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3294#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3295#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3296#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3297
3298/* Bit definitions for SMPS2_FORCE */
3299#define TPS65917_SMPS2_FORCE_CMD 0x80
3300#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3301#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3302#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3303
3304/* Bit definitions for SMPS2_VOLTAGE */
3305#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3306#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3307#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3308#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3309
3310/* Bit definitions for SMPS3_CTRL */
3311#define TPS65917_SMPS3_CTRL_WR_S 0x80
3312#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3313#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3314#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3315#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3316#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3317#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3318#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3319#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3320#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3321
3322/* Bit definitions for SMPS3_FORCE */
3323#define TPS65917_SMPS3_FORCE_CMD 0x80
3324#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3325#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3326#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3327
3328/* Bit definitions for SMPS3_VOLTAGE */
3329#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3330#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3331#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3332#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3333
3334/* Bit definitions for SMPS4_CTRL */
3335#define TPS65917_SMPS4_CTRL_WR_S 0x80
3336#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3337#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3338#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3339#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3340#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3341#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3342#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3343#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3344#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3345
3346/* Bit definitions for SMPS4_VOLTAGE */
3347#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3348#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3349#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3350#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3351
3352/* Bit definitions for SMPS5_CTRL */
3353#define TPS65917_SMPS5_CTRL_WR_S 0x80
3354#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3355#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3356#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3357#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3358#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3359#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3360#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3361#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3362#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3363
3364/* Bit definitions for SMPS5_VOLTAGE */
3365#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3366#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3367#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3368#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3369
3370/* Bit definitions for SMPS_CTRL */
3371#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3372#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3373#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3374#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3375
3376/* Bit definitions for SMPS_PD_CTRL */
3377#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3378#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3379#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3380#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3381#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3382#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3383#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3384#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3385#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3386#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3387
3388/* Bit definitions for SMPS_THERMAL_EN */
3389#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3390#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3391#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3392#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3393#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3394#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3395
3396/* Bit definitions for SMPS_THERMAL_STATUS */
3397#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3398#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3399#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3400#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3401#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3402#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3403
3404/* Bit definitions for SMPS_SHORT_STATUS */
3405#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3406#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3407#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3408#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3409#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3410#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3411#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3412#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3413#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3414#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3415
3416/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3417#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3418#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3419#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3420#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3421#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3422#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3423#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3424#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3425#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3426#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3427
3428/* Bit definitions for SMPS_POWERGOOD_MASK1 */
3429#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3430#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3431#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3432#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3433#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3434#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3435#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3436#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3437#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3438#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3439
3440/* Bit definitions for SMPS_POWERGOOD_MASK2 */
3441#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3442#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3443#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3444#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3445
3446/* Bit definitions for SMPS_PLL_CTRL */
3447
3448#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3449#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3450#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3451#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3452
3453/* Registers for function LDO */
3454#define TPS65917_LDO1_CTRL 0x00
3455#define TPS65917_LDO1_VOLTAGE 0x01
3456#define TPS65917_LDO2_CTRL 0x02
3457#define TPS65917_LDO2_VOLTAGE 0x03
3458#define TPS65917_LDO3_CTRL 0x04
3459#define TPS65917_LDO3_VOLTAGE 0x05
3460#define TPS65917_LDO4_CTRL 0x0E
3461#define TPS65917_LDO4_VOLTAGE 0x0F
3462#define TPS65917_LDO5_CTRL 0x12
3463#define TPS65917_LDO5_VOLTAGE 0x13
3464#define TPS65917_LDO_PD_CTRL1 0x1B
3465#define TPS65917_LDO_PD_CTRL2 0x1C
3466#define TPS65917_LDO_SHORT_STATUS1 0x1D
3467#define TPS65917_LDO_SHORT_STATUS2 0x1E
3468#define TPS65917_LDO_PD_CTRL3 0x2D
3469#define TPS65917_LDO_SHORT_STATUS3 0x2E
3470
3471/* Bit definitions for LDO1_CTRL */
3472#define TPS65917_LDO1_CTRL_WR_S 0x80
3473#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3474#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3475#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3476#define TPS65917_LDO1_CTRL_STATUS 0x10
3477#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3478#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3479#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3480#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3481#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3482
3483/* Bit definitions for LDO1_VOLTAGE */
3484#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3485#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3486
3487/* Bit definitions for LDO2_CTRL */
3488#define TPS65917_LDO2_CTRL_WR_S 0x80
3489#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3490#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3491#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3492#define TPS65917_LDO2_CTRL_STATUS 0x10
3493#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3494#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3495#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3496#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3497#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3498
3499/* Bit definitions for LDO2_VOLTAGE */
3500#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3501#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3502
3503/* Bit definitions for LDO3_CTRL */
3504#define TPS65917_LDO3_CTRL_WR_S 0x80
3505#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3506#define TPS65917_LDO3_CTRL_STATUS 0x10
3507#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3508#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3509#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3510#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3511#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3512
3513/* Bit definitions for LDO3_VOLTAGE */
3514#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3515#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3516
3517/* Bit definitions for LDO4_CTRL */
3518#define TPS65917_LDO4_CTRL_WR_S 0x80
3519#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3520#define TPS65917_LDO4_CTRL_STATUS 0x10
3521#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3522#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3523#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3524#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3525#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3526
3527/* Bit definitions for LDO4_VOLTAGE */
3528#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3529#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3530
3531/* Bit definitions for LDO5_CTRL */
3532#define TPS65917_LDO5_CTRL_WR_S 0x80
3533#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3534#define TPS65917_LDO5_CTRL_STATUS 0x10
3535#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3536#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3537#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3538#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3539#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3540
3541/* Bit definitions for LDO5_VOLTAGE */
3542#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3543#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3544
3545/* Bit definitions for LDO_PD_CTRL1 */
3546#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3547#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3548#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3549#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3550#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3551#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3552
3553/* Bit definitions for LDO_PD_CTRL2 */
3554#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3555#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3556#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3557#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3558
3559/* Bit definitions for LDO_PD_CTRL3 */
3560#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3561#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3562
3563/* Bit definitions for LDO_SHORT_STATUS1 */
3564#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3565#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3566#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3567#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3568#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3569#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3570
3571/* Bit definitions for LDO_SHORT_STATUS2 */
3572#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3573#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3574#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3575#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3576
3577/* Bit definitions for LDO_SHORT_STATUS2 */
3578#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3579#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3580
3581/* Bit definitions for REGEN1_CTRL */
3582#define TPS65917_REGEN1_CTRL_STATUS 0x10
3583#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3584#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3585#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3586#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3587#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3588
3589/* Bit definitions for PLLEN_CTRL */
3590#define TPS65917_PLLEN_CTRL_STATUS 0x10
3591#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3592#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3593#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3594#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3595#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3596
3597/* Bit definitions for REGEN2_CTRL */
3598#define TPS65917_REGEN2_CTRL_STATUS 0x10
3599#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3600#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3601#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3602#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3603#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3604
3605/* Bit definitions for NSLEEP_RES_ASSIGN */
3606#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3607#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3608#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3609#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3610#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3611#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3612#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3613#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3614
3615/* Bit definitions for NSLEEP_SMPS_ASSIGN */
3616#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3617#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3618#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3619#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3620#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3621#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3622#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3623#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3624#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3625#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3626
3627/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3628#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3629#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3630#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3631#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3632#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3633#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3634
3635/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3636#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3637#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3638#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3639#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3640
3641/* Bit definitions for ENABLE1_RES_ASSIGN */
3642#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3643#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3644#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3645#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3646#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3647#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3648#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3649#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3650
3651/* Bit definitions for ENABLE1_SMPS_ASSIGN */
3652#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3653#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3654#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3655#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3656#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3657#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3658#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3659#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3660#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3661#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3662
3663/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3664#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3665#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3666#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3667#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3668#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3669#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3670
3671/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3672#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3673#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3674#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3675#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3676
3677/* Bit definitions for ENABLE2_RES_ASSIGN */
3678#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3679#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3680#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3681#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3682#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3683#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3684#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3685#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3686
3687/* Bit definitions for ENABLE2_SMPS_ASSIGN */
3688#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3689#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3690#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3691#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3692#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3693#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3694#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3695#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3696#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3697#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3698
3699/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3700#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3701#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3702#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3703#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3704#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3705#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3706
3707/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3708#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3709#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3710#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3711#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3712
3713/* Bit definitions for REGEN3_CTRL */
3714#define TPS65917_REGEN3_CTRL_STATUS 0x10
3715#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3716#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3717#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3718#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3719#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3720
3721/* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */
3722#define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0xC
3723
3724/* Registers for function RESOURCE */
3725#define TPS65917_REGEN1_CTRL 0x2
3726#define TPS65917_PLLEN_CTRL 0x3
3727#define TPS65917_NSLEEP_RES_ASSIGN 0x6
3728#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3729#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3730#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3731#define TPS65917_ENABLE1_RES_ASSIGN 0xA
3732#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3733#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3734#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3735#define TPS65917_ENABLE2_RES_ASSIGN 0xE
3736#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3737#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3738#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3739#define TPS65917_REGEN2_CTRL 0x12
3740#define TPS65917_REGEN3_CTRL 0x13
3741
3742static inline int palmas_read(struct palmas *palmas, unsigned int base,
3743 unsigned int reg, unsigned int *val)
3744{
3745 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3746 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3747
3748 return regmap_read(map: palmas->regmap[slave_id], reg: addr, val);
3749}
3750
3751static inline int palmas_write(struct palmas *palmas, unsigned int base,
3752 unsigned int reg, unsigned int value)
3753{
3754 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3755 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3756
3757 return regmap_write(map: palmas->regmap[slave_id], reg: addr, val: value);
3758}
3759
3760static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3761 unsigned int reg, const void *val, size_t val_count)
3762{
3763 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3764 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3765
3766 return regmap_bulk_write(map: palmas->regmap[slave_id], reg: addr,
3767 val, val_count);
3768}
3769
3770static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3771 unsigned int reg, void *val, size_t val_count)
3772{
3773 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3774 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3775
3776 return regmap_bulk_read(map: palmas->regmap[slave_id], reg: addr,
3777 val, val_count);
3778}
3779
3780static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3781 unsigned int reg, unsigned int mask, unsigned int val)
3782{
3783 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3784 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3785
3786 return regmap_update_bits(map: palmas->regmap[slave_id], reg: addr, mask, val);
3787}
3788
3789static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3790{
3791 return regmap_irq_get_virq(data: palmas->irq_data, irq);
3792}
3793
3794
3795int palmas_ext_control_req_config(struct palmas *palmas,
3796 enum palmas_external_requestor_id ext_control_req_id,
3797 int ext_ctrl, bool enable);
3798
3799#endif /* __LINUX_MFD_PALMAS_H */
3800

source code of linux/include/linux/mfd/palmas.h