| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (C) STMicroelectronics 2018 - All Rights Reserved |
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| 4 | * Author: Philippe Peurichard <philippe.peurichard@st.com>, |
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| 5 | * Pascal Paillet <p.paillet@st.com> for STMicroelectronics. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __LINUX_MFD_STPMIC1_H |
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| 9 | #define __LINUX_MFD_STPMIC1_H |
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| 10 | |
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| 11 | #define TURN_ON_SR 0x1 |
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| 12 | #define TURN_OFF_SR 0x2 |
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| 13 | #define ICC_LDO_TURN_OFF_SR 0x3 |
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| 14 | #define ICC_BUCK_TURN_OFF_SR 0x4 |
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| 15 | #define RREQ_STATE_SR 0x5 |
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| 16 | #define VERSION_SR 0x6 |
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| 17 | |
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| 18 | #define MAIN_CR 0x10 |
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| 19 | #define PADS_PULL_CR 0x11 |
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| 20 | #define BUCKS_PD_CR 0x12 |
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| 21 | #define LDO14_PD_CR 0x13 |
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| 22 | #define LDO56_VREF_PD_CR 0x14 |
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| 23 | #define VBUS_DET_VIN_CR 0x15 |
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| 24 | #define PKEY_TURNOFF_CR 0x16 |
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| 25 | #define BUCKS_MASK_RANK_CR 0x17 |
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| 26 | #define BUCKS_MASK_RESET_CR 0x18 |
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| 27 | #define LDOS_MASK_RANK_CR 0x19 |
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| 28 | #define LDOS_MASK_RESET_CR 0x1A |
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| 29 | #define WCHDG_CR 0x1B |
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| 30 | #define WCHDG_TIMER_CR 0x1C |
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| 31 | #define BUCKS_ICCTO_CR 0x1D |
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| 32 | #define LDOS_ICCTO_CR 0x1E |
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| 33 | |
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| 34 | #define BUCK1_ACTIVE_CR 0x20 |
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| 35 | #define BUCK2_ACTIVE_CR 0x21 |
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| 36 | #define BUCK3_ACTIVE_CR 0x22 |
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| 37 | #define BUCK4_ACTIVE_CR 0x23 |
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| 38 | #define VREF_DDR_ACTIVE_CR 0x24 |
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| 39 | #define LDO1_ACTIVE_CR 0x25 |
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| 40 | #define LDO2_ACTIVE_CR 0x26 |
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| 41 | #define LDO3_ACTIVE_CR 0x27 |
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| 42 | #define LDO4_ACTIVE_CR 0x28 |
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| 43 | #define LDO5_ACTIVE_CR 0x29 |
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| 44 | #define LDO6_ACTIVE_CR 0x2A |
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| 45 | |
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| 46 | #define BUCK1_STDBY_CR 0x30 |
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| 47 | #define BUCK2_STDBY_CR 0x31 |
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| 48 | #define BUCK3_STDBY_CR 0x32 |
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| 49 | #define BUCK4_STDBY_CR 0x33 |
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| 50 | #define VREF_DDR_STDBY_CR 0x34 |
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| 51 | #define LDO1_STDBY_CR 0x35 |
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| 52 | #define LDO2_STDBY_CR 0x36 |
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| 53 | #define LDO3_STDBY_CR 0x37 |
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| 54 | #define LDO4_STDBY_CR 0x38 |
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| 55 | #define LDO5_STDBY_CR 0x39 |
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| 56 | #define LDO6_STDBY_CR 0x3A |
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| 57 | |
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| 58 | #define BST_SW_CR 0x40 |
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| 59 | |
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| 60 | #define INT_PENDING_R1 0x50 |
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| 61 | #define INT_PENDING_R2 0x51 |
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| 62 | #define INT_PENDING_R3 0x52 |
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| 63 | #define INT_PENDING_R4 0x53 |
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| 64 | |
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| 65 | #define INT_DBG_LATCH_R1 0x60 |
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| 66 | #define INT_DBG_LATCH_R2 0x61 |
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| 67 | #define INT_DBG_LATCH_R3 0x62 |
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| 68 | #define INT_DBG_LATCH_R4 0x63 |
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| 69 | |
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| 70 | #define INT_CLEAR_R1 0x70 |
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| 71 | #define INT_CLEAR_R2 0x71 |
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| 72 | #define INT_CLEAR_R3 0x72 |
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| 73 | #define INT_CLEAR_R4 0x73 |
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| 74 | |
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| 75 | #define INT_MASK_R1 0x80 |
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| 76 | #define INT_MASK_R2 0x81 |
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| 77 | #define INT_MASK_R3 0x82 |
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| 78 | #define INT_MASK_R4 0x83 |
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| 79 | |
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| 80 | #define INT_SET_MASK_R1 0x90 |
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| 81 | #define INT_SET_MASK_R2 0x91 |
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| 82 | #define INT_SET_MASK_R3 0x92 |
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| 83 | #define INT_SET_MASK_R4 0x93 |
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| 84 | |
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| 85 | #define INT_CLEAR_MASK_R1 0xA0 |
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| 86 | #define INT_CLEAR_MASK_R2 0xA1 |
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| 87 | #define INT_CLEAR_MASK_R3 0xA2 |
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| 88 | #define INT_CLEAR_MASK_R4 0xA3 |
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| 89 | |
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| 90 | #define INT_SRC_R1 0xB0 |
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| 91 | #define INT_SRC_R2 0xB1 |
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| 92 | #define INT_SRC_R3 0xB2 |
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| 93 | #define INT_SRC_R4 0xB3 |
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| 94 | |
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| 95 | #define PMIC_MAX_REGISTER_ADDRESS INT_SRC_R4 |
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| 96 | |
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| 97 | #define STPMIC1_PMIC_NUM_IRQ_REGS 4 |
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| 98 | |
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| 99 | #define TURN_OFF_SR_ICC_EVENT 0x08 |
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| 100 | |
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| 101 | #define LDO_VOLTAGE_MASK GENMASK(6, 2) |
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| 102 | #define BUCK_VOLTAGE_MASK GENMASK(7, 2) |
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| 103 | #define LDO_BUCK_VOLTAGE_SHIFT 2 |
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| 104 | |
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| 105 | #define LDO_ENABLE_MASK BIT(0) |
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| 106 | #define BUCK_ENABLE_MASK BIT(0) |
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| 107 | |
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| 108 | #define BUCK_HPLP_ENABLE_MASK BIT(1) |
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| 109 | #define BUCK_HPLP_SHIFT 1 |
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| 110 | |
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| 111 | #define STDBY_ENABLE_MASK BIT(0) |
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| 112 | |
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| 113 | #define BUCKS_PD_CR_REG_MASK GENMASK(7, 0) |
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| 114 | #define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0) |
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| 115 | #define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0) |
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| 116 | #define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0) |
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| 117 | #define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0) |
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| 118 | #define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0) |
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| 119 | #define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0) |
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| 120 | |
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| 121 | #define BUCK1_PULL_DOWN_REG BUCKS_PD_CR |
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| 122 | #define BUCK1_PULL_DOWN_MASK BIT(0) |
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| 123 | #define BUCK2_PULL_DOWN_REG BUCKS_PD_CR |
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| 124 | #define BUCK2_PULL_DOWN_MASK BIT(2) |
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| 125 | #define BUCK3_PULL_DOWN_REG BUCKS_PD_CR |
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| 126 | #define BUCK3_PULL_DOWN_MASK BIT(4) |
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| 127 | #define BUCK4_PULL_DOWN_REG BUCKS_PD_CR |
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| 128 | #define BUCK4_PULL_DOWN_MASK BIT(6) |
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| 129 | |
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| 130 | #define LDO1_PULL_DOWN_REG LDO14_PD_CR |
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| 131 | #define LDO1_PULL_DOWN_MASK BIT(0) |
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| 132 | #define LDO2_PULL_DOWN_REG LDO14_PD_CR |
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| 133 | #define LDO2_PULL_DOWN_MASK BIT(2) |
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| 134 | #define LDO3_PULL_DOWN_REG LDO14_PD_CR |
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| 135 | #define LDO3_PULL_DOWN_MASK BIT(4) |
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| 136 | #define LDO4_PULL_DOWN_REG LDO14_PD_CR |
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| 137 | #define LDO4_PULL_DOWN_MASK BIT(6) |
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| 138 | #define LDO5_PULL_DOWN_REG LDO56_VREF_PD_CR |
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| 139 | #define LDO5_PULL_DOWN_MASK BIT(0) |
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| 140 | #define LDO6_PULL_DOWN_REG LDO56_VREF_PD_CR |
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| 141 | #define LDO6_PULL_DOWN_MASK BIT(2) |
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| 142 | #define VREF_DDR_PULL_DOWN_REG LDO56_VREF_PD_CR |
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| 143 | #define VREF_DDR_PULL_DOWN_MASK BIT(4) |
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| 144 | |
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| 145 | #define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0) |
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| 146 | #define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0) |
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| 147 | |
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| 148 | #define LDO_BYPASS_MASK BIT(7) |
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| 149 | |
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| 150 | /* Main PMIC Control Register |
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| 151 | * MAIN_CR |
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| 152 | * Address : 0x10 |
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| 153 | */ |
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| 154 | #define OCP_OFF_DBG BIT(4) |
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| 155 | #define PWRCTRL_POLARITY_HIGH BIT(3) |
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| 156 | #define PWRCTRL_ENABLE BIT(2) |
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| 157 | #define RESTART_REQUEST_ENABLE BIT(1) |
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| 158 | #define SOFTWARE_SWITCH_OFF BIT(0) |
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| 159 | |
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| 160 | /* Main PMIC PADS Control Register |
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| 161 | * PADS_PULL_CR |
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| 162 | * Address : 0x11 |
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| 163 | */ |
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| 164 | #define WAKEUP_DETECTOR_DISABLED BIT(4) |
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| 165 | #define PWRCTRL_PD_ACTIVE BIT(3) |
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| 166 | #define PWRCTRL_PU_ACTIVE BIT(2) |
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| 167 | #define WAKEUP_PD_ACTIVE BIT(1) |
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| 168 | #define PONKEY_PU_INACTIVE BIT(0) |
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| 169 | |
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| 170 | /* Main PMIC VINLOW Control Register |
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| 171 | * VBUS_DET_VIN_CRC DMSC |
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| 172 | * Address : 0x15 |
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| 173 | */ |
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| 174 | #define SWIN_DETECTOR_ENABLED BIT(7) |
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| 175 | #define SWOUT_DETECTOR_ENABLED BIT(6) |
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| 176 | #define VINLOW_ENABLED BIT(0) |
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| 177 | #define VINLOW_CTRL_REG_MASK GENMASK(7, 0) |
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| 178 | |
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| 179 | /* USB Control Register |
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| 180 | * Address : 0x40 |
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| 181 | */ |
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| 182 | #define BOOST_OVP_DISABLED BIT(7) |
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| 183 | #define VBUS_OTG_DETECTION_DISABLED BIT(6) |
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| 184 | #define SW_OUT_DISCHARGE BIT(5) |
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| 185 | #define VBUS_OTG_DISCHARGE BIT(4) |
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| 186 | #define OCP_LIMIT_HIGH BIT(3) |
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| 187 | #define SWIN_SWOUT_ENABLED BIT(2) |
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| 188 | #define USBSW_OTG_SWITCH_ENABLED BIT(1) |
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| 189 | #define BOOST_ENABLED BIT(0) |
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| 190 | |
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| 191 | /* PKEY_TURNOFF_CR |
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| 192 | * Address : 0x16 |
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| 193 | */ |
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| 194 | #define PONKEY_PWR_OFF BIT(7) |
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| 195 | #define PONKEY_CC_FLAG_CLEAR BIT(6) |
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| 196 | #define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0) |
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| 197 | #define PONKEY_TURNOFF_MASK GENMASK(7, 0) |
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| 198 | |
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| 199 | /* |
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| 200 | * struct stpmic1 - stpmic1 master device for sub-drivers |
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| 201 | * @dev: master device of the chip (can be used to access platform data) |
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| 202 | * @irq: main IRQ number |
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| 203 | * @regmap_irq_chip_data: irq chip data |
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| 204 | */ |
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| 205 | struct stpmic1 { |
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| 206 | struct device *dev; |
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| 207 | struct regmap *regmap; |
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| 208 | int irq; |
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| 209 | struct regmap_irq_chip_data *irq_data; |
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| 210 | }; |
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| 211 | |
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| 212 | #endif /* __LINUX_MFD_STPMIC1_H */ |
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| 213 | |
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