| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __LINUX_IMX6Q_IOMUXC_GPR_H |
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| 7 | #define __LINUX_IMX6Q_IOMUXC_GPR_H |
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| 8 | |
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| 9 | #include <linux/bitops.h> |
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| 10 | |
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| 11 | #define IOMUXC_GPR0 0x00 |
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| 12 | #define IOMUXC_GPR1 0x04 |
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| 13 | #define IOMUXC_GPR2 0x08 |
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| 14 | #define IOMUXC_GPR3 0x0c |
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| 15 | #define IOMUXC_GPR4 0x10 |
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| 16 | #define IOMUXC_GPR5 0x14 |
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| 17 | #define IOMUXC_GPR6 0x18 |
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| 18 | #define IOMUXC_GPR7 0x1c |
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| 19 | #define IOMUXC_GPR8 0x20 |
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| 20 | #define IOMUXC_GPR9 0x24 |
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| 21 | #define IOMUXC_GPR10 0x28 |
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| 22 | #define IOMUXC_GPR11 0x2c |
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| 23 | #define IOMUXC_GPR12 0x30 |
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| 24 | #define IOMUXC_GPR13 0x34 |
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| 25 | |
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| 26 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30) |
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| 27 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30) |
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| 28 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30) |
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| 29 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30) |
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| 30 | #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30) |
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| 31 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28) |
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| 32 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28) |
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| 33 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28) |
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| 34 | #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28) |
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| 35 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26) |
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| 36 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26) |
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| 37 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26) |
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| 38 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26) |
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| 39 | #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26) |
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| 40 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24) |
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| 41 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24) |
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| 42 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24) |
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| 43 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24) |
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| 44 | #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24) |
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| 45 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22) |
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| 46 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22) |
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| 47 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22) |
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| 48 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22) |
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| 49 | #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22) |
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| 50 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20) |
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| 51 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20) |
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| 52 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20) |
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| 53 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20) |
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| 54 | #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20) |
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| 55 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18) |
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| 56 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18) |
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| 57 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18) |
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| 58 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18) |
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| 59 | #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18) |
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| 60 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16) |
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| 61 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16) |
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| 62 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16) |
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| 63 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16) |
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| 64 | #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16) |
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| 65 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14) |
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| 66 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14) |
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| 67 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14) |
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| 68 | #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14) |
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| 69 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7) |
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| 70 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0 |
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| 71 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7) |
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| 72 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6) |
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| 73 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0 |
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| 74 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6) |
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| 75 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5) |
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| 76 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0 |
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| 77 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5) |
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| 78 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4) |
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| 79 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0 |
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| 80 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4) |
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| 81 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3) |
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| 82 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0 |
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| 83 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3) |
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| 84 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2) |
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| 85 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0 |
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| 86 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2) |
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| 87 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1) |
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| 88 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0 |
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| 89 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1) |
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| 90 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0) |
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| 91 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0 |
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| 92 | #define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0) |
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| 93 | |
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| 94 | #define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30) |
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| 95 | #define IMX6Q_GPR1_PCIE_SW_RST BIT(29) |
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| 96 | #define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28) |
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| 97 | #define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27) |
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| 98 | #define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26) |
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| 99 | #define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25) |
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| 100 | #define IMX6Q_GPR1_DPI_OFF BIT(24) |
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| 101 | #define IMX6Q_GPR1_EXC_MON_MASK BIT(22) |
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| 102 | #define IMX6Q_GPR1_EXC_MON_OKAY 0x0 |
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| 103 | #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22) |
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| 104 | #define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21) |
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| 105 | #define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0 |
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| 106 | #define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21) |
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| 107 | #define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20) |
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| 108 | #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0 |
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| 109 | #define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) |
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| 110 | #define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19) |
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| 111 | #define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0 |
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| 112 | #define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) |
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| 113 | #define IMX6Q_GPR1_PCIE_TEST_PD BIT(18) |
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| 114 | #define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17) |
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| 115 | #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0 |
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| 116 | #define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17) |
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| 117 | #define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16) |
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| 118 | #define IMX6Q_GPR1_USB_EXP_MODE BIT(15) |
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| 119 | #define IMX6Q_GPR1_PCIE_INT BIT(14) |
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| 120 | #define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13) |
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| 121 | #define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0 |
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| 122 | #define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13) |
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| 123 | #define IMX6Q_GPR1_GINT BIT(12) |
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| 124 | #define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10) |
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| 125 | #define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10) |
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| 126 | #define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10) |
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| 127 | #define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10) |
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| 128 | #define IMX6Q_GPR1_ACT_CS3 BIT(9) |
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| 129 | #define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7) |
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| 130 | #define IMX6Q_GPR1_ACT_CS2 BIT(6) |
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| 131 | #define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4) |
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| 132 | #define IMX6Q_GPR1_ACT_CS1 BIT(3) |
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| 133 | #define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1) |
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| 134 | #define IMX6Q_GPR1_ACT_CS0 BIT(0) |
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| 135 | |
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| 136 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20) |
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| 137 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20) |
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| 138 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20) |
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| 139 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20) |
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| 140 | #define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20) |
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| 141 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16) |
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| 142 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16) |
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| 143 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16) |
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| 144 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16) |
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| 145 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16) |
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| 146 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16) |
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| 147 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16) |
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| 148 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16) |
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| 149 | #define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16) |
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| 150 | #define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15) |
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| 151 | #define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0 |
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| 152 | #define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15) |
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| 153 | #define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10) |
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| 154 | #define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0 |
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| 155 | #define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10) |
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| 156 | #define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9) |
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| 157 | #define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0 |
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| 158 | #define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9) |
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| 159 | #define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8) |
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| 160 | #define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0 |
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| 161 | #define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8) |
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| 162 | #define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7) |
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| 163 | #define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0 |
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| 164 | #define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7) |
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| 165 | #define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6) |
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| 166 | #define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0 |
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| 167 | #define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6) |
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| 168 | #define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5) |
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| 169 | #define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0 |
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| 170 | #define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5) |
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| 171 | #define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4) |
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| 172 | #define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2) |
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| 173 | #define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2) |
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| 174 | #define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2) |
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| 175 | #define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2) |
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| 176 | #define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0) |
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| 177 | #define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0) |
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| 178 | #define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0) |
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| 179 | #define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0) |
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| 180 | |
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| 181 | #define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29) |
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| 182 | #define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29) |
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| 183 | #define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29) |
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| 184 | #define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29) |
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| 185 | #define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28) |
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| 186 | #define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27) |
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| 187 | #define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26) |
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| 188 | #define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25) |
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| 189 | #define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21) |
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| 190 | #define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17) |
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| 191 | #define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16) |
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| 192 | #define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15) |
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| 193 | #define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14) |
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| 194 | #define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13) |
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| 195 | #define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12) |
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| 196 | #define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11) |
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| 197 | #define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10) |
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| 198 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) |
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| 199 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) |
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| 200 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8) |
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| 201 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8) |
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| 202 | #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8) |
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| 203 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6) |
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| 204 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6) |
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| 205 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) |
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| 206 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6) |
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| 207 | #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6) |
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| 208 | #define IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT 4 |
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| 209 | #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4) |
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| 210 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4) |
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| 211 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4) |
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| 212 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4) |
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| 213 | #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4) |
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| 214 | #define IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT 2 |
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| 215 | #define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2) |
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| 216 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2) |
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| 217 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2) |
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| 218 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2) |
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| 219 | #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2) |
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| 220 | |
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| 221 | #define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31) |
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| 222 | #define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30) |
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| 223 | #define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29) |
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| 224 | #define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28) |
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| 225 | #define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27) |
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| 226 | #define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26) |
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| 227 | #define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25) |
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| 228 | #define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24) |
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| 229 | #define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19) |
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| 230 | #define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18) |
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| 231 | #define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17) |
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| 232 | #define IMX6Q_GPR4_ENET_STOP_ACK BIT(16) |
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| 233 | #define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8) |
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| 234 | #define IMX6Q_GPR4_SOC_VERSION_OFF 0x8 |
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| 235 | #define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7) |
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| 236 | #define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6) |
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| 237 | #define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3) |
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| 238 | #define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2) |
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| 239 | #define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1) |
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| 240 | #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) |
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| 241 | |
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| 242 | #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) |
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| 243 | #define IMX6Q_GPR5_SATA_SW_PD BIT(10) |
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| 244 | #define IMX6Q_GPR5_SATA_SW_RST BIT(11) |
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| 245 | |
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| 246 | #define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) |
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| 247 | #define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) |
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| 248 | #define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK (0xf << 8) |
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| 249 | #define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK (0xf << 12) |
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| 250 | #define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK (0xf << 16) |
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| 251 | #define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK (0xf << 20) |
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| 252 | #define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24) |
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| 253 | #define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK (0xf << 28) |
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| 254 | |
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| 255 | #define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK (0xf << 0) |
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| 256 | #define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK (0xf << 4) |
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| 257 | #define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK (0xf << 8) |
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| 258 | #define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK (0xf << 12) |
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| 259 | #define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK (0xf << 16) |
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| 260 | #define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK (0xf << 20) |
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| 261 | #define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24) |
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| 262 | #define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28) |
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| 263 | |
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| 264 | #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) |
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| 265 | #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) |
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| 266 | #define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) |
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| 267 | #define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) |
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| 268 | #define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) |
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| 269 | |
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| 270 | #define IMX6Q_GPR9_TZASC2_BYP BIT(1) |
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| 271 | #define IMX6Q_GPR9_TZASC1_BYP BIT(0) |
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| 272 | |
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| 273 | #define IMX6Q_GPR10_LOCK_DBG_EN BIT(29) |
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| 274 | #define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28) |
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| 275 | #define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27) |
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| 276 | #define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21) |
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| 277 | #define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20) |
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| 278 | #define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18) |
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| 279 | #define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16) |
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| 280 | #define IMX6Q_GPR10_DBG_EN BIT(13) |
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| 281 | #define IMX6Q_GPR10_DBG_CLK_EN BIT(12) |
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| 282 | #define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11) |
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| 283 | #define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0 |
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| 284 | #define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11) |
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| 285 | #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) |
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| 286 | #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) |
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| 287 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) |
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| 288 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2) |
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| 289 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2) |
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| 290 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2) |
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| 291 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2) |
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| 292 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) |
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| 293 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) |
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| 294 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0) |
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| 295 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0) |
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| 296 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0) |
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| 297 | |
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| 298 | #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) |
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| 299 | #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) |
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| 300 | #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) |
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| 301 | #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) |
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| 302 | #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) |
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| 303 | #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) |
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| 304 | #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) |
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| 305 | |
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| 306 | #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) |
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| 307 | #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) |
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| 308 | #define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28) |
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| 309 | #define IMX6Q_GPR13_ENET_STOP_REQ BIT(27) |
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| 310 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24) |
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| 311 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24) |
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| 312 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24) |
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| 313 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24) |
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| 314 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24) |
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| 315 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24) |
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| 316 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24) |
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| 317 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24) |
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| 318 | #define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24) |
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| 319 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19) |
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| 320 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19) |
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| 321 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19) |
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| 322 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19) |
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| 323 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19) |
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| 324 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19) |
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| 325 | #define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19) |
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| 326 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK (0x7 << 16) |
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| 327 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F (0x0 << 16) |
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| 328 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F (0x1 << 16) |
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| 329 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16) |
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| 330 | #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F (0x3 << 16) |
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| 331 | #define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15) |
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| 332 | #define IMX6Q_GPR13_SATA_SPD_MODE_1P5G 0x0 |
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| 333 | #define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15) |
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| 334 | #define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14) |
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| 335 | #define IMX6Q_GPR13_SATA_TX_ATTEN_MASK (0x7 << 11) |
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| 336 | #define IMX6Q_GPR13_SATA_TX_ATTEN_16_16 (0x0 << 11) |
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| 337 | #define IMX6Q_GPR13_SATA_TX_ATTEN_14_16 (0x1 << 11) |
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| 338 | #define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11) |
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| 339 | #define IMX6Q_GPR13_SATA_TX_ATTEN_10_16 (0x3 << 11) |
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| 340 | #define IMX6Q_GPR13_SATA_TX_ATTEN_9_16 (0x4 << 11) |
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| 341 | #define IMX6Q_GPR13_SATA_TX_ATTEN_8_16 (0x5 << 11) |
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| 342 | #define IMX6Q_GPR13_SATA_TX_BOOST_MASK (0xf << 7) |
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| 343 | #define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB (0x0 << 7) |
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| 344 | #define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB (0x1 << 7) |
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| 345 | #define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7) |
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| 346 | #define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB (0x3 << 7) |
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| 347 | #define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB (0x4 << 7) |
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| 348 | #define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB (0x5 << 7) |
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| 349 | #define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB (0x6 << 7) |
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| 350 | #define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB (0x7 << 7) |
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| 351 | #define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB (0x8 << 7) |
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| 352 | #define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB (0x9 << 7) |
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| 353 | #define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB (0xa << 7) |
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| 354 | #define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB (0xb << 7) |
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| 355 | #define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB (0xc << 7) |
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| 356 | #define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB (0xd << 7) |
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| 357 | #define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB (0xe << 7) |
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| 358 | #define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB (0xf << 7) |
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| 359 | #define IMX6Q_GPR13_SATA_TX_LVL_MASK (0x1f << 2) |
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| 360 | #define IMX6Q_GPR13_SATA_TX_LVL_0_937_V (0x00 << 2) |
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| 361 | #define IMX6Q_GPR13_SATA_TX_LVL_0_947_V (0x01 << 2) |
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| 362 | #define IMX6Q_GPR13_SATA_TX_LVL_0_957_V (0x02 << 2) |
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| 363 | #define IMX6Q_GPR13_SATA_TX_LVL_0_966_V (0x03 << 2) |
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| 364 | #define IMX6Q_GPR13_SATA_TX_LVL_0_976_V (0x04 << 2) |
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| 365 | #define IMX6Q_GPR13_SATA_TX_LVL_0_986_V (0x05 << 2) |
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| 366 | #define IMX6Q_GPR13_SATA_TX_LVL_0_996_V (0x06 << 2) |
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| 367 | #define IMX6Q_GPR13_SATA_TX_LVL_1_005_V (0x07 << 2) |
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| 368 | #define IMX6Q_GPR13_SATA_TX_LVL_1_015_V (0x08 << 2) |
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| 369 | #define IMX6Q_GPR13_SATA_TX_LVL_1_025_V (0x09 << 2) |
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| 370 | #define IMX6Q_GPR13_SATA_TX_LVL_1_035_V (0x0a << 2) |
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| 371 | #define IMX6Q_GPR13_SATA_TX_LVL_1_045_V (0x0b << 2) |
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| 372 | #define IMX6Q_GPR13_SATA_TX_LVL_1_054_V (0x0c << 2) |
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| 373 | #define IMX6Q_GPR13_SATA_TX_LVL_1_064_V (0x0d << 2) |
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| 374 | #define IMX6Q_GPR13_SATA_TX_LVL_1_074_V (0x0e << 2) |
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| 375 | #define IMX6Q_GPR13_SATA_TX_LVL_1_084_V (0x0f << 2) |
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| 376 | #define IMX6Q_GPR13_SATA_TX_LVL_1_094_V (0x10 << 2) |
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| 377 | #define IMX6Q_GPR13_SATA_TX_LVL_1_104_V (0x11 << 2) |
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| 378 | #define IMX6Q_GPR13_SATA_TX_LVL_1_113_V (0x12 << 2) |
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| 379 | #define IMX6Q_GPR13_SATA_TX_LVL_1_123_V (0x13 << 2) |
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| 380 | #define IMX6Q_GPR13_SATA_TX_LVL_1_133_V (0x14 << 2) |
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| 381 | #define IMX6Q_GPR13_SATA_TX_LVL_1_143_V (0x15 << 2) |
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| 382 | #define IMX6Q_GPR13_SATA_TX_LVL_1_152_V (0x16 << 2) |
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| 383 | #define IMX6Q_GPR13_SATA_TX_LVL_1_162_V (0x17 << 2) |
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| 384 | #define IMX6Q_GPR13_SATA_TX_LVL_1_172_V (0x18 << 2) |
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| 385 | #define IMX6Q_GPR13_SATA_TX_LVL_1_182_V (0x19 << 2) |
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| 386 | #define IMX6Q_GPR13_SATA_TX_LVL_1_191_V (0x1a << 2) |
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| 387 | #define IMX6Q_GPR13_SATA_TX_LVL_1_201_V (0x1b << 2) |
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| 388 | #define IMX6Q_GPR13_SATA_TX_LVL_1_211_V (0x1c << 2) |
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| 389 | #define IMX6Q_GPR13_SATA_TX_LVL_1_221_V (0x1d << 2) |
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| 390 | #define IMX6Q_GPR13_SATA_TX_LVL_1_230_V (0x1e << 2) |
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| 391 | #define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2) |
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| 392 | #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1) |
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| 393 | #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0) |
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| 394 | |
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| 395 | /* For imx6sl iomux gpr register field define */ |
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| 396 | #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) |
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| 397 | #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) |
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| 398 | |
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| 399 | /* For imx6sx iomux gpr register field define */ |
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| 400 | #define IMX6SX_GPR1_VDEC_SW_RST_MASK (0x1 << 20) |
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| 401 | #define IMX6SX_GPR1_VDEC_SW_RST_RESET (0x1 << 20) |
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| 402 | #define IMX6SX_GPR1_VDEC_SW_RST_RELEASE (0x0 << 20) |
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| 403 | #define IMX6SX_GPR1_VADC_SW_RST_MASK (0x1 << 19) |
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| 404 | #define IMX6SX_GPR1_VADC_SW_RST_RESET (0x1 << 19) |
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| 405 | #define IMX6SX_GPR1_VADC_SW_RST_RELEASE (0x0 << 19) |
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| 406 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK (0x3 << 13) |
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| 407 | #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17) |
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| 408 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13) |
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| 409 | |
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| 410 | #define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK (0x1 << 26) |
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| 411 | #define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT (26) |
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| 412 | #define IMX6SX_GPR2_MQS_EN_MASK (0x1 << 25) |
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| 413 | #define IMX6SX_GPR2_MQS_EN_SHIFT (25) |
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| 414 | #define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24) |
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| 415 | #define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24) |
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| 416 | #define IMX6SX_GPR2_MQS_CLK_DIV_MASK (0xFF << 16) |
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| 417 | #define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT (16) |
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| 418 | |
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| 419 | #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3) |
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| 420 | #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4) |
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| 421 | |
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| 422 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) |
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| 423 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) |
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| 424 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) |
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| 425 | |
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| 426 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK (0x3 << 27) |
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| 427 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN (0x0 << 27) |
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| 428 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD (0x1 << 27) |
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| 429 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI (0x2 << 27) |
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| 430 | #define IMX6SX_GPR5_CSI2_MUX_CTRL_GND (0x3 << 27) |
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| 431 | #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26) |
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| 432 | #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26) |
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| 433 | #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26) |
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| 434 | #define IMX6SX_GPR5_PCIE_BTNRST_RESET BIT(19) |
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| 435 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4) |
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| 436 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4) |
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| 437 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4) |
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| 438 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4) |
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| 439 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4) |
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| 440 | |
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| 441 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2 (0x0 << 2) |
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| 442 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS (0x1 << 2) |
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| 443 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK (0x1 << 2) |
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| 444 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1 (0x0 << 1) |
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| 445 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) |
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| 446 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) |
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| 447 | |
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| 448 | #define IMX6SX_GPR12_PCIE_TEST_POWERDOWN BIT(30) |
|---|
| 449 | #define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16) |
|---|
| 450 | #define IMX6SX_GPR12_PCIE_RX_EQ_MASK (0x7 << 0) |
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| 451 | #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) |
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| 452 | |
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| 453 | /* For imx6ul iomux gpr register field define */ |
|---|
| 454 | #define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) |
|---|
| 455 | #define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) |
|---|
| 456 | #define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) |
|---|
| 457 | #define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) |
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| 458 | #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) |
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| 459 | #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) |
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| 460 | #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) |
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| 461 | #define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17) |
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| 462 | #define IMX6UL_GPR1_SAI1_MCLK_DIR (0x1 << 19) |
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| 463 | #define IMX6UL_GPR1_SAI2_MCLK_DIR (0x1 << 20) |
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| 464 | #define IMX6UL_GPR1_SAI3_MCLK_DIR (0x1 << 21) |
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| 465 | #define IMX6UL_GPR1_SAI_MCLK_MASK (0x7 << 19) |
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| 466 | #define MCLK_DIR(x) (x == 1 ? IMX6UL_GPR1_SAI1_MCLK_DIR : x == 2 ? \ |
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| 467 | IMX6UL_GPR1_SAI2_MCLK_DIR : IMX6UL_GPR1_SAI3_MCLK_DIR) |
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| 468 | |
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| 469 | /* For imx6sll iomux gpr register field define */ |
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| 470 | #define IMX6SLL_GPR5_AFCG_X_BYPASS_MASK (0x1f << 11) |
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| 471 | |
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| 472 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ |
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| 473 | |
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