1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * linux/mfd/tps65218.h |
4 | * |
5 | * Functions to access TPS65218 power management chip. |
6 | * |
7 | * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ |
8 | */ |
9 | |
10 | #ifndef __LINUX_MFD_TPS65218_H |
11 | #define __LINUX_MFD_TPS65218_H |
12 | |
13 | #include <linux/i2c.h> |
14 | #include <linux/regulator/driver.h> |
15 | #include <linux/regulator/machine.h> |
16 | #include <linux/bitops.h> |
17 | |
18 | /* TPS chip id list */ |
19 | #define TPS65218 0xF0 |
20 | |
21 | /* I2C ID for TPS65218 part */ |
22 | #define TPS65218_I2C_ID 0x24 |
23 | |
24 | /* All register addresses */ |
25 | #define TPS65218_REG_CHIPID 0x00 |
26 | #define TPS65218_REG_INT1 0x01 |
27 | #define TPS65218_REG_INT2 0x02 |
28 | #define TPS65218_REG_INT_MASK1 0x03 |
29 | #define TPS65218_REG_INT_MASK2 0x04 |
30 | #define TPS65218_REG_STATUS 0x05 |
31 | #define TPS65218_REG_CONTROL 0x06 |
32 | #define TPS65218_REG_FLAG 0x07 |
33 | |
34 | #define TPS65218_REG_PASSWORD 0x10 |
35 | #define TPS65218_REG_ENABLE1 0x11 |
36 | #define TPS65218_REG_ENABLE2 0x12 |
37 | #define TPS65218_REG_CONFIG1 0x13 |
38 | #define TPS65218_REG_CONFIG2 0x14 |
39 | #define TPS65218_REG_CONFIG3 0x15 |
40 | #define TPS65218_REG_CONTROL_DCDC1 0x16 |
41 | #define TPS65218_REG_CONTROL_DCDC2 0x17 |
42 | #define TPS65218_REG_CONTROL_DCDC3 0x18 |
43 | #define TPS65218_REG_CONTROL_DCDC4 0x19 |
44 | #define TPS65218_REG_CONTRL_SLEW_RATE 0x1A |
45 | #define TPS65218_REG_CONTROL_LDO1 0x1B |
46 | #define TPS65218_REG_SEQ1 0x20 |
47 | #define TPS65218_REG_SEQ2 0x21 |
48 | #define TPS65218_REG_SEQ3 0x22 |
49 | #define TPS65218_REG_SEQ4 0x23 |
50 | #define TPS65218_REG_SEQ5 0x24 |
51 | #define TPS65218_REG_SEQ6 0x25 |
52 | #define TPS65218_REG_SEQ7 0x26 |
53 | |
54 | /* Register field definitions */ |
55 | #define TPS65218_CHIPID_CHIP_MASK 0xF8 |
56 | #define TPS65218_CHIPID_REV_MASK 0x07 |
57 | |
58 | #define TPS65218_REV_1_0 0x0 |
59 | #define TPS65218_REV_1_1 0x1 |
60 | #define TPS65218_REV_2_0 0x2 |
61 | #define TPS65218_REV_2_1 0x3 |
62 | |
63 | #define TPS65218_INT1_VPRG BIT(5) |
64 | #define TPS65218_INT1_AC BIT(4) |
65 | #define TPS65218_INT1_PB BIT(3) |
66 | #define TPS65218_INT1_HOT BIT(2) |
67 | #define TPS65218_INT1_CC_AQC BIT(1) |
68 | #define TPS65218_INT1_PRGC BIT(0) |
69 | |
70 | #define TPS65218_INT2_LS3_F BIT(5) |
71 | #define TPS65218_INT2_LS2_F BIT(4) |
72 | #define TPS65218_INT2_LS1_F BIT(3) |
73 | #define TPS65218_INT2_LS3_I BIT(2) |
74 | #define TPS65218_INT2_LS2_I BIT(1) |
75 | #define TPS65218_INT2_LS1_I BIT(0) |
76 | |
77 | #define TPS65218_INT_MASK1_VPRG BIT(5) |
78 | #define TPS65218_INT_MASK1_AC BIT(4) |
79 | #define TPS65218_INT_MASK1_PB BIT(3) |
80 | #define TPS65218_INT_MASK1_HOT BIT(2) |
81 | #define TPS65218_INT_MASK1_CC_AQC BIT(1) |
82 | #define TPS65218_INT_MASK1_PRGC BIT(0) |
83 | |
84 | #define TPS65218_INT_MASK2_LS3_F BIT(5) |
85 | #define TPS65218_INT_MASK2_LS2_F BIT(4) |
86 | #define TPS65218_INT_MASK2_LS1_F BIT(3) |
87 | #define TPS65218_INT_MASK2_LS3_I BIT(2) |
88 | #define TPS65218_INT_MASK2_LS2_I BIT(1) |
89 | #define TPS65218_INT_MASK2_LS1_I BIT(0) |
90 | |
91 | #define TPS65218_STATUS_FSEAL BIT(7) |
92 | #define TPS65218_STATUS_EE BIT(6) |
93 | #define TPS65218_STATUS_AC_STATE BIT(5) |
94 | #define TPS65218_STATUS_PB_STATE BIT(4) |
95 | #define TPS65218_STATUS_STATE_MASK 0xC |
96 | #define TPS65218_STATUS_CC_STAT 0x3 |
97 | |
98 | #define TPS65218_CONTROL_OFFNPFO BIT(1) |
99 | #define TPS65218_CONTROL_CC_AQ BIT(0) |
100 | |
101 | #define TPS65218_FLAG_GPO3_FLG BIT(7) |
102 | #define TPS65218_FLAG_GPO2_FLG BIT(6) |
103 | #define TPS65218_FLAG_GPO1_FLG BIT(5) |
104 | #define TPS65218_FLAG_LDO1_FLG BIT(4) |
105 | #define TPS65218_FLAG_DC4_FLG BIT(3) |
106 | #define TPS65218_FLAG_DC3_FLG BIT(2) |
107 | #define TPS65218_FLAG_DC2_FLG BIT(1) |
108 | #define TPS65218_FLAG_DC1_FLG BIT(0) |
109 | |
110 | #define TPS65218_ENABLE1_DC6_EN BIT(5) |
111 | #define TPS65218_ENABLE1_DC5_EN BIT(4) |
112 | #define TPS65218_ENABLE1_DC4_EN BIT(3) |
113 | #define TPS65218_ENABLE1_DC3_EN BIT(2) |
114 | #define TPS65218_ENABLE1_DC2_EN BIT(1) |
115 | #define TPS65218_ENABLE1_DC1_EN BIT(0) |
116 | |
117 | #define TPS65218_ENABLE2_GPIO3 BIT(6) |
118 | #define TPS65218_ENABLE2_GPIO2 BIT(5) |
119 | #define TPS65218_ENABLE2_GPIO1 BIT(4) |
120 | #define TPS65218_ENABLE2_LS3_EN BIT(3) |
121 | #define TPS65218_ENABLE2_LS2_EN BIT(2) |
122 | #define TPS65218_ENABLE2_LS1_EN BIT(1) |
123 | #define TPS65218_ENABLE2_LDO1_EN BIT(0) |
124 | |
125 | |
126 | #define TPS65218_CONFIG1_TRST BIT(7) |
127 | #define TPS65218_CONFIG1_GPO2_BUF BIT(6) |
128 | #define TPS65218_CONFIG1_IO1_SEL BIT(5) |
129 | #define TPS65218_CONFIG1_PGDLY_MASK 0x18 |
130 | #define TPS65218_CONFIG1_STRICT BIT(2) |
131 | #define TPS65218_CONFIG1_UVLO_MASK 0x3 |
132 | #define TPS65218_CONFIG1_UVLO_2750000 0x0 |
133 | #define TPS65218_CONFIG1_UVLO_2950000 0x1 |
134 | #define TPS65218_CONFIG1_UVLO_3250000 0x2 |
135 | #define TPS65218_CONFIG1_UVLO_3350000 0x3 |
136 | |
137 | #define TPS65218_CONFIG2_DC12_RST BIT(7) |
138 | #define TPS65218_CONFIG2_UVLOHYS BIT(6) |
139 | #define TPS65218_CONFIG2_LS3ILIM_MASK 0xC |
140 | #define TPS65218_CONFIG2_LS2ILIM_MASK 0x3 |
141 | |
142 | #define TPS65218_CONFIG3_LS3NPFO BIT(5) |
143 | #define TPS65218_CONFIG3_LS2NPFO BIT(4) |
144 | #define TPS65218_CONFIG3_LS1NPFO BIT(3) |
145 | #define TPS65218_CONFIG3_LS3DCHRG BIT(2) |
146 | #define TPS65218_CONFIG3_LS2DCHRG BIT(1) |
147 | #define TPS65218_CONFIG3_LS1DCHRG BIT(0) |
148 | |
149 | #define TPS65218_CONTROL_DCDC1_PFM BIT(7) |
150 | #define TPS65218_CONTROL_DCDC1_MASK 0x7F |
151 | |
152 | #define TPS65218_CONTROL_DCDC2_PFM BIT(7) |
153 | #define TPS65218_CONTROL_DCDC2_MASK 0x3F |
154 | |
155 | #define TPS65218_CONTROL_DCDC3_PFM BIT(7) |
156 | #define TPS65218_CONTROL_DCDC3_MASK 0x3F |
157 | |
158 | #define TPS65218_CONTROL_DCDC4_PFM BIT(7) |
159 | #define TPS65218_CONTROL_DCDC4_MASK 0x3F |
160 | |
161 | #define TPS65218_SLEW_RATE_GO BIT(7) |
162 | #define TPS65218_SLEW_RATE_GODSBL BIT(6) |
163 | #define TPS65218_SLEW_RATE_SLEW_MASK 0x7 |
164 | |
165 | #define TPS65218_CONTROL_LDO1_MASK 0x3F |
166 | |
167 | #define TPS65218_SEQ1_DLY8 BIT(7) |
168 | #define TPS65218_SEQ1_DLY7 BIT(6) |
169 | #define TPS65218_SEQ1_DLY6 BIT(5) |
170 | #define TPS65218_SEQ1_DLY5 BIT(4) |
171 | #define TPS65218_SEQ1_DLY4 BIT(3) |
172 | #define TPS65218_SEQ1_DLY3 BIT(2) |
173 | #define TPS65218_SEQ1_DLY2 BIT(1) |
174 | #define TPS65218_SEQ1_DLY1 BIT(0) |
175 | |
176 | #define TPS65218_SEQ2_DLYFCTR BIT(7) |
177 | #define TPS65218_SEQ2_DLY9 BIT(0) |
178 | |
179 | #define TPS65218_SEQ3_DC2_SEQ_MASK 0xF0 |
180 | #define TPS65218_SEQ3_DC1_SEQ_MASK 0xF |
181 | |
182 | #define TPS65218_SEQ4_DC4_SEQ_MASK 0xF0 |
183 | #define TPS65218_SEQ4_DC3_SEQ_MASK 0xF |
184 | |
185 | #define TPS65218_SEQ5_DC6_SEQ_MASK 0xF0 |
186 | #define TPS65218_SEQ5_DC5_SEQ_MASK 0xF |
187 | |
188 | #define TPS65218_SEQ6_LS1_SEQ_MASK 0xF0 |
189 | #define TPS65218_SEQ6_LDO1_SEQ_MASK 0xF |
190 | |
191 | #define TPS65218_SEQ7_GPO3_SEQ_MASK 0xF0 |
192 | #define TPS65218_SEQ7_GPO1_SEQ_MASK 0xF |
193 | #define TPS65218_PROTECT_NONE 0 |
194 | #define TPS65218_PROTECT_L1 1 |
195 | |
196 | enum tps65218_regulator_id { |
197 | /* DCDC's */ |
198 | TPS65218_DCDC_1, |
199 | TPS65218_DCDC_2, |
200 | TPS65218_DCDC_3, |
201 | TPS65218_DCDC_4, |
202 | TPS65218_DCDC_5, |
203 | TPS65218_DCDC_6, |
204 | /* LDOs */ |
205 | TPS65218_LDO_1, |
206 | /* LS's */ |
207 | TPS65218_LS_2, |
208 | TPS65218_LS_3, |
209 | }; |
210 | |
211 | #define TPS65218_MAX_REG_ID TPS65218_LDO_1 |
212 | |
213 | /* Number of step-down converters available */ |
214 | #define TPS65218_NUM_DCDC 6 |
215 | /* Number of LDO voltage regulators available */ |
216 | #define TPS65218_NUM_LDO 1 |
217 | /* Number of total LS current regulators available */ |
218 | #define TPS65218_NUM_LS 2 |
219 | /* Number of total regulators available */ |
220 | #define TPS65218_NUM_REGULATOR (TPS65218_NUM_DCDC + TPS65218_NUM_LDO \ |
221 | + TPS65218_NUM_LS) |
222 | |
223 | /* Define the TPS65218 IRQ numbers */ |
224 | enum tps65218_irqs { |
225 | /* INT1 registers */ |
226 | TPS65218_PRGC_IRQ, |
227 | TPS65218_CC_AQC_IRQ, |
228 | TPS65218_HOT_IRQ, |
229 | TPS65218_PB_IRQ, |
230 | TPS65218_AC_IRQ, |
231 | TPS65218_VPRG_IRQ, |
232 | TPS65218_INVALID1_IRQ, |
233 | TPS65218_INVALID2_IRQ, |
234 | /* INT2 registers */ |
235 | TPS65218_LS1_I_IRQ, |
236 | TPS65218_LS2_I_IRQ, |
237 | TPS65218_LS3_I_IRQ, |
238 | TPS65218_LS1_F_IRQ, |
239 | TPS65218_LS2_F_IRQ, |
240 | TPS65218_LS3_F_IRQ, |
241 | TPS65218_INVALID3_IRQ, |
242 | TPS65218_INVALID4_IRQ, |
243 | }; |
244 | |
245 | /** |
246 | * struct tps65218 - tps65218 sub-driver chip access routines |
247 | * |
248 | * Device data may be used to access the TPS65218 chip |
249 | */ |
250 | |
251 | struct tps65218 { |
252 | struct device *dev; |
253 | unsigned int id; |
254 | u8 rev; |
255 | |
256 | struct mutex tps_lock; /* lock guarding the data structure */ |
257 | /* IRQ Data */ |
258 | int irq; |
259 | u32 irq_mask; |
260 | struct regmap_irq_chip_data *irq_data; |
261 | struct regulator_desc desc[TPS65218_NUM_REGULATOR]; |
262 | struct regmap *regmap; |
263 | u8 *strobes; |
264 | }; |
265 | |
266 | int tps65218_reg_write(struct tps65218 *tps, unsigned int reg, |
267 | unsigned int val, unsigned int level); |
268 | int tps65218_set_bits(struct tps65218 *tps, unsigned int reg, |
269 | unsigned int mask, unsigned int val, unsigned int level); |
270 | int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, |
271 | unsigned int mask, unsigned int level); |
272 | |
273 | #endif /* __LINUX_MFD_TPS65218_H */ |
274 | |