1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * include/linux/mfd/wm831x/core.h -- Core interface for WM831x |
4 | * |
5 | * Copyright 2009 Wolfson Microelectronics PLC. |
6 | * |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
8 | */ |
9 | |
10 | #ifndef __MFD_WM831X_CORE_H__ |
11 | #define __MFD_WM831X_CORE_H__ |
12 | |
13 | #include <linux/completion.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/irqdomain.h> |
16 | #include <linux/list.h> |
17 | #include <linux/regmap.h> |
18 | #include <linux/mfd/wm831x/auxadc.h> |
19 | #include <linux/mfd/wm831x/pdata.h> |
20 | #include <linux/of.h> |
21 | |
22 | /* |
23 | * Register values. |
24 | */ |
25 | #define WM831X_RESET_ID 0x00 |
26 | #define WM831X_REVISION 0x01 |
27 | #define WM831X_PARENT_ID 0x4000 |
28 | #define WM831X_SYSVDD_CONTROL 0x4001 |
29 | #define WM831X_THERMAL_MONITORING 0x4002 |
30 | #define WM831X_POWER_STATE 0x4003 |
31 | #define WM831X_WATCHDOG 0x4004 |
32 | #define WM831X_ON_PIN_CONTROL 0x4005 |
33 | #define WM831X_RESET_CONTROL 0x4006 |
34 | #define WM831X_CONTROL_INTERFACE 0x4007 |
35 | #define WM831X_SECURITY_KEY 0x4008 |
36 | #define WM831X_SOFTWARE_SCRATCH 0x4009 |
37 | #define WM831X_OTP_CONTROL 0x400A |
38 | #define WM831X_GPIO_LEVEL 0x400C |
39 | #define WM831X_SYSTEM_STATUS 0x400D |
40 | #define WM831X_ON_SOURCE 0x400E |
41 | #define WM831X_OFF_SOURCE 0x400F |
42 | #define WM831X_SYSTEM_INTERRUPTS 0x4010 |
43 | #define WM831X_INTERRUPT_STATUS_1 0x4011 |
44 | #define WM831X_INTERRUPT_STATUS_2 0x4012 |
45 | #define WM831X_INTERRUPT_STATUS_3 0x4013 |
46 | #define WM831X_INTERRUPT_STATUS_4 0x4014 |
47 | #define WM831X_INTERRUPT_STATUS_5 0x4015 |
48 | #define WM831X_IRQ_CONFIG 0x4017 |
49 | #define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018 |
50 | #define WM831X_INTERRUPT_STATUS_1_MASK 0x4019 |
51 | #define WM831X_INTERRUPT_STATUS_2_MASK 0x401A |
52 | #define WM831X_INTERRUPT_STATUS_3_MASK 0x401B |
53 | #define WM831X_INTERRUPT_STATUS_4_MASK 0x401C |
54 | #define WM831X_INTERRUPT_STATUS_5_MASK 0x401D |
55 | #define WM831X_RTC_WRITE_COUNTER 0x4020 |
56 | #define WM831X_RTC_TIME_1 0x4021 |
57 | #define WM831X_RTC_TIME_2 0x4022 |
58 | #define WM831X_RTC_ALARM_1 0x4023 |
59 | #define WM831X_RTC_ALARM_2 0x4024 |
60 | #define WM831X_RTC_CONTROL 0x4025 |
61 | #define WM831X_RTC_TRIM 0x4026 |
62 | #define WM831X_TOUCH_CONTROL_1 0x4028 |
63 | #define WM831X_TOUCH_CONTROL_2 0x4029 |
64 | #define WM831X_TOUCH_DATA_X 0x402A |
65 | #define WM831X_TOUCH_DATA_Y 0x402B |
66 | #define WM831X_TOUCH_DATA_Z 0x402C |
67 | #define WM831X_AUXADC_DATA 0x402D |
68 | #define WM831X_AUXADC_CONTROL 0x402E |
69 | #define WM831X_AUXADC_SOURCE 0x402F |
70 | #define WM831X_COMPARATOR_CONTROL 0x4030 |
71 | #define WM831X_COMPARATOR_1 0x4031 |
72 | #define WM831X_COMPARATOR_2 0x4032 |
73 | #define WM831X_COMPARATOR_3 0x4033 |
74 | #define WM831X_COMPARATOR_4 0x4034 |
75 | #define WM831X_GPIO1_CONTROL 0x4038 |
76 | #define WM831X_GPIO2_CONTROL 0x4039 |
77 | #define WM831X_GPIO3_CONTROL 0x403A |
78 | #define WM831X_GPIO4_CONTROL 0x403B |
79 | #define WM831X_GPIO5_CONTROL 0x403C |
80 | #define WM831X_GPIO6_CONTROL 0x403D |
81 | #define WM831X_GPIO7_CONTROL 0x403E |
82 | #define WM831X_GPIO8_CONTROL 0x403F |
83 | #define WM831X_GPIO9_CONTROL 0x4040 |
84 | #define WM831X_GPIO10_CONTROL 0x4041 |
85 | #define WM831X_GPIO11_CONTROL 0x4042 |
86 | #define WM831X_GPIO12_CONTROL 0x4043 |
87 | #define WM831X_GPIO13_CONTROL 0x4044 |
88 | #define WM831X_GPIO14_CONTROL 0x4045 |
89 | #define WM831X_GPIO15_CONTROL 0x4046 |
90 | #define WM831X_GPIO16_CONTROL 0x4047 |
91 | #define WM831X_CHARGER_CONTROL_1 0x4048 |
92 | #define WM831X_CHARGER_CONTROL_2 0x4049 |
93 | #define WM831X_CHARGER_STATUS 0x404A |
94 | #define WM831X_BACKUP_CHARGER_CONTROL 0x404B |
95 | #define WM831X_STATUS_LED_1 0x404C |
96 | #define WM831X_STATUS_LED_2 0x404D |
97 | #define WM831X_CURRENT_SINK_1 0x404E |
98 | #define WM831X_CURRENT_SINK_2 0x404F |
99 | #define WM831X_DCDC_ENABLE 0x4050 |
100 | #define WM831X_LDO_ENABLE 0x4051 |
101 | #define WM831X_DCDC_STATUS 0x4052 |
102 | #define WM831X_LDO_STATUS 0x4053 |
103 | #define WM831X_DCDC_UV_STATUS 0x4054 |
104 | #define WM831X_LDO_UV_STATUS 0x4055 |
105 | #define WM831X_DC1_CONTROL_1 0x4056 |
106 | #define WM831X_DC1_CONTROL_2 0x4057 |
107 | #define WM831X_DC1_ON_CONFIG 0x4058 |
108 | #define WM831X_DC1_SLEEP_CONTROL 0x4059 |
109 | #define WM831X_DC1_DVS_CONTROL 0x405A |
110 | #define WM831X_DC2_CONTROL_1 0x405B |
111 | #define WM831X_DC2_CONTROL_2 0x405C |
112 | #define WM831X_DC2_ON_CONFIG 0x405D |
113 | #define WM831X_DC2_SLEEP_CONTROL 0x405E |
114 | #define WM831X_DC2_DVS_CONTROL 0x405F |
115 | #define WM831X_DC3_CONTROL_1 0x4060 |
116 | #define WM831X_DC3_CONTROL_2 0x4061 |
117 | #define WM831X_DC3_ON_CONFIG 0x4062 |
118 | #define WM831X_DC3_SLEEP_CONTROL 0x4063 |
119 | #define WM831X_DC4_CONTROL 0x4064 |
120 | #define WM831X_DC4_SLEEP_CONTROL 0x4065 |
121 | #define WM832X_DC4_SLEEP_CONTROL 0x4067 |
122 | #define WM831X_EPE1_CONTROL 0x4066 |
123 | #define WM831X_EPE2_CONTROL 0x4067 |
124 | #define WM831X_LDO1_CONTROL 0x4068 |
125 | #define WM831X_LDO1_ON_CONTROL 0x4069 |
126 | #define WM831X_LDO1_SLEEP_CONTROL 0x406A |
127 | #define WM831X_LDO2_CONTROL 0x406B |
128 | #define WM831X_LDO2_ON_CONTROL 0x406C |
129 | #define WM831X_LDO2_SLEEP_CONTROL 0x406D |
130 | #define WM831X_LDO3_CONTROL 0x406E |
131 | #define WM831X_LDO3_ON_CONTROL 0x406F |
132 | #define WM831X_LDO3_SLEEP_CONTROL 0x4070 |
133 | #define WM831X_LDO4_CONTROL 0x4071 |
134 | #define WM831X_LDO4_ON_CONTROL 0x4072 |
135 | #define WM831X_LDO4_SLEEP_CONTROL 0x4073 |
136 | #define WM831X_LDO5_CONTROL 0x4074 |
137 | #define WM831X_LDO5_ON_CONTROL 0x4075 |
138 | #define WM831X_LDO5_SLEEP_CONTROL 0x4076 |
139 | #define WM831X_LDO6_CONTROL 0x4077 |
140 | #define WM831X_LDO6_ON_CONTROL 0x4078 |
141 | #define WM831X_LDO6_SLEEP_CONTROL 0x4079 |
142 | #define WM831X_LDO7_CONTROL 0x407A |
143 | #define WM831X_LDO7_ON_CONTROL 0x407B |
144 | #define WM831X_LDO7_SLEEP_CONTROL 0x407C |
145 | #define WM831X_LDO8_CONTROL 0x407D |
146 | #define WM831X_LDO8_ON_CONTROL 0x407E |
147 | #define WM831X_LDO8_SLEEP_CONTROL 0x407F |
148 | #define WM831X_LDO9_CONTROL 0x4080 |
149 | #define WM831X_LDO9_ON_CONTROL 0x4081 |
150 | #define WM831X_LDO9_SLEEP_CONTROL 0x4082 |
151 | #define WM831X_LDO10_CONTROL 0x4083 |
152 | #define WM831X_LDO10_ON_CONTROL 0x4084 |
153 | #define WM831X_LDO10_SLEEP_CONTROL 0x4085 |
154 | #define WM831X_LDO11_ON_CONTROL 0x4087 |
155 | #define WM831X_LDO11_SLEEP_CONTROL 0x4088 |
156 | #define WM831X_POWER_GOOD_SOURCE_1 0x408E |
157 | #define WM831X_POWER_GOOD_SOURCE_2 0x408F |
158 | #define WM831X_CLOCK_CONTROL_1 0x4090 |
159 | #define WM831X_CLOCK_CONTROL_2 0x4091 |
160 | #define WM831X_FLL_CONTROL_1 0x4092 |
161 | #define WM831X_FLL_CONTROL_2 0x4093 |
162 | #define WM831X_FLL_CONTROL_3 0x4094 |
163 | #define WM831X_FLL_CONTROL_4 0x4095 |
164 | #define WM831X_FLL_CONTROL_5 0x4096 |
165 | #define WM831X_UNIQUE_ID_1 0x7800 |
166 | #define WM831X_UNIQUE_ID_2 0x7801 |
167 | #define WM831X_UNIQUE_ID_3 0x7802 |
168 | #define WM831X_UNIQUE_ID_4 0x7803 |
169 | #define WM831X_UNIQUE_ID_5 0x7804 |
170 | #define WM831X_UNIQUE_ID_6 0x7805 |
171 | #define WM831X_UNIQUE_ID_7 0x7806 |
172 | #define WM831X_UNIQUE_ID_8 0x7807 |
173 | #define WM831X_FACTORY_OTP_ID 0x7808 |
174 | #define WM831X_FACTORY_OTP_1 0x7809 |
175 | #define WM831X_FACTORY_OTP_2 0x780A |
176 | #define WM831X_FACTORY_OTP_3 0x780B |
177 | #define WM831X_FACTORY_OTP_4 0x780C |
178 | #define WM831X_FACTORY_OTP_5 0x780D |
179 | #define WM831X_CUSTOMER_OTP_ID 0x7810 |
180 | #define WM831X_DC1_OTP_CONTROL 0x7811 |
181 | #define WM831X_DC2_OTP_CONTROL 0x7812 |
182 | #define WM831X_DC3_OTP_CONTROL 0x7813 |
183 | #define WM831X_LDO1_2_OTP_CONTROL 0x7814 |
184 | #define WM831X_LDO3_4_OTP_CONTROL 0x7815 |
185 | #define WM831X_LDO5_6_OTP_CONTROL 0x7816 |
186 | #define WM831X_LDO7_8_OTP_CONTROL 0x7817 |
187 | #define WM831X_LDO9_10_OTP_CONTROL 0x7818 |
188 | #define WM831X_LDO11_EPE_CONTROL 0x7819 |
189 | #define WM831X_GPIO1_OTP_CONTROL 0x781A |
190 | #define WM831X_GPIO2_OTP_CONTROL 0x781B |
191 | #define WM831X_GPIO3_OTP_CONTROL 0x781C |
192 | #define WM831X_GPIO4_OTP_CONTROL 0x781D |
193 | #define WM831X_GPIO5_OTP_CONTROL 0x781E |
194 | #define WM831X_GPIO6_OTP_CONTROL 0x781F |
195 | #define WM831X_DBE_CHECK_DATA 0x7827 |
196 | |
197 | /* |
198 | * R0 (0x00) - Reset ID |
199 | */ |
200 | #define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */ |
201 | #define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */ |
202 | #define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */ |
203 | |
204 | /* |
205 | * R1 (0x01) - Revision |
206 | */ |
207 | #define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */ |
208 | #define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */ |
209 | #define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */ |
210 | #define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */ |
211 | #define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */ |
212 | #define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */ |
213 | |
214 | /* |
215 | * R16384 (0x4000) - Parent ID |
216 | */ |
217 | #define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */ |
218 | #define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */ |
219 | #define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */ |
220 | |
221 | /* |
222 | * R16389 (0x4005) - ON Pin Control |
223 | */ |
224 | #define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */ |
225 | #define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */ |
226 | #define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */ |
227 | #define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */ |
228 | #define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */ |
229 | #define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */ |
230 | #define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */ |
231 | #define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */ |
232 | #define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */ |
233 | #define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */ |
234 | #define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */ |
235 | #define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */ |
236 | #define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */ |
237 | |
238 | /* |
239 | * R16528 (0x4090) - Clock Control 1 |
240 | */ |
241 | #define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */ |
242 | #define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */ |
243 | #define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */ |
244 | #define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */ |
245 | #define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */ |
246 | #define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */ |
247 | #define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */ |
248 | #define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */ |
249 | #define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */ |
250 | #define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */ |
251 | #define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */ |
252 | #define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */ |
253 | #define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */ |
254 | #define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */ |
255 | #define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */ |
256 | #define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */ |
257 | #define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */ |
258 | #define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */ |
259 | |
260 | /* |
261 | * R16529 (0x4091) - Clock Control 2 |
262 | */ |
263 | #define WM831X_XTAL_INH 0x8000 /* XTAL_INH */ |
264 | #define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */ |
265 | #define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */ |
266 | #define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */ |
267 | #define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */ |
268 | #define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */ |
269 | #define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */ |
270 | #define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */ |
271 | #define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */ |
272 | #define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */ |
273 | #define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */ |
274 | #define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */ |
275 | #define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */ |
276 | #define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */ |
277 | #define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */ |
278 | #define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */ |
279 | #define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */ |
280 | #define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */ |
281 | #define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */ |
282 | |
283 | /* |
284 | * R16530 (0x4092) - FLL Control 1 |
285 | */ |
286 | #define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */ |
287 | #define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */ |
288 | #define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */ |
289 | #define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */ |
290 | #define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ |
291 | #define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ |
292 | #define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ |
293 | #define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ |
294 | #define WM831X_FLL_ENA 0x0001 /* FLL_ENA */ |
295 | #define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */ |
296 | #define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */ |
297 | #define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */ |
298 | |
299 | /* |
300 | * R16531 (0x4093) - FLL Control 2 |
301 | */ |
302 | #define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ |
303 | #define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ |
304 | #define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ |
305 | #define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */ |
306 | #define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */ |
307 | #define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */ |
308 | #define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ |
309 | #define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ |
310 | #define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ |
311 | |
312 | /* |
313 | * R16532 (0x4094) - FLL Control 3 |
314 | */ |
315 | #define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */ |
316 | #define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */ |
317 | #define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */ |
318 | |
319 | /* |
320 | * R16533 (0x4095) - FLL Control 4 |
321 | */ |
322 | #define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ |
323 | #define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ |
324 | #define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ |
325 | #define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */ |
326 | #define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */ |
327 | #define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */ |
328 | |
329 | /* |
330 | * R16534 (0x4096) - FLL Control 5 |
331 | */ |
332 | #define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */ |
333 | #define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */ |
334 | #define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */ |
335 | #define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */ |
336 | #define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */ |
337 | #define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */ |
338 | |
339 | struct regulator_dev; |
340 | struct irq_domain; |
341 | |
342 | #define WM831X_NUM_IRQ_REGS 5 |
343 | #define WM831X_NUM_GPIO_REGS 16 |
344 | |
345 | enum wm831x_parent { |
346 | WM8310 = 0x8310, |
347 | WM8311 = 0x8311, |
348 | WM8312 = 0x8312, |
349 | WM8320 = 0x8320, |
350 | WM8321 = 0x8321, |
351 | WM8325 = 0x8325, |
352 | WM8326 = 0x8326, |
353 | }; |
354 | |
355 | struct wm831x; |
356 | |
357 | typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x, |
358 | enum wm831x_auxadc input); |
359 | |
360 | struct wm831x { |
361 | struct mutex io_lock; |
362 | |
363 | struct device *dev; |
364 | |
365 | struct regmap *regmap; |
366 | |
367 | struct wm831x_pdata pdata; |
368 | enum wm831x_parent type; |
369 | |
370 | int irq; /* Our chip IRQ */ |
371 | struct mutex irq_lock; |
372 | struct irq_domain *irq_domain; |
373 | int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ |
374 | int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ |
375 | |
376 | bool soft_shutdown; |
377 | |
378 | /* Chip revision based flags */ |
379 | unsigned has_gpio_ena:1; /* Has GPIO enable bit */ |
380 | unsigned has_cs_sts:1; /* Has current sink status bit */ |
381 | unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */ |
382 | |
383 | int num_gpio; |
384 | |
385 | /* Used by the interrupt controller code to post writes */ |
386 | int gpio_update[WM831X_NUM_GPIO_REGS]; |
387 | bool gpio_level_high[WM831X_NUM_GPIO_REGS]; |
388 | bool gpio_level_low[WM831X_NUM_GPIO_REGS]; |
389 | |
390 | struct mutex auxadc_lock; |
391 | struct list_head auxadc_pending; |
392 | u16 auxadc_active; |
393 | wm831x_auxadc_read_fn auxadc_read; |
394 | |
395 | /* The WM831x has a security key blocking access to certain |
396 | * registers. The mutex is taken by the accessors for locking |
397 | * and unlocking the security key, locked is used to fail |
398 | * writes if the lock is held. |
399 | */ |
400 | struct mutex key_lock; |
401 | unsigned int locked:1; |
402 | }; |
403 | |
404 | /* Device I/O API */ |
405 | int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg); |
406 | int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg, |
407 | unsigned short val); |
408 | void wm831x_reg_lock(struct wm831x *wm831x); |
409 | int wm831x_reg_unlock(struct wm831x *wm831x); |
410 | int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg, |
411 | unsigned short mask, unsigned short val); |
412 | int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg, |
413 | int count, u16 *buf); |
414 | |
415 | int wm831x_device_init(struct wm831x *wm831x, int irq); |
416 | int wm831x_device_suspend(struct wm831x *wm831x); |
417 | void wm831x_device_shutdown(struct wm831x *wm831x); |
418 | int wm831x_irq_init(struct wm831x *wm831x, int irq); |
419 | void wm831x_irq_exit(struct wm831x *wm831x); |
420 | void wm831x_auxadc_init(struct wm831x *wm831x); |
421 | |
422 | static inline int wm831x_irq(struct wm831x *wm831x, int irq) |
423 | { |
424 | return irq_create_mapping(host: wm831x->irq_domain, hwirq: irq); |
425 | } |
426 | |
427 | extern struct regmap_config wm831x_regmap_config; |
428 | |
429 | extern const struct of_device_id wm831x_of_match[]; |
430 | |
431 | #endif |
432 | |