| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x |
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| 4 | * |
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| 5 | * Copyright 2009 Wolfson Microelectronics PLC. |
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| 6 | * |
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| 7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __MFD_WM831X_IRQ_H__ |
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| 11 | #define __MFD_WM831X_IRQ_H__ |
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| 12 | |
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| 13 | /* Interrupt number assignments within Linux */ |
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| 14 | #define WM831X_IRQ_TEMP_THW 0 |
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| 15 | #define WM831X_IRQ_GPIO_1 1 |
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| 16 | #define WM831X_IRQ_GPIO_2 2 |
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| 17 | #define WM831X_IRQ_GPIO_3 3 |
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| 18 | #define WM831X_IRQ_GPIO_4 4 |
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| 19 | #define WM831X_IRQ_GPIO_5 5 |
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| 20 | #define WM831X_IRQ_GPIO_6 6 |
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| 21 | #define WM831X_IRQ_GPIO_7 7 |
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| 22 | #define WM831X_IRQ_GPIO_8 8 |
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| 23 | #define WM831X_IRQ_GPIO_9 9 |
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| 24 | #define WM831X_IRQ_GPIO_10 10 |
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| 25 | #define WM831X_IRQ_GPIO_11 11 |
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| 26 | #define WM831X_IRQ_GPIO_12 12 |
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| 27 | #define WM831X_IRQ_GPIO_13 13 |
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| 28 | #define WM831X_IRQ_GPIO_14 14 |
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| 29 | #define WM831X_IRQ_GPIO_15 15 |
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| 30 | #define WM831X_IRQ_GPIO_16 16 |
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| 31 | #define WM831X_IRQ_ON 17 |
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| 32 | #define WM831X_IRQ_PPM_SYSLO 18 |
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| 33 | #define WM831X_IRQ_PPM_PWR_SRC 19 |
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| 34 | #define WM831X_IRQ_PPM_USB_CURR 20 |
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| 35 | #define WM831X_IRQ_WDOG_TO 21 |
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| 36 | #define WM831X_IRQ_RTC_PER 22 |
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| 37 | #define WM831X_IRQ_RTC_ALM 23 |
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| 38 | #define WM831X_IRQ_CHG_BATT_HOT 24 |
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| 39 | #define WM831X_IRQ_CHG_BATT_COLD 25 |
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| 40 | #define WM831X_IRQ_CHG_BATT_FAIL 26 |
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| 41 | #define WM831X_IRQ_CHG_OV 27 |
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| 42 | #define WM831X_IRQ_CHG_END 29 |
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| 43 | #define WM831X_IRQ_CHG_TO 30 |
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| 44 | #define WM831X_IRQ_CHG_MODE 31 |
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| 45 | #define WM831X_IRQ_CHG_START 32 |
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| 46 | #define WM831X_IRQ_TCHDATA 33 |
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| 47 | #define WM831X_IRQ_TCHPD 34 |
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| 48 | #define WM831X_IRQ_AUXADC_DATA 35 |
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| 49 | #define WM831X_IRQ_AUXADC_DCOMP1 36 |
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| 50 | #define WM831X_IRQ_AUXADC_DCOMP2 37 |
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| 51 | #define WM831X_IRQ_AUXADC_DCOMP3 38 |
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| 52 | #define WM831X_IRQ_AUXADC_DCOMP4 39 |
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| 53 | #define WM831X_IRQ_CS1 40 |
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| 54 | #define WM831X_IRQ_CS2 41 |
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| 55 | #define WM831X_IRQ_HC_DC1 42 |
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| 56 | #define WM831X_IRQ_HC_DC2 43 |
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| 57 | #define WM831X_IRQ_UV_LDO1 44 |
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| 58 | #define WM831X_IRQ_UV_LDO2 45 |
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| 59 | #define WM831X_IRQ_UV_LDO3 46 |
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| 60 | #define WM831X_IRQ_UV_LDO4 47 |
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| 61 | #define WM831X_IRQ_UV_LDO5 48 |
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| 62 | #define WM831X_IRQ_UV_LDO6 49 |
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| 63 | #define WM831X_IRQ_UV_LDO7 50 |
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| 64 | #define WM831X_IRQ_UV_LDO8 51 |
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| 65 | #define WM831X_IRQ_UV_LDO9 52 |
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| 66 | #define WM831X_IRQ_UV_LDO10 53 |
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| 67 | #define WM831X_IRQ_UV_DC1 54 |
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| 68 | #define WM831X_IRQ_UV_DC2 55 |
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| 69 | #define WM831X_IRQ_UV_DC3 56 |
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| 70 | #define WM831X_IRQ_UV_DC4 57 |
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| 71 | |
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| 72 | #define WM831X_NUM_IRQS 58 |
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| 73 | |
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| 74 | /* |
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| 75 | * R16400 (0x4010) - System Interrupts |
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| 76 | */ |
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| 77 | #define WM831X_PS_INT 0x8000 /* PS_INT */ |
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| 78 | #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */ |
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| 79 | #define WM831X_PS_INT_SHIFT 15 /* PS_INT */ |
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| 80 | #define WM831X_PS_INT_WIDTH 1 /* PS_INT */ |
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| 81 | #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */ |
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| 82 | #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */ |
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| 83 | #define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */ |
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| 84 | #define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */ |
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| 85 | #define WM831X_GP_INT 0x2000 /* GP_INT */ |
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| 86 | #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */ |
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| 87 | #define WM831X_GP_INT_SHIFT 13 /* GP_INT */ |
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| 88 | #define WM831X_GP_INT_WIDTH 1 /* GP_INT */ |
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| 89 | #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */ |
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| 90 | #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */ |
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| 91 | #define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */ |
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| 92 | #define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */ |
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| 93 | #define WM831X_WDOG_INT 0x0800 /* WDOG_INT */ |
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| 94 | #define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */ |
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| 95 | #define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */ |
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| 96 | #define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */ |
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| 97 | #define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */ |
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| 98 | #define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */ |
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| 99 | #define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */ |
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| 100 | #define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */ |
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| 101 | #define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */ |
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| 102 | #define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */ |
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| 103 | #define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */ |
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| 104 | #define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */ |
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| 105 | #define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */ |
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| 106 | #define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */ |
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| 107 | #define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */ |
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| 108 | #define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */ |
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| 109 | #define WM831X_PPM_INT 0x0080 /* PPM_INT */ |
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| 110 | #define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */ |
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| 111 | #define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */ |
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| 112 | #define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */ |
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| 113 | #define WM831X_CS_INT 0x0040 /* CS_INT */ |
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| 114 | #define WM831X_CS_INT_MASK 0x0040 /* CS_INT */ |
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| 115 | #define WM831X_CS_INT_SHIFT 6 /* CS_INT */ |
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| 116 | #define WM831X_CS_INT_WIDTH 1 /* CS_INT */ |
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| 117 | #define WM831X_RTC_INT 0x0020 /* RTC_INT */ |
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| 118 | #define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */ |
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| 119 | #define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */ |
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| 120 | #define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */ |
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| 121 | #define WM831X_OTP_INT 0x0010 /* OTP_INT */ |
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| 122 | #define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */ |
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| 123 | #define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */ |
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| 124 | #define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */ |
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| 125 | #define WM831X_CHILD_INT 0x0008 /* CHILD_INT */ |
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| 126 | #define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */ |
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| 127 | #define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */ |
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| 128 | #define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */ |
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| 129 | #define WM831X_CHG_INT 0x0004 /* CHG_INT */ |
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| 130 | #define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */ |
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| 131 | #define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */ |
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| 132 | #define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */ |
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| 133 | #define WM831X_HC_INT 0x0002 /* HC_INT */ |
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| 134 | #define WM831X_HC_INT_MASK 0x0002 /* HC_INT */ |
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| 135 | #define WM831X_HC_INT_SHIFT 1 /* HC_INT */ |
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| 136 | #define WM831X_HC_INT_WIDTH 1 /* HC_INT */ |
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| 137 | #define WM831X_UV_INT 0x0001 /* UV_INT */ |
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| 138 | #define WM831X_UV_INT_MASK 0x0001 /* UV_INT */ |
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| 139 | #define WM831X_UV_INT_SHIFT 0 /* UV_INT */ |
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| 140 | #define WM831X_UV_INT_WIDTH 1 /* UV_INT */ |
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| 141 | |
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| 142 | /* |
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| 143 | * R16401 (0x4011) - Interrupt Status 1 |
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| 144 | */ |
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| 145 | #define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */ |
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| 146 | #define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */ |
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| 147 | #define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */ |
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| 148 | #define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */ |
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| 149 | #define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */ |
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| 150 | #define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */ |
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| 151 | #define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */ |
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| 152 | #define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */ |
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| 153 | #define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */ |
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| 154 | #define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */ |
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| 155 | #define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */ |
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| 156 | #define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */ |
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| 157 | #define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */ |
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| 158 | #define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */ |
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| 159 | #define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */ |
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| 160 | #define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */ |
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| 161 | #define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */ |
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| 162 | #define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */ |
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| 163 | #define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */ |
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| 164 | #define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */ |
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| 165 | #define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */ |
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| 166 | #define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */ |
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| 167 | #define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */ |
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| 168 | #define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */ |
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| 169 | #define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */ |
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| 170 | #define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */ |
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| 171 | #define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */ |
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| 172 | #define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */ |
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| 173 | #define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */ |
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| 174 | #define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */ |
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| 175 | #define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */ |
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| 176 | #define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */ |
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| 177 | #define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */ |
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| 178 | #define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */ |
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| 179 | #define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */ |
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| 180 | #define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */ |
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| 181 | #define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */ |
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| 182 | #define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */ |
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| 183 | #define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */ |
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| 184 | #define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */ |
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| 185 | #define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */ |
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| 186 | #define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */ |
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| 187 | #define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */ |
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| 188 | #define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */ |
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| 189 | #define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */ |
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| 190 | #define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */ |
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| 191 | #define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */ |
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| 192 | #define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */ |
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| 193 | #define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */ |
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| 194 | #define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */ |
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| 195 | #define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */ |
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| 196 | #define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */ |
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| 197 | #define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */ |
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| 198 | #define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */ |
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| 199 | #define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */ |
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| 200 | #define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */ |
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| 201 | #define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */ |
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| 202 | #define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */ |
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| 203 | #define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */ |
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| 204 | #define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */ |
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| 205 | |
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| 206 | /* |
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| 207 | * R16402 (0x4012) - Interrupt Status 2 |
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| 208 | */ |
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| 209 | #define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */ |
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| 210 | #define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */ |
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| 211 | #define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */ |
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| 212 | #define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */ |
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| 213 | #define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */ |
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| 214 | #define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */ |
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| 215 | #define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */ |
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| 216 | #define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */ |
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| 217 | #define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */ |
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| 218 | #define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */ |
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| 219 | #define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */ |
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| 220 | #define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */ |
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| 221 | #define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */ |
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| 222 | #define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */ |
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| 223 | #define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */ |
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| 224 | #define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */ |
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| 225 | #define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */ |
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| 226 | #define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */ |
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| 227 | #define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */ |
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| 228 | #define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */ |
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| 229 | #define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */ |
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| 230 | #define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */ |
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| 231 | #define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */ |
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| 232 | #define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */ |
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| 233 | #define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */ |
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| 234 | #define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */ |
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| 235 | #define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */ |
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| 236 | #define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */ |
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| 237 | #define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */ |
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| 238 | #define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */ |
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| 239 | #define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */ |
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| 240 | #define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */ |
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| 241 | #define WM831X_CS2_EINT 0x0080 /* CS2_EINT */ |
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| 242 | #define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */ |
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| 243 | #define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */ |
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| 244 | #define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */ |
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| 245 | #define WM831X_CS1_EINT 0x0040 /* CS1_EINT */ |
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| 246 | #define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */ |
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| 247 | #define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */ |
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| 248 | #define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */ |
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| 249 | #define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */ |
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| 250 | #define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */ |
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| 251 | #define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */ |
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| 252 | #define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */ |
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| 253 | #define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */ |
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| 254 | #define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */ |
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| 255 | #define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */ |
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| 256 | #define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */ |
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| 257 | #define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */ |
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| 258 | #define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */ |
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| 259 | #define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */ |
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| 260 | #define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */ |
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| 261 | #define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */ |
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| 262 | #define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */ |
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| 263 | #define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */ |
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| 264 | #define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */ |
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| 265 | #define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */ |
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| 266 | #define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */ |
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| 267 | #define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */ |
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| 268 | #define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */ |
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| 269 | |
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| 270 | /* |
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| 271 | * R16403 (0x4013) - Interrupt Status 3 |
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| 272 | */ |
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| 273 | #define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */ |
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| 274 | #define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */ |
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| 275 | #define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */ |
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| 276 | #define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */ |
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| 277 | #define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */ |
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| 278 | #define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */ |
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| 279 | #define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */ |
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| 280 | #define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */ |
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| 281 | #define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */ |
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| 282 | #define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */ |
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| 283 | #define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */ |
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| 284 | #define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */ |
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| 285 | #define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */ |
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| 286 | #define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */ |
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| 287 | #define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */ |
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| 288 | #define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */ |
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| 289 | #define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */ |
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| 290 | #define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */ |
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| 291 | #define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */ |
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| 292 | #define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */ |
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| 293 | #define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */ |
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| 294 | #define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */ |
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| 295 | #define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */ |
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| 296 | #define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */ |
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| 297 | #define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */ |
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| 298 | #define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */ |
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| 299 | #define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */ |
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| 300 | #define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */ |
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| 301 | #define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */ |
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| 302 | #define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */ |
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| 303 | #define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */ |
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| 304 | #define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */ |
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| 305 | #define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */ |
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| 306 | #define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */ |
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| 307 | #define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */ |
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| 308 | #define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */ |
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| 309 | #define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */ |
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| 310 | #define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */ |
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| 311 | #define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */ |
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| 312 | #define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */ |
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| 313 | |
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| 314 | /* |
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| 315 | * R16404 (0x4014) - Interrupt Status 4 |
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| 316 | */ |
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| 317 | #define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */ |
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| 318 | #define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */ |
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| 319 | #define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */ |
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| 320 | #define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */ |
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| 321 | #define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */ |
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| 322 | #define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */ |
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| 323 | #define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */ |
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| 324 | #define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */ |
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| 325 | #define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */ |
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| 326 | #define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */ |
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| 327 | #define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */ |
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| 328 | #define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */ |
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| 329 | #define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */ |
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| 330 | #define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */ |
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| 331 | #define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */ |
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| 332 | #define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */ |
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| 333 | #define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */ |
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| 334 | #define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */ |
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| 335 | #define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */ |
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| 336 | #define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */ |
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| 337 | #define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */ |
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| 338 | #define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */ |
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| 339 | #define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */ |
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| 340 | #define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */ |
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| 341 | |
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| 342 | /* |
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| 343 | * R16405 (0x4015) - Interrupt Status 5 |
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| 344 | */ |
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| 345 | #define WM831X_GP16_EINT 0x8000 /* GP16_EINT */ |
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| 346 | #define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */ |
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| 347 | #define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */ |
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| 348 | #define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */ |
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| 349 | #define WM831X_GP15_EINT 0x4000 /* GP15_EINT */ |
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| 350 | #define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */ |
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| 351 | #define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */ |
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| 352 | #define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */ |
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| 353 | #define WM831X_GP14_EINT 0x2000 /* GP14_EINT */ |
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| 354 | #define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */ |
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| 355 | #define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */ |
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| 356 | #define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */ |
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| 357 | #define WM831X_GP13_EINT 0x1000 /* GP13_EINT */ |
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| 358 | #define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */ |
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| 359 | #define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */ |
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| 360 | #define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */ |
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| 361 | #define WM831X_GP12_EINT 0x0800 /* GP12_EINT */ |
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| 362 | #define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */ |
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| 363 | #define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */ |
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| 364 | #define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */ |
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| 365 | #define WM831X_GP11_EINT 0x0400 /* GP11_EINT */ |
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| 366 | #define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */ |
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| 367 | #define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */ |
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| 368 | #define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */ |
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| 369 | #define WM831X_GP10_EINT 0x0200 /* GP10_EINT */ |
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| 370 | #define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */ |
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| 371 | #define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */ |
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| 372 | #define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */ |
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| 373 | #define WM831X_GP9_EINT 0x0100 /* GP9_EINT */ |
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| 374 | #define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */ |
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| 375 | #define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */ |
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| 376 | #define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */ |
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| 377 | #define WM831X_GP8_EINT 0x0080 /* GP8_EINT */ |
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| 378 | #define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */ |
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| 379 | #define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */ |
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| 380 | #define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */ |
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| 381 | #define WM831X_GP7_EINT 0x0040 /* GP7_EINT */ |
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| 382 | #define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */ |
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| 383 | #define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */ |
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| 384 | #define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */ |
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| 385 | #define WM831X_GP6_EINT 0x0020 /* GP6_EINT */ |
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| 386 | #define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */ |
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| 387 | #define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */ |
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| 388 | #define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */ |
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| 389 | #define WM831X_GP5_EINT 0x0010 /* GP5_EINT */ |
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| 390 | #define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */ |
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| 391 | #define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */ |
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| 392 | #define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */ |
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| 393 | #define WM831X_GP4_EINT 0x0008 /* GP4_EINT */ |
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| 394 | #define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */ |
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| 395 | #define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */ |
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| 396 | #define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */ |
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| 397 | #define WM831X_GP3_EINT 0x0004 /* GP3_EINT */ |
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| 398 | #define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */ |
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| 399 | #define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */ |
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| 400 | #define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */ |
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| 401 | #define WM831X_GP2_EINT 0x0002 /* GP2_EINT */ |
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| 402 | #define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */ |
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| 403 | #define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */ |
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| 404 | #define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */ |
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| 405 | #define WM831X_GP1_EINT 0x0001 /* GP1_EINT */ |
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| 406 | #define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */ |
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| 407 | #define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */ |
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| 408 | #define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */ |
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| 409 | |
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| 410 | /* |
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| 411 | * R16407 (0x4017) - IRQ Config |
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| 412 | */ |
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| 413 | #define WM831X_IRQ_OD 0x0002 /* IRQ_OD */ |
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| 414 | #define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */ |
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| 415 | #define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */ |
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| 416 | #define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */ |
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| 417 | #define WM831X_IM_IRQ 0x0001 /* IM_IRQ */ |
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| 418 | #define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */ |
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| 419 | #define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */ |
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| 420 | #define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */ |
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| 421 | |
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| 422 | /* |
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| 423 | * R16408 (0x4018) - System Interrupts Mask |
|---|
| 424 | */ |
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| 425 | #define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */ |
|---|
| 426 | #define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */ |
|---|
| 427 | #define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */ |
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| 428 | #define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */ |
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| 429 | #define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */ |
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| 430 | #define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */ |
|---|
| 431 | #define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */ |
|---|
| 432 | #define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */ |
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| 433 | #define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */ |
|---|
| 434 | #define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */ |
|---|
| 435 | #define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */ |
|---|
| 436 | #define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */ |
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| 437 | #define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */ |
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| 438 | #define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */ |
|---|
| 439 | #define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */ |
|---|
| 440 | #define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */ |
|---|
| 441 | #define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */ |
|---|
| 442 | #define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */ |
|---|
| 443 | #define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */ |
|---|
| 444 | #define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */ |
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| 445 | #define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */ |
|---|
| 446 | #define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */ |
|---|
| 447 | #define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */ |
|---|
| 448 | #define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */ |
|---|
| 449 | #define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */ |
|---|
| 450 | #define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */ |
|---|
| 451 | #define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */ |
|---|
| 452 | #define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */ |
|---|
| 453 | #define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */ |
|---|
| 454 | #define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */ |
|---|
| 455 | #define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */ |
|---|
| 456 | #define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */ |
|---|
| 457 | #define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */ |
|---|
| 458 | #define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */ |
|---|
| 459 | #define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */ |
|---|
| 460 | #define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */ |
|---|
| 461 | #define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */ |
|---|
| 462 | #define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */ |
|---|
| 463 | #define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */ |
|---|
| 464 | #define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */ |
|---|
| 465 | #define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */ |
|---|
| 466 | #define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */ |
|---|
| 467 | #define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */ |
|---|
| 468 | #define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */ |
|---|
| 469 | #define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */ |
|---|
| 470 | #define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */ |
|---|
| 471 | #define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */ |
|---|
| 472 | #define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */ |
|---|
| 473 | #define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */ |
|---|
| 474 | #define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */ |
|---|
| 475 | #define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */ |
|---|
| 476 | #define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */ |
|---|
| 477 | #define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */ |
|---|
| 478 | #define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */ |
|---|
| 479 | #define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */ |
|---|
| 480 | #define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */ |
|---|
| 481 | #define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */ |
|---|
| 482 | #define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */ |
|---|
| 483 | #define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */ |
|---|
| 484 | #define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */ |
|---|
| 485 | #define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */ |
|---|
| 486 | #define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */ |
|---|
| 487 | #define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */ |
|---|
| 488 | #define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */ |
|---|
| 489 | |
|---|
| 490 | /* |
|---|
| 491 | * R16409 (0x4019) - Interrupt Status 1 Mask |
|---|
| 492 | */ |
|---|
| 493 | #define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */ |
|---|
| 494 | #define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */ |
|---|
| 495 | #define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */ |
|---|
| 496 | #define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */ |
|---|
| 497 | #define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */ |
|---|
| 498 | #define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */ |
|---|
| 499 | #define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */ |
|---|
| 500 | #define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */ |
|---|
| 501 | #define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */ |
|---|
| 502 | #define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */ |
|---|
| 503 | #define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */ |
|---|
| 504 | #define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */ |
|---|
| 505 | #define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */ |
|---|
| 506 | #define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */ |
|---|
| 507 | #define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */ |
|---|
| 508 | #define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */ |
|---|
| 509 | #define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */ |
|---|
| 510 | #define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */ |
|---|
| 511 | #define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */ |
|---|
| 512 | #define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */ |
|---|
| 513 | #define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */ |
|---|
| 514 | #define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */ |
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| 515 | #define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */ |
|---|
| 516 | #define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */ |
|---|
| 517 | #define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */ |
|---|
| 518 | #define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */ |
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| 519 | #define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */ |
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| 520 | #define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */ |
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| 521 | #define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */ |
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| 522 | #define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */ |
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| 523 | #define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */ |
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| 524 | #define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */ |
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| 525 | #define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */ |
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| 526 | #define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */ |
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| 527 | #define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */ |
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| 528 | #define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */ |
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| 529 | #define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */ |
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| 530 | #define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */ |
|---|
| 531 | #define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */ |
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| 532 | #define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */ |
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| 533 | #define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */ |
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| 534 | #define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */ |
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| 535 | #define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */ |
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| 536 | #define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */ |
|---|
| 537 | #define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */ |
|---|
| 538 | #define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */ |
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| 539 | #define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */ |
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| 540 | #define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */ |
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| 541 | #define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */ |
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| 542 | #define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */ |
|---|
| 543 | #define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */ |
|---|
| 544 | #define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */ |
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| 545 | #define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */ |
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| 546 | #define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */ |
|---|
| 547 | #define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */ |
|---|
| 548 | #define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */ |
|---|
| 549 | #define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */ |
|---|
| 550 | #define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */ |
|---|
| 551 | #define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */ |
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| 552 | #define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */ |
|---|
| 553 | |
|---|
| 554 | /* |
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| 555 | * R16410 (0x401A) - Interrupt Status 2 Mask |
|---|
| 556 | */ |
|---|
| 557 | #define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */ |
|---|
| 558 | #define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */ |
|---|
| 559 | #define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */ |
|---|
| 560 | #define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */ |
|---|
| 561 | #define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */ |
|---|
| 562 | #define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */ |
|---|
| 563 | #define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */ |
|---|
| 564 | #define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */ |
|---|
| 565 | #define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */ |
|---|
| 566 | #define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */ |
|---|
| 567 | #define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */ |
|---|
| 568 | #define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */ |
|---|
| 569 | #define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */ |
|---|
| 570 | #define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */ |
|---|
| 571 | #define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */ |
|---|
| 572 | #define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */ |
|---|
| 573 | #define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */ |
|---|
| 574 | #define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */ |
|---|
| 575 | #define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */ |
|---|
| 576 | #define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */ |
|---|
| 577 | #define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */ |
|---|
| 578 | #define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */ |
|---|
| 579 | #define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */ |
|---|
| 580 | #define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */ |
|---|
| 581 | #define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */ |
|---|
| 582 | #define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */ |
|---|
| 583 | #define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */ |
|---|
| 584 | #define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */ |
|---|
| 585 | #define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */ |
|---|
| 586 | #define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */ |
|---|
| 587 | #define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */ |
|---|
| 588 | #define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */ |
|---|
| 589 | #define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */ |
|---|
| 590 | #define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */ |
|---|
| 591 | #define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */ |
|---|
| 592 | #define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */ |
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| 593 | #define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */ |
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| 594 | #define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */ |
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| 595 | #define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */ |
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| 596 | #define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */ |
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| 597 | #define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */ |
|---|
| 598 | #define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */ |
|---|
| 599 | #define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */ |
|---|
| 600 | #define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */ |
|---|
| 601 | #define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */ |
|---|
| 602 | #define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */ |
|---|
| 603 | #define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */ |
|---|
| 604 | #define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */ |
|---|
| 605 | #define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */ |
|---|
| 606 | #define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */ |
|---|
| 607 | #define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */ |
|---|
| 608 | #define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */ |
|---|
| 609 | #define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */ |
|---|
| 610 | #define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */ |
|---|
| 611 | #define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */ |
|---|
| 612 | #define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */ |
|---|
| 613 | #define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */ |
|---|
| 614 | #define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */ |
|---|
| 615 | #define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */ |
|---|
| 616 | #define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */ |
|---|
| 617 | |
|---|
| 618 | /* |
|---|
| 619 | * R16411 (0x401B) - Interrupt Status 3 Mask |
|---|
| 620 | */ |
|---|
| 621 | #define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */ |
|---|
| 622 | #define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */ |
|---|
| 623 | #define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */ |
|---|
| 624 | #define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */ |
|---|
| 625 | #define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */ |
|---|
| 626 | #define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */ |
|---|
| 627 | #define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */ |
|---|
| 628 | #define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */ |
|---|
| 629 | #define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */ |
|---|
| 630 | #define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */ |
|---|
| 631 | #define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */ |
|---|
| 632 | #define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */ |
|---|
| 633 | #define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */ |
|---|
| 634 | #define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */ |
|---|
| 635 | #define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */ |
|---|
| 636 | #define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */ |
|---|
| 637 | #define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */ |
|---|
| 638 | #define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */ |
|---|
| 639 | #define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */ |
|---|
| 640 | #define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */ |
|---|
| 641 | #define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */ |
|---|
| 642 | #define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */ |
|---|
| 643 | #define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */ |
|---|
| 644 | #define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */ |
|---|
| 645 | #define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */ |
|---|
| 646 | #define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */ |
|---|
| 647 | #define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */ |
|---|
| 648 | #define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */ |
|---|
| 649 | #define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */ |
|---|
| 650 | #define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */ |
|---|
| 651 | #define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */ |
|---|
| 652 | #define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */ |
|---|
| 653 | #define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */ |
|---|
| 654 | #define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */ |
|---|
| 655 | #define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */ |
|---|
| 656 | #define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */ |
|---|
| 657 | #define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */ |
|---|
| 658 | #define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */ |
|---|
| 659 | #define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */ |
|---|
| 660 | #define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */ |
|---|
| 661 | |
|---|
| 662 | /* |
|---|
| 663 | * R16412 (0x401C) - Interrupt Status 4 Mask |
|---|
| 664 | */ |
|---|
| 665 | #define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */ |
|---|
| 666 | #define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */ |
|---|
| 667 | #define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */ |
|---|
| 668 | #define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */ |
|---|
| 669 | #define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */ |
|---|
| 670 | #define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */ |
|---|
| 671 | #define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */ |
|---|
| 672 | #define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */ |
|---|
| 673 | #define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */ |
|---|
| 674 | #define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */ |
|---|
| 675 | #define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */ |
|---|
| 676 | #define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */ |
|---|
| 677 | #define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */ |
|---|
| 678 | #define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */ |
|---|
| 679 | #define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */ |
|---|
| 680 | #define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */ |
|---|
| 681 | #define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */ |
|---|
| 682 | #define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */ |
|---|
| 683 | #define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */ |
|---|
| 684 | #define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */ |
|---|
| 685 | #define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */ |
|---|
| 686 | #define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */ |
|---|
| 687 | #define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */ |
|---|
| 688 | #define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */ |
|---|
| 689 | |
|---|
| 690 | /* |
|---|
| 691 | * R16413 (0x401D) - Interrupt Status 5 Mask |
|---|
| 692 | */ |
|---|
| 693 | #define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */ |
|---|
| 694 | #define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */ |
|---|
| 695 | #define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */ |
|---|
| 696 | #define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */ |
|---|
| 697 | #define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */ |
|---|
| 698 | #define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */ |
|---|
| 699 | #define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */ |
|---|
| 700 | #define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */ |
|---|
| 701 | #define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */ |
|---|
| 702 | #define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */ |
|---|
| 703 | #define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */ |
|---|
| 704 | #define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */ |
|---|
| 705 | #define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */ |
|---|
| 706 | #define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */ |
|---|
| 707 | #define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */ |
|---|
| 708 | #define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */ |
|---|
| 709 | #define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */ |
|---|
| 710 | #define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */ |
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| 711 | #define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */ |
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| 712 | #define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */ |
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| 713 | #define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ |
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| 714 | #define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ |
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| 715 | #define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ |
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| 716 | #define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ |
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| 717 | #define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ |
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| 718 | #define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ |
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| 719 | #define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ |
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| 720 | #define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ |
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| 721 | #define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ |
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| 722 | #define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ |
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| 723 | #define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ |
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| 724 | #define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ |
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| 725 | #define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ |
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| 726 | #define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ |
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| 727 | #define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ |
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| 728 | #define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ |
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| 729 | #define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ |
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| 730 | #define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ |
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| 731 | #define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ |
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| 732 | #define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ |
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| 733 | #define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ |
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| 734 | #define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ |
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| 735 | #define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ |
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| 736 | #define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ |
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| 737 | #define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ |
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| 738 | #define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ |
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| 739 | #define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ |
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| 740 | #define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ |
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| 741 | #define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ |
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| 742 | #define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ |
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| 743 | #define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ |
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| 744 | #define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ |
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| 745 | #define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ |
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| 746 | #define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ |
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| 747 | #define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ |
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| 748 | #define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ |
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| 749 | #define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ |
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| 750 | #define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ |
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| 751 | #define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ |
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| 752 | #define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ |
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| 753 | #define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ |
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| 754 | #define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ |
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| 755 | #define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ |
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| 756 | #define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ |
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| 757 | |
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| 758 | |
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| 759 | #endif |
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| 760 | |
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