| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2015 Microchip Technology |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _MICROCHIPPHY_H |
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| 7 | #define _MICROCHIPPHY_H |
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| 8 | |
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| 9 | #define LAN88XX_INT_MASK (0x19) |
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| 10 | #define LAN88XX_INT_MASK_MDINTPIN_EN_ (0x8000) |
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| 11 | #define LAN88XX_INT_MASK_SPEED_CHANGE_ (0x4000) |
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| 12 | #define LAN88XX_INT_MASK_LINK_CHANGE_ (0x2000) |
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| 13 | #define LAN88XX_INT_MASK_FDX_CHANGE_ (0x1000) |
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| 14 | #define LAN88XX_INT_MASK_AUTONEG_ERR_ (0x0800) |
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| 15 | #define LAN88XX_INT_MASK_AUTONEG_DONE_ (0x0400) |
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| 16 | #define LAN88XX_INT_MASK_POE_DETECT_ (0x0200) |
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| 17 | #define LAN88XX_INT_MASK_SYMBOL_ERR_ (0x0100) |
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| 18 | #define LAN88XX_INT_MASK_FAST_LINK_FAIL_ (0x0080) |
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| 19 | #define LAN88XX_INT_MASK_WOL_EVENT_ (0x0040) |
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| 20 | #define LAN88XX_INT_MASK_EXTENDED_INT_ (0x0020) |
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| 21 | #define LAN88XX_INT_MASK_RESERVED_ (0x0010) |
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| 22 | #define LAN88XX_INT_MASK_FALSE_CARRIER_ (0x0008) |
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| 23 | #define LAN88XX_INT_MASK_LINK_SPEED_DS_ (0x0004) |
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| 24 | #define LAN88XX_INT_MASK_MASTER_SLAVE_DONE_ (0x0002) |
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| 25 | #define LAN88XX_INT_MASK_RX__ER_ (0x0001) |
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| 26 | |
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| 27 | #define LAN88XX_INT_STS (0x1A) |
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| 28 | #define LAN88XX_INT_STS_INT_ACTIVE_ (0x8000) |
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| 29 | #define LAN88XX_INT_STS_SPEED_CHANGE_ (0x4000) |
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| 30 | #define LAN88XX_INT_STS_LINK_CHANGE_ (0x2000) |
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| 31 | #define LAN88XX_INT_STS_FDX_CHANGE_ (0x1000) |
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| 32 | #define LAN88XX_INT_STS_AUTONEG_ERR_ (0x0800) |
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| 33 | #define LAN88XX_INT_STS_AUTONEG_DONE_ (0x0400) |
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| 34 | #define LAN88XX_INT_STS_POE_DETECT_ (0x0200) |
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| 35 | #define LAN88XX_INT_STS_SYMBOL_ERR_ (0x0100) |
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| 36 | #define LAN88XX_INT_STS_FAST_LINK_FAIL_ (0x0080) |
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| 37 | #define LAN88XX_INT_STS_WOL_EVENT_ (0x0040) |
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| 38 | #define LAN88XX_INT_STS_EXTENDED_INT_ (0x0020) |
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| 39 | #define LAN88XX_INT_STS_RESERVED_ (0x0010) |
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| 40 | #define LAN88XX_INT_STS_FALSE_CARRIER_ (0x0008) |
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| 41 | #define LAN88XX_INT_STS_LINK_SPEED_DS_ (0x0004) |
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| 42 | #define LAN88XX_INT_STS_MASTER_SLAVE_DONE_ (0x0002) |
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| 43 | #define LAN88XX_INT_STS_RX_ER_ (0x0001) |
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| 44 | |
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| 45 | #define LAN88XX_EXT_PAGE_ACCESS (0x1F) |
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| 46 | #define LAN88XX_EXT_PAGE_SPACE_0 (0x0000) |
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| 47 | #define LAN88XX_EXT_PAGE_SPACE_1 (0x0001) |
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| 48 | #define LAN88XX_EXT_PAGE_SPACE_2 (0x0002) |
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| 49 | |
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| 50 | /* Extended Register Page 1 space */ |
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| 51 | #define LAN88XX_EXT_MODE_CTRL (0x13) |
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| 52 | #define LAN88XX_EXT_MODE_CTRL_MDIX_MASK_ (0x000C) |
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| 53 | #define LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_ (0x0000) |
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| 54 | #define LAN88XX_EXT_MODE_CTRL_MDI_ (0x0008) |
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| 55 | #define LAN88XX_EXT_MODE_CTRL_MDI_X_ (0x000C) |
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| 56 | |
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| 57 | /* MMD 3 Registers */ |
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| 58 | #define LAN88XX_MMD3_CHIP_ID (32877) |
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| 59 | #define LAN88XX_MMD3_CHIP_REV (32878) |
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| 60 | |
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| 61 | /* Registers specific to the LAN7800/LAN7850 embedded phy */ |
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| 62 | #define LAN78XX_PHY_LED_MODE_SELECT (0x1D) |
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| 63 | |
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| 64 | /* DSP registers */ |
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| 65 | #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG (0x806A) |
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| 66 | #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_ (0x2000) |
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| 67 | #define LAN88XX_EXT_PAGE_ACCESS_TR (0x52B5) |
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| 68 | #define LAN88XX_EXT_PAGE_TR_CR 16 |
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| 69 | #define LAN88XX_EXT_PAGE_TR_LOW_DATA 17 |
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| 70 | #define LAN88XX_EXT_PAGE_TR_HIGH_DATA 18 |
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| 71 | |
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| 72 | #endif /* _MICROCHIPPHY_H */ |
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| 73 | |
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