1 | /* |
2 | * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. |
3 | * |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU |
6 | * General Public License (GPL) Version 2, available from the file |
7 | * COPYING in the main directory of this source tree, or the |
8 | * OpenIB.org BSD license below: |
9 | * |
10 | * Redistribution and use in source and binary forms, with or |
11 | * without modification, are permitted provided that the following |
12 | * conditions are met: |
13 | * |
14 | * - Redistributions of source code must retain the above |
15 | * copyright notice, this list of conditions and the following |
16 | * disclaimer. |
17 | * |
18 | * - Redistributions in binary form must reproduce the above |
19 | * copyright notice, this list of conditions and the following |
20 | * disclaimer in the documentation and/or other materials |
21 | * provided with the distribution. |
22 | * |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
30 | * SOFTWARE. |
31 | */ |
32 | |
33 | #ifndef MLX4_QP_H |
34 | #define MLX4_QP_H |
35 | |
36 | #include <linux/types.h> |
37 | #include <linux/if_ether.h> |
38 | |
39 | #include <linux/mlx4/device.h> |
40 | |
41 | #define MLX4_INVALID_LKEY 0x100 |
42 | |
43 | enum mlx4_qp_optpar { |
44 | MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, |
45 | MLX4_QP_OPTPAR_RRE = 1 << 1, |
46 | MLX4_QP_OPTPAR_RAE = 1 << 2, |
47 | MLX4_QP_OPTPAR_RWE = 1 << 3, |
48 | MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4, |
49 | MLX4_QP_OPTPAR_Q_KEY = 1 << 5, |
50 | MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, |
51 | MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, |
52 | MLX4_QP_OPTPAR_SRA_MAX = 1 << 8, |
53 | MLX4_QP_OPTPAR_RRA_MAX = 1 << 9, |
54 | MLX4_QP_OPTPAR_PM_STATE = 1 << 10, |
55 | MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12, |
56 | MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13, |
57 | MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, |
58 | MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16, |
59 | MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20, |
60 | MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21, |
61 | }; |
62 | |
63 | enum mlx4_qp_state { |
64 | MLX4_QP_STATE_RST = 0, |
65 | MLX4_QP_STATE_INIT = 1, |
66 | MLX4_QP_STATE_RTR = 2, |
67 | MLX4_QP_STATE_RTS = 3, |
68 | MLX4_QP_STATE_SQER = 4, |
69 | MLX4_QP_STATE_SQD = 5, |
70 | MLX4_QP_STATE_ERR = 6, |
71 | MLX4_QP_STATE_SQ_DRAINING = 7, |
72 | MLX4_QP_NUM_STATE |
73 | }; |
74 | |
75 | enum { |
76 | MLX4_QP_ST_RC = 0x0, |
77 | MLX4_QP_ST_UC = 0x1, |
78 | MLX4_QP_ST_RD = 0x2, |
79 | MLX4_QP_ST_UD = 0x3, |
80 | MLX4_QP_ST_XRC = 0x6, |
81 | MLX4_QP_ST_MLX = 0x7 |
82 | }; |
83 | |
84 | enum { |
85 | MLX4_QP_PM_MIGRATED = 0x3, |
86 | MLX4_QP_PM_ARMED = 0x0, |
87 | MLX4_QP_PM_REARM = 0x1 |
88 | }; |
89 | |
90 | enum { |
91 | /* params1 */ |
92 | MLX4_QP_BIT_SRE = 1 << 15, |
93 | MLX4_QP_BIT_SWE = 1 << 14, |
94 | MLX4_QP_BIT_SAE = 1 << 13, |
95 | /* params2 */ |
96 | MLX4_QP_BIT_RRE = 1 << 15, |
97 | MLX4_QP_BIT_RWE = 1 << 14, |
98 | MLX4_QP_BIT_RAE = 1 << 13, |
99 | MLX4_QP_BIT_FPP = 1 << 3, |
100 | MLX4_QP_BIT_RIC = 1 << 4, |
101 | }; |
102 | |
103 | enum { |
104 | = 0, |
105 | = 1, |
106 | |
107 | = 1 << 0, |
108 | = 1 << 1, |
109 | = 1 << 2, |
110 | = 1 << 3, |
111 | = 1 << 4, |
112 | = 1 << 5, |
113 | |
114 | = 0 << 6, |
115 | = 2 << 6, |
116 | = 3 << 6, |
117 | |
118 | /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ |
119 | = 0x24, |
120 | /* offset of being RSS indirection QP within mlx4_qp_context.flags */ |
121 | = 13, |
122 | }; |
123 | |
124 | #define 40 |
125 | |
126 | struct { |
127 | __be32 ; |
128 | __be32 ; |
129 | u16 ; |
130 | u8 ; |
131 | u8 ; |
132 | __be32 [MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)]; |
133 | __be32 ; |
134 | }; |
135 | |
136 | struct mlx4_qp_path { |
137 | u8 fl; |
138 | union { |
139 | u8 vlan_control; |
140 | u8 control; |
141 | }; |
142 | u8 disable_pkey_check; |
143 | u8 pkey_index; |
144 | u8 counter_index; |
145 | u8 grh_mylmc; |
146 | __be16 rlid; |
147 | u8 ackto; |
148 | u8 mgid_index; |
149 | u8 static_rate; |
150 | u8 hop_limit; |
151 | __be32 tclass_flowlabel; |
152 | u8 rgid[16]; |
153 | u8 sched_queue; |
154 | u8 vlan_index; |
155 | u8 feup; |
156 | u8 fvl_rx; |
157 | u8 reserved4[2]; |
158 | u8 dmac[ETH_ALEN]; |
159 | }; |
160 | |
161 | enum { /* fl */ |
162 | MLX4_FL_CV = 1 << 6, |
163 | MLX4_FL_SV = 1 << 5, |
164 | MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2, |
165 | MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1, |
166 | MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0, |
167 | }; |
168 | |
169 | enum { /* control */ |
170 | MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7, |
171 | }; |
172 | |
173 | enum { /* vlan_control */ |
174 | MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6, |
175 | MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */ |
176 | MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4, |
177 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2, |
178 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */ |
179 | MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0 |
180 | }; |
181 | |
182 | enum { /* feup */ |
183 | MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */ |
184 | MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */ |
185 | MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */ |
186 | }; |
187 | |
188 | enum { /* fvl_rx */ |
189 | MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */ |
190 | }; |
191 | |
192 | struct mlx4_qp_context { |
193 | __be32 flags; |
194 | __be32 pd; |
195 | u8 mtu_msgmax; |
196 | u8 rq_size_stride; |
197 | u8 sq_size_stride; |
198 | u8 rlkey_roce_mode; |
199 | __be32 usr_page; |
200 | __be32 local_qpn; |
201 | __be32 remote_qpn; |
202 | struct mlx4_qp_path pri_path; |
203 | struct mlx4_qp_path alt_path; |
204 | __be32 params1; |
205 | u32 reserved1; |
206 | __be32 next_send_psn; |
207 | __be32 cqn_send; |
208 | __be16 roce_entropy; |
209 | __be16 reserved2[3]; |
210 | __be32 last_acked_psn; |
211 | __be32 ssn; |
212 | __be32 params2; |
213 | __be32 rnr_nextrecvpsn; |
214 | __be32 xrcd; |
215 | __be32 cqn_recv; |
216 | __be64 db_rec_addr; |
217 | __be32 qkey; |
218 | __be32 srqn; |
219 | __be32 msn; |
220 | __be16 rq_wqe_counter; |
221 | __be16 sq_wqe_counter; |
222 | u32 reserved3; |
223 | __be16 rate_limit_params; |
224 | u8 reserved4; |
225 | u8 qos_vport; |
226 | __be32 param3; |
227 | __be32 nummmcpeers_basemkey; |
228 | u8 log_page_size; |
229 | u8 reserved5[2]; |
230 | u8 mtt_base_addr_h; |
231 | __be32 mtt_base_addr_l; |
232 | u32 reserved6[10]; |
233 | }; |
234 | |
235 | struct mlx4_update_qp_context { |
236 | __be64 qp_mask; |
237 | __be64 primary_addr_path_mask; |
238 | __be64 secondary_addr_path_mask; |
239 | u64 reserved1; |
240 | struct mlx4_qp_context qp_context; |
241 | u64 reserved2[58]; |
242 | }; |
243 | |
244 | enum { |
245 | MLX4_UPD_QP_MASK_PM_STATE = 32, |
246 | MLX4_UPD_QP_MASK_VSD = 33, |
247 | MLX4_UPD_QP_MASK_QOS_VPP = 34, |
248 | MLX4_UPD_QP_MASK_RATE_LIMIT = 35, |
249 | }; |
250 | |
251 | enum { |
252 | MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32, |
253 | MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32, |
254 | MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32, |
255 | MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32, |
256 | MLX4_UPD_QP_PATH_MASK_CV = 4 + 32, |
257 | MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32, |
258 | MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32, |
259 | MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32, |
260 | MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32, |
261 | MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32, |
262 | MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32, |
263 | MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32, |
264 | MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32, |
265 | MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32, |
266 | MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32, |
267 | MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32, |
268 | MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32, |
269 | MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32, |
270 | MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32, |
271 | MLX4_UPD_QP_PATH_MASK_SV = 22 + 32, |
272 | }; |
273 | |
274 | enum { /* param3 */ |
275 | MLX4_STRIP_VLAN = 1 << 30 |
276 | }; |
277 | |
278 | /* Which firmware version adds support for NEC (NoErrorCompletion) bit */ |
279 | #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) |
280 | |
281 | enum { |
282 | MLX4_WQE_CTRL_NEC = 1 << 29, |
283 | MLX4_WQE_CTRL_IIP = 1 << 28, |
284 | MLX4_WQE_CTRL_ILP = 1 << 27, |
285 | MLX4_WQE_CTRL_FENCE = 1 << 6, |
286 | MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, |
287 | MLX4_WQE_CTRL_SOLICITED = 1 << 1, |
288 | MLX4_WQE_CTRL_IP_CSUM = 1 << 4, |
289 | MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5, |
290 | MLX4_WQE_CTRL_INS_CVLAN = 1 << 6, |
291 | MLX4_WQE_CTRL_INS_SVLAN = 1 << 7, |
292 | MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7, |
293 | MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0, |
294 | }; |
295 | |
296 | union mlx4_wqe_qpn_vlan { |
297 | struct { |
298 | __be16 vlan_tag; |
299 | u8 ins_vlan; |
300 | u8 fence_size; |
301 | }; |
302 | __be32 bf_qpn; |
303 | }; |
304 | |
305 | struct mlx4_wqe_ctrl_seg { |
306 | __be32 owner_opcode; |
307 | union mlx4_wqe_qpn_vlan qpn_vlan; |
308 | /* |
309 | * High 24 bits are SRC remote buffer; low 8 bits are flags: |
310 | * [7] SO (strong ordering) |
311 | * [5] TCP/UDP checksum |
312 | * [4] IP checksum |
313 | * [3:2] C (generate completion queue entry) |
314 | * [1] SE (solicited event) |
315 | * [0] FL (force loopback) |
316 | */ |
317 | union { |
318 | __be32 srcrb_flags; |
319 | __be16 srcrb_flags16[2]; |
320 | }; |
321 | /* |
322 | * imm is immediate data for send/RDMA write w/ immediate; |
323 | * also invalidation key for send with invalidate; input |
324 | * modifier for WQEs on CCQs. |
325 | */ |
326 | __be32 imm; |
327 | }; |
328 | |
329 | enum { |
330 | MLX4_WQE_MLX_VL15 = 1 << 17, |
331 | MLX4_WQE_MLX_SLR = 1 << 16 |
332 | }; |
333 | |
334 | struct mlx4_wqe_mlx_seg { |
335 | u8 owner; |
336 | u8 reserved1[2]; |
337 | u8 opcode; |
338 | __be16 sched_prio; |
339 | u8 reserved2; |
340 | u8 size; |
341 | /* |
342 | * [17] VL15 |
343 | * [16] SLR |
344 | * [15:12] static rate |
345 | * [11:8] SL |
346 | * [4] ICRC |
347 | * [3:2] C |
348 | * [0] FL (force loopback) |
349 | */ |
350 | __be32 flags; |
351 | __be16 rlid; |
352 | u16 reserved3; |
353 | }; |
354 | |
355 | struct mlx4_wqe_datagram_seg { |
356 | __be32 av[8]; |
357 | __be32 dqpn; |
358 | __be32 qkey; |
359 | __be16 vlan; |
360 | u8 mac[ETH_ALEN]; |
361 | }; |
362 | |
363 | struct mlx4_wqe_lso_seg { |
364 | __be32 mss_hdr_size; |
365 | __be32 []; |
366 | }; |
367 | |
368 | enum mlx4_wqe_bind_seg_flags2 { |
369 | MLX4_WQE_BIND_ZERO_BASED = (1 << 30), |
370 | MLX4_WQE_BIND_TYPE_2 = (1 << 31), |
371 | }; |
372 | |
373 | struct mlx4_wqe_bind_seg { |
374 | __be32 flags1; |
375 | __be32 flags2; |
376 | __be32 new_rkey; |
377 | __be32 lkey; |
378 | __be64 addr; |
379 | __be64 length; |
380 | }; |
381 | |
382 | enum { |
383 | MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27, |
384 | MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, |
385 | MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29, |
386 | MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30, |
387 | MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31 |
388 | }; |
389 | |
390 | struct mlx4_wqe_fmr_seg { |
391 | __be32 flags; |
392 | __be32 mem_key; |
393 | __be64 buf_list; |
394 | __be64 start_addr; |
395 | __be64 reg_len; |
396 | __be32 offset; |
397 | __be32 page_size; |
398 | u32 reserved[2]; |
399 | }; |
400 | |
401 | struct mlx4_wqe_fmr_ext_seg { |
402 | u8 flags; |
403 | u8 reserved; |
404 | __be16 app_mask; |
405 | __be16 wire_app_tag; |
406 | __be16 mem_app_tag; |
407 | __be32 wire_ref_tag_base; |
408 | __be32 mem_ref_tag_base; |
409 | }; |
410 | |
411 | struct mlx4_wqe_local_inval_seg { |
412 | u64 reserved1; |
413 | __be32 mem_key; |
414 | u32 reserved2; |
415 | u64 reserved3[2]; |
416 | }; |
417 | |
418 | struct mlx4_wqe_raddr_seg { |
419 | __be64 raddr; |
420 | __be32 rkey; |
421 | u32 reserved; |
422 | }; |
423 | |
424 | struct mlx4_wqe_atomic_seg { |
425 | __be64 swap_add; |
426 | __be64 compare; |
427 | }; |
428 | |
429 | struct mlx4_wqe_masked_atomic_seg { |
430 | __be64 swap_add; |
431 | __be64 compare; |
432 | __be64 swap_add_mask; |
433 | __be64 compare_mask; |
434 | }; |
435 | |
436 | struct mlx4_wqe_data_seg { |
437 | __be32 byte_count; |
438 | __be32 lkey; |
439 | __be64 addr; |
440 | }; |
441 | |
442 | enum { |
443 | MLX4_INLINE_ALIGN = 64, |
444 | MLX4_INLINE_SEG = 1 << 31, |
445 | }; |
446 | |
447 | struct mlx4_wqe_inline_seg { |
448 | __be32 byte_count; |
449 | __u8 data[]; |
450 | }; |
451 | |
452 | enum mlx4_update_qp_attr { |
453 | MLX4_UPDATE_QP_SMAC = 1 << 0, |
454 | MLX4_UPDATE_QP_VSD = 1 << 1, |
455 | MLX4_UPDATE_QP_RATE_LIMIT = 1 << 2, |
456 | MLX4_UPDATE_QP_QOS_VPORT = 1 << 3, |
457 | MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB = 1 << 4, |
458 | MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 5) - 1 |
459 | }; |
460 | |
461 | enum mlx4_update_qp_params_flags { |
462 | MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB = 1 << 0, |
463 | MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 1, |
464 | }; |
465 | |
466 | struct mlx4_update_qp_params { |
467 | u8 smac_index; |
468 | u8 qos_vport; |
469 | u32 flags; |
470 | u16 rate_unit; |
471 | u16 rate_val; |
472 | }; |
473 | |
474 | struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn); |
475 | int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, |
476 | enum mlx4_update_qp_attr attr, |
477 | struct mlx4_update_qp_params *params); |
478 | int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
479 | enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, |
480 | struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar, |
481 | int sqd_event, struct mlx4_qp *qp); |
482 | |
483 | int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, |
484 | struct mlx4_qp_context *context); |
485 | |
486 | int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
487 | struct mlx4_qp_context *context, |
488 | struct mlx4_qp *qp, enum mlx4_qp_state *qp_state); |
489 | |
490 | static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn) |
491 | { |
492 | return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1)); |
493 | } |
494 | |
495 | void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp); |
496 | |
497 | static inline u16 folded_qp(u32 q) |
498 | { |
499 | u16 res; |
500 | |
501 | res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) | (q & 0xff00); |
502 | return res; |
503 | } |
504 | |
505 | u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn); |
506 | |
507 | void mlx4_put_qp(struct mlx4_qp *qp); |
508 | #endif /* MLX4_QP_H */ |
509 | |