1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Primary function overlay window definitions |
3 | * and service functions used by LPDDR chips |
4 | */ |
5 | #ifndef __LINUX_MTD_PFOW_H |
6 | #define __LINUX_MTD_PFOW_H |
7 | |
8 | #include <linux/mtd/qinfo.h> |
9 | |
10 | /* PFOW registers addressing */ |
11 | /* Address of symbol "P" */ |
12 | #define PFOW_QUERY_STRING_P 0x0000 |
13 | /* Address of symbol "F" */ |
14 | #define PFOW_QUERY_STRING_F 0x0002 |
15 | /* Address of symbol "O" */ |
16 | #define PFOW_QUERY_STRING_O 0x0004 |
17 | /* Address of symbol "W" */ |
18 | #define PFOW_QUERY_STRING_W 0x0006 |
19 | /* Identification info for LPDDR chip */ |
20 | #define PFOW_MANUFACTURER_ID 0x0020 |
21 | #define PFOW_DEVICE_ID 0x0022 |
22 | /* Address in PFOW where prog buffer can be found */ |
23 | #define PFOW_PROGRAM_BUFFER_OFFSET 0x0040 |
24 | /* Size of program buffer in words */ |
25 | #define PFOW_PROGRAM_BUFFER_SIZE 0x0042 |
26 | /* Address command code register */ |
27 | #define PFOW_COMMAND_CODE 0x0080 |
28 | /* command data register */ |
29 | #define PFOW_COMMAND_DATA 0x0084 |
30 | /* command address register lower address bits */ |
31 | #define PFOW_COMMAND_ADDRESS_L 0x0088 |
32 | /* command address register upper address bits */ |
33 | #define PFOW_COMMAND_ADDRESS_H 0x008a |
34 | /* number of bytes to be proggrammed lower address bits */ |
35 | #define PFOW_DATA_COUNT_L 0x0090 |
36 | /* number of bytes to be proggrammed higher address bits */ |
37 | #define PFOW_DATA_COUNT_H 0x0092 |
38 | /* command execution register, the only possible value is 0x01 */ |
39 | #define PFOW_COMMAND_EXECUTE 0x00c0 |
40 | /* 0x01 should be written at this address to clear buffer */ |
41 | #define PFOW_CLEAR_PROGRAM_BUFFER 0x00c4 |
42 | /* device program/erase suspend register */ |
43 | #define PFOW_PROGRAM_ERASE_SUSPEND 0x00c8 |
44 | /* device status register */ |
45 | #define PFOW_DSR 0x00cc |
46 | |
47 | /* LPDDR memory device command codes */ |
48 | /* They are possible values of PFOW command code register */ |
49 | #define LPDDR_WORD_PROGRAM 0x0041 |
50 | #define LPDDR_BUFF_PROGRAM 0x00E9 |
51 | #define LPDDR_BLOCK_ERASE 0x0020 |
52 | #define LPDDR_LOCK_BLOCK 0x0061 |
53 | #define LPDDR_UNLOCK_BLOCK 0x0062 |
54 | #define LPDDR_READ_BLOCK_LOCK_STATUS 0x0065 |
55 | #define LPDDR_INFO_QUERY 0x0098 |
56 | #define LPDDR_READ_OTP 0x0097 |
57 | #define LPDDR_PROG_OTP 0x00C0 |
58 | #define LPDDR_RESUME 0x00D0 |
59 | |
60 | /* Defines possible value of PFOW command execution register */ |
61 | #define LPDDR_START_EXECUTION 0x0001 |
62 | |
63 | /* Defines possible value of PFOW program/erase suspend register */ |
64 | #define LPDDR_SUSPEND 0x0001 |
65 | |
66 | /* Possible values of PFOW device status register */ |
67 | /* access R - read; RC read & clearable */ |
68 | #define DSR_DPS (1<<1) /* RC; device protect status |
69 | * 0 - not protected 1 - locked */ |
70 | #define DSR_PSS (1<<2) /* R; program suspend status; |
71 | * 0-prog in progress/completed, |
72 | * 1- prog suspended */ |
73 | #define DSR_VPPS (1<<3) /* RC; 0-Vpp OK, * 1-Vpp low */ |
74 | #define DSR_PROGRAM_STATUS (1<<4) /* RC; 0-successful, 1-error */ |
75 | #define DSR_ERASE_STATUS (1<<5) /* RC; erase or blank check status; |
76 | * 0-success erase/blank check, |
77 | * 1 blank check error */ |
78 | #define DSR_ESS (1<<6) /* R; erase suspend status; |
79 | * 0-erase in progress/complete, |
80 | * 1 erase suspended */ |
81 | #define DSR_READY_STATUS (1<<7) /* R; Device status |
82 | * 0-busy, |
83 | * 1-ready */ |
84 | #define DSR_RPS (0x3<<8) /* RC; region program status |
85 | * 00 - Success, |
86 | * 01-re-program attempt in region with |
87 | * object mode data, |
88 | * 10-object mode program w attempt in |
89 | * region with control mode data |
90 | * 11-attempt to program invalid half |
91 | * with 0x41 command */ |
92 | #define DSR_AOS (1<<12) /* RC; 1- AO related failure */ |
93 | #define DSR_AVAILABLE (1<<15) /* R; Device availbility |
94 | * 1 - Device available |
95 | * 0 - not available */ |
96 | |
97 | /* The superset of all possible error bits in DSR */ |
98 | #define DSR_ERR 0x133A |
99 | |
100 | static inline void send_pfow_command(struct map_info *map, |
101 | unsigned long cmd_code, unsigned long adr, |
102 | unsigned long len, map_word *datum) |
103 | { |
104 | int bits_per_chip = map_bankwidth(map) * 8; |
105 | |
106 | map_write(map, CMD(cmd_code), map->pfow_base + PFOW_COMMAND_CODE); |
107 | map_write(map, CMD(adr & ((1<<bits_per_chip) - 1)), |
108 | map->pfow_base + PFOW_COMMAND_ADDRESS_L); |
109 | map_write(map, CMD(adr>>bits_per_chip), |
110 | map->pfow_base + PFOW_COMMAND_ADDRESS_H); |
111 | if (len) { |
112 | map_write(map, CMD(len & ((1<<bits_per_chip) - 1)), |
113 | map->pfow_base + PFOW_DATA_COUNT_L); |
114 | map_write(map, CMD(len>>bits_per_chip), |
115 | map->pfow_base + PFOW_DATA_COUNT_H); |
116 | } |
117 | if (datum) |
118 | map_write(map, *datum, map->pfow_base + PFOW_COMMAND_DATA); |
119 | |
120 | /* Command execution start */ |
121 | map_write(map, CMD(LPDDR_START_EXECUTION), |
122 | map->pfow_base + PFOW_COMMAND_EXECUTE); |
123 | } |
124 | #endif /* __LINUX_MTD_PFOW_H */ |
125 | |