1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7#ifndef _LINUX_NVME_H
8#define _LINUX_NVME_H
9
10#include <linux/bits.h>
11#include <linux/types.h>
12#include <linux/uuid.h>
13
14/* NQN names in commands fields specified one size */
15#define NVMF_NQN_FIELD_LEN 256
16
17/* However the max length of a qualified name is another size */
18#define NVMF_NQN_SIZE 223
19
20#define NVMF_TRSVCID_SIZE 32
21#define NVMF_TRADDR_SIZE 256
22#define NVMF_TSAS_SIZE 256
23#define NVMF_AUTH_HASH_LEN 64
24
25#define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
26
27#define NVME_RDMA_IP_PORT 4420
28
29#define NVME_NSID_ALL 0xffffffff
30
31enum nvme_subsys_type {
32 /* Referral to another discovery type target subsystem */
33 NVME_NQN_DISC = 1,
34
35 /* NVME type target subsystem */
36 NVME_NQN_NVME = 2,
37
38 /* Current discovery type target subsystem */
39 NVME_NQN_CURR = 3,
40};
41
42enum nvme_ctrl_type {
43 NVME_CTRL_IO = 1, /* I/O controller */
44 NVME_CTRL_DISC = 2, /* Discovery controller */
45 NVME_CTRL_ADMIN = 3, /* Administrative controller */
46};
47
48enum nvme_dctype {
49 NVME_DCTYPE_NOT_REPORTED = 0,
50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
52};
53
54/* Address Family codes for Discovery Log Page entry ADRFAM field */
55enum {
56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
62 NVMF_ADDR_FAMILY_MAX,
63};
64
65/* Transport Type codes for Discovery Log Page entry TRTYPE field */
66enum {
67 NVMF_TRTYPE_RDMA = 1, /* RDMA */
68 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
69 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
70 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
71 NVMF_TRTYPE_MAX,
72};
73
74/* Transport Requirements codes for Discovery Log Page entry TREQ field */
75enum {
76 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
77 NVMF_TREQ_REQUIRED = 1, /* Required */
78 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
79#define NVME_TREQ_SECURE_CHANNEL_MASK \
80 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
81
82 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
83};
84
85/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
86 * RDMA_QPTYPE field
87 */
88enum {
89 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
90 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
91};
92
93/* RDMA QP Service Type codes for Discovery Log Page entry TSAS
94 * RDMA_QPTYPE field
95 */
96enum {
97 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
98 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
99 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
100 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
101 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
102};
103
104/* RDMA Connection Management Service Type codes for Discovery Log Page
105 * entry TSAS RDMA_CMS field
106 */
107enum {
108 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
109};
110
111/* TSAS SECTYPE for TCP transport */
112enum {
113 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
114 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
115 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
116};
117
118#define NVME_AQ_DEPTH 32
119#define NVME_NR_AEN_COMMANDS 1
120#define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
121
122/*
123 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
124 * NVM-Express 1.2 specification, section 4.1.2.
125 */
126#define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
127
128enum {
129 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
130 NVME_REG_VS = 0x0008, /* Version */
131 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
132 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
133 NVME_REG_CC = 0x0014, /* Controller Configuration */
134 NVME_REG_CSTS = 0x001c, /* Controller Status */
135 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
136 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
137 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
138 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
139 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
140 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
141 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
142 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
143 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
144 * Location
145 */
146 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
147 * Space Control
148 */
149 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
150 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
151 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
152 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
153 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
154 * Buffer Size
155 */
156 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
157 * Write Throughput
158 */
159 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
160};
161
162#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
163#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
164#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
165#define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
166#define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
167#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
168#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
169#define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
170
171#define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
172#define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
173
174#define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
175#define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
176
177enum {
178 NVME_CMBSZ_SQS = 1 << 0,
179 NVME_CMBSZ_CQS = 1 << 1,
180 NVME_CMBSZ_LISTS = 1 << 2,
181 NVME_CMBSZ_RDS = 1 << 3,
182 NVME_CMBSZ_WDS = 1 << 4,
183
184 NVME_CMBSZ_SZ_SHIFT = 12,
185 NVME_CMBSZ_SZ_MASK = 0xfffff,
186
187 NVME_CMBSZ_SZU_SHIFT = 8,
188 NVME_CMBSZ_SZU_MASK = 0xf,
189};
190
191/*
192 * Submission and Completion Queue Entry Sizes for the NVM command set.
193 * (In bytes and specified as a power of two (2^n)).
194 */
195#define NVME_ADM_SQES 6
196#define NVME_NVM_IOSQES 6
197#define NVME_NVM_IOCQES 4
198
199enum {
200 NVME_CC_ENABLE = 1 << 0,
201 NVME_CC_EN_SHIFT = 0,
202 NVME_CC_CSS_SHIFT = 4,
203 NVME_CC_MPS_SHIFT = 7,
204 NVME_CC_AMS_SHIFT = 11,
205 NVME_CC_SHN_SHIFT = 14,
206 NVME_CC_IOSQES_SHIFT = 16,
207 NVME_CC_IOCQES_SHIFT = 20,
208 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
209 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
210 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
211 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
212 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
213 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
214 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
215 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
216 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
217 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
218 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
219 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
220 NVME_CC_CRIME = 1 << 24,
221};
222
223enum {
224 NVME_CSTS_RDY = 1 << 0,
225 NVME_CSTS_CFS = 1 << 1,
226 NVME_CSTS_NSSRO = 1 << 4,
227 NVME_CSTS_PP = 1 << 5,
228 NVME_CSTS_SHST_NORMAL = 0 << 2,
229 NVME_CSTS_SHST_OCCUR = 1 << 2,
230 NVME_CSTS_SHST_CMPLT = 2 << 2,
231 NVME_CSTS_SHST_MASK = 3 << 2,
232};
233
234enum {
235 NVME_CMBMSC_CRE = 1 << 0,
236 NVME_CMBMSC_CMSE = 1 << 1,
237};
238
239enum {
240 NVME_CAP_CSS_NVM = 1 << 0,
241 NVME_CAP_CSS_CSI = 1 << 6,
242};
243
244enum {
245 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
246 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
247};
248
249struct nvme_id_power_state {
250 __le16 max_power; /* centiwatts */
251 __u8 rsvd2;
252 __u8 flags;
253 __le32 entry_lat; /* microseconds */
254 __le32 exit_lat; /* microseconds */
255 __u8 read_tput;
256 __u8 read_lat;
257 __u8 write_tput;
258 __u8 write_lat;
259 __le16 idle_power;
260 __u8 idle_scale;
261 __u8 rsvd19;
262 __le16 active_power;
263 __u8 active_work_scale;
264 __u8 rsvd23[9];
265};
266
267enum {
268 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
269 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
270};
271
272enum nvme_ctrl_attr {
273 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
274 NVME_CTRL_ATTR_TBKAS = (1 << 6),
275 NVME_CTRL_ATTR_ELBAS = (1 << 15),
276};
277
278struct nvme_id_ctrl {
279 __le16 vid;
280 __le16 ssvid;
281 char sn[20];
282 char mn[40];
283 char fr[8];
284 __u8 rab;
285 __u8 ieee[3];
286 __u8 cmic;
287 __u8 mdts;
288 __le16 cntlid;
289 __le32 ver;
290 __le32 rtd3r;
291 __le32 rtd3e;
292 __le32 oaes;
293 __le32 ctratt;
294 __u8 rsvd100[11];
295 __u8 cntrltype;
296 __u8 fguid[16];
297 __le16 crdt1;
298 __le16 crdt2;
299 __le16 crdt3;
300 __u8 rsvd134[122];
301 __le16 oacs;
302 __u8 acl;
303 __u8 aerl;
304 __u8 frmw;
305 __u8 lpa;
306 __u8 elpe;
307 __u8 npss;
308 __u8 avscc;
309 __u8 apsta;
310 __le16 wctemp;
311 __le16 cctemp;
312 __le16 mtfa;
313 __le32 hmpre;
314 __le32 hmmin;
315 __u8 tnvmcap[16];
316 __u8 unvmcap[16];
317 __le32 rpmbs;
318 __le16 edstt;
319 __u8 dsto;
320 __u8 fwug;
321 __le16 kas;
322 __le16 hctma;
323 __le16 mntmt;
324 __le16 mxtmt;
325 __le32 sanicap;
326 __le32 hmminds;
327 __le16 hmmaxd;
328 __u8 rsvd338[4];
329 __u8 anatt;
330 __u8 anacap;
331 __le32 anagrpmax;
332 __le32 nanagrpid;
333 __u8 rsvd352[160];
334 __u8 sqes;
335 __u8 cqes;
336 __le16 maxcmd;
337 __le32 nn;
338 __le16 oncs;
339 __le16 fuses;
340 __u8 fna;
341 __u8 vwc;
342 __le16 awun;
343 __le16 awupf;
344 __u8 nvscc;
345 __u8 nwpc;
346 __le16 acwu;
347 __u8 rsvd534[2];
348 __le32 sgls;
349 __le32 mnan;
350 __u8 rsvd544[224];
351 char subnqn[256];
352 __u8 rsvd1024[768];
353 __le32 ioccsz;
354 __le32 iorcsz;
355 __le16 icdoff;
356 __u8 ctrattr;
357 __u8 msdbd;
358 __u8 rsvd1804[2];
359 __u8 dctype;
360 __u8 rsvd1807[241];
361 struct nvme_id_power_state psd[32];
362 __u8 vs[1024];
363};
364
365enum {
366 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
367 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
368 NVME_CTRL_CMIC_ANA = 1 << 3,
369 NVME_CTRL_ONCS_COMPARE = 1 << 0,
370 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
371 NVME_CTRL_ONCS_DSM = 1 << 2,
372 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
373 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
374 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
375 NVME_CTRL_VWC_PRESENT = 1 << 0,
376 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
377 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
378 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
379 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
380 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
381 NVME_CTRL_CTRATT_128_ID = 1 << 0,
382 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
383 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
384 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
385 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
386 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
387 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
388 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
389};
390
391struct nvme_lbaf {
392 __le16 ms;
393 __u8 ds;
394 __u8 rp;
395};
396
397struct nvme_id_ns {
398 __le64 nsze;
399 __le64 ncap;
400 __le64 nuse;
401 __u8 nsfeat;
402 __u8 nlbaf;
403 __u8 flbas;
404 __u8 mc;
405 __u8 dpc;
406 __u8 dps;
407 __u8 nmic;
408 __u8 rescap;
409 __u8 fpi;
410 __u8 dlfeat;
411 __le16 nawun;
412 __le16 nawupf;
413 __le16 nacwu;
414 __le16 nabsn;
415 __le16 nabo;
416 __le16 nabspf;
417 __le16 noiob;
418 __u8 nvmcap[16];
419 __le16 npwg;
420 __le16 npwa;
421 __le16 npdg;
422 __le16 npda;
423 __le16 nows;
424 __u8 rsvd74[18];
425 __le32 anagrpid;
426 __u8 rsvd96[3];
427 __u8 nsattr;
428 __le16 nvmsetid;
429 __le16 endgid;
430 __u8 nguid[16];
431 __u8 eui64[8];
432 struct nvme_lbaf lbaf[64];
433 __u8 vs[3712];
434};
435
436/* I/O Command Set Independent Identify Namespace Data Structure */
437struct nvme_id_ns_cs_indep {
438 __u8 nsfeat;
439 __u8 nmic;
440 __u8 rescap;
441 __u8 fpi;
442 __le32 anagrpid;
443 __u8 nsattr;
444 __u8 rsvd9;
445 __le16 nvmsetid;
446 __le16 endgid;
447 __u8 nstat;
448 __u8 rsvd15[4081];
449};
450
451struct nvme_zns_lbafe {
452 __le64 zsze;
453 __u8 zdes;
454 __u8 rsvd9[7];
455};
456
457struct nvme_id_ns_zns {
458 __le16 zoc;
459 __le16 ozcs;
460 __le32 mar;
461 __le32 mor;
462 __le32 rrl;
463 __le32 frl;
464 __u8 rsvd20[2796];
465 struct nvme_zns_lbafe lbafe[64];
466 __u8 vs[256];
467};
468
469struct nvme_id_ctrl_zns {
470 __u8 zasl;
471 __u8 rsvd1[4095];
472};
473
474struct nvme_id_ns_nvm {
475 __le64 lbstm;
476 __u8 pic;
477 __u8 rsvd9[3];
478 __le32 elbaf[64];
479 __u8 rsvd268[3828];
480};
481
482enum {
483 NVME_ID_NS_NVM_STS_MASK = 0x7f,
484 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
485 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
486};
487
488static inline __u8 nvme_elbaf_sts(__u32 elbaf)
489{
490 return elbaf & NVME_ID_NS_NVM_STS_MASK;
491}
492
493static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
494{
495 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
496}
497
498struct nvme_id_ctrl_nvm {
499 __u8 vsl;
500 __u8 wzsl;
501 __u8 wusl;
502 __u8 dmrl;
503 __le32 dmrsl;
504 __le64 dmsl;
505 __u8 rsvd16[4080];
506};
507
508enum {
509 NVME_ID_CNS_NS = 0x00,
510 NVME_ID_CNS_CTRL = 0x01,
511 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
512 NVME_ID_CNS_NS_DESC_LIST = 0x03,
513 NVME_ID_CNS_CS_NS = 0x05,
514 NVME_ID_CNS_CS_CTRL = 0x06,
515 NVME_ID_CNS_NS_CS_INDEP = 0x08,
516 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
517 NVME_ID_CNS_NS_PRESENT = 0x11,
518 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
519 NVME_ID_CNS_CTRL_LIST = 0x13,
520 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
521 NVME_ID_CNS_NS_GRANULARITY = 0x16,
522 NVME_ID_CNS_UUID_LIST = 0x17,
523};
524
525enum {
526 NVME_CSI_NVM = 0,
527 NVME_CSI_ZNS = 2,
528};
529
530enum {
531 NVME_DIR_IDENTIFY = 0x00,
532 NVME_DIR_STREAMS = 0x01,
533 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
534 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
535 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
536 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
537 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
538 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
539 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
540 NVME_DIR_ENDIR = 0x01,
541};
542
543enum {
544 NVME_NS_FEAT_THIN = 1 << 0,
545 NVME_NS_FEAT_ATOMICS = 1 << 1,
546 NVME_NS_FEAT_IO_OPT = 1 << 4,
547 NVME_NS_ATTR_RO = 1 << 0,
548 NVME_NS_FLBAS_LBA_MASK = 0xf,
549 NVME_NS_FLBAS_LBA_UMASK = 0x60,
550 NVME_NS_FLBAS_LBA_SHIFT = 1,
551 NVME_NS_FLBAS_META_EXT = 0x10,
552 NVME_NS_NMIC_SHARED = 1 << 0,
553 NVME_LBAF_RP_BEST = 0,
554 NVME_LBAF_RP_BETTER = 1,
555 NVME_LBAF_RP_GOOD = 2,
556 NVME_LBAF_RP_DEGRADED = 3,
557 NVME_NS_DPC_PI_LAST = 1 << 4,
558 NVME_NS_DPC_PI_FIRST = 1 << 3,
559 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
560 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
561 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
562 NVME_NS_DPS_PI_FIRST = 1 << 3,
563 NVME_NS_DPS_PI_MASK = 0x7,
564 NVME_NS_DPS_PI_TYPE1 = 1,
565 NVME_NS_DPS_PI_TYPE2 = 2,
566 NVME_NS_DPS_PI_TYPE3 = 3,
567};
568
569enum {
570 NVME_NSTAT_NRDY = 1 << 0,
571};
572
573enum {
574 NVME_NVM_NS_16B_GUARD = 0,
575 NVME_NVM_NS_32B_GUARD = 1,
576 NVME_NVM_NS_64B_GUARD = 2,
577};
578
579static inline __u8 nvme_lbaf_index(__u8 flbas)
580{
581 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
582 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
583}
584
585/* Identify Namespace Metadata Capabilities (MC): */
586enum {
587 NVME_MC_EXTENDED_LBA = (1 << 0),
588 NVME_MC_METADATA_PTR = (1 << 1),
589};
590
591struct nvme_ns_id_desc {
592 __u8 nidt;
593 __u8 nidl;
594 __le16 reserved;
595};
596
597#define NVME_NIDT_EUI64_LEN 8
598#define NVME_NIDT_NGUID_LEN 16
599#define NVME_NIDT_UUID_LEN 16
600#define NVME_NIDT_CSI_LEN 1
601
602enum {
603 NVME_NIDT_EUI64 = 0x01,
604 NVME_NIDT_NGUID = 0x02,
605 NVME_NIDT_UUID = 0x03,
606 NVME_NIDT_CSI = 0x04,
607};
608
609struct nvme_smart_log {
610 __u8 critical_warning;
611 __u8 temperature[2];
612 __u8 avail_spare;
613 __u8 spare_thresh;
614 __u8 percent_used;
615 __u8 endu_grp_crit_warn_sumry;
616 __u8 rsvd7[25];
617 __u8 data_units_read[16];
618 __u8 data_units_written[16];
619 __u8 host_reads[16];
620 __u8 host_writes[16];
621 __u8 ctrl_busy_time[16];
622 __u8 power_cycles[16];
623 __u8 power_on_hours[16];
624 __u8 unsafe_shutdowns[16];
625 __u8 media_errors[16];
626 __u8 num_err_log_entries[16];
627 __le32 warning_temp_time;
628 __le32 critical_comp_time;
629 __le16 temp_sensor[8];
630 __le32 thm_temp1_trans_count;
631 __le32 thm_temp2_trans_count;
632 __le32 thm_temp1_total_time;
633 __le32 thm_temp2_total_time;
634 __u8 rsvd232[280];
635};
636
637struct nvme_fw_slot_info_log {
638 __u8 afi;
639 __u8 rsvd1[7];
640 __le64 frs[7];
641 __u8 rsvd64[448];
642};
643
644enum {
645 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
646 NVME_CMD_EFFECTS_LBCC = 1 << 1,
647 NVME_CMD_EFFECTS_NCC = 1 << 2,
648 NVME_CMD_EFFECTS_NIC = 1 << 3,
649 NVME_CMD_EFFECTS_CCC = 1 << 4,
650 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
651 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
652 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
653};
654
655struct nvme_effects_log {
656 __le32 acs[256];
657 __le32 iocs[256];
658 __u8 resv[2048];
659};
660
661enum nvme_ana_state {
662 NVME_ANA_OPTIMIZED = 0x01,
663 NVME_ANA_NONOPTIMIZED = 0x02,
664 NVME_ANA_INACCESSIBLE = 0x03,
665 NVME_ANA_PERSISTENT_LOSS = 0x04,
666 NVME_ANA_CHANGE = 0x0f,
667};
668
669struct nvme_ana_group_desc {
670 __le32 grpid;
671 __le32 nnsids;
672 __le64 chgcnt;
673 __u8 state;
674 __u8 rsvd17[15];
675 __le32 nsids[];
676};
677
678/* flag for the log specific field of the ANA log */
679#define NVME_ANA_LOG_RGO (1 << 0)
680
681struct nvme_ana_rsp_hdr {
682 __le64 chgcnt;
683 __le16 ngrps;
684 __le16 rsvd10[3];
685};
686
687struct nvme_zone_descriptor {
688 __u8 zt;
689 __u8 zs;
690 __u8 za;
691 __u8 rsvd3[5];
692 __le64 zcap;
693 __le64 zslba;
694 __le64 wp;
695 __u8 rsvd32[32];
696};
697
698enum {
699 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
700};
701
702struct nvme_zone_report {
703 __le64 nr_zones;
704 __u8 resv8[56];
705 struct nvme_zone_descriptor entries[];
706};
707
708enum {
709 NVME_SMART_CRIT_SPARE = 1 << 0,
710 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
711 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
712 NVME_SMART_CRIT_MEDIA = 1 << 3,
713 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
714};
715
716enum {
717 NVME_AER_ERROR = 0,
718 NVME_AER_SMART = 1,
719 NVME_AER_NOTICE = 2,
720 NVME_AER_CSS = 6,
721 NVME_AER_VS = 7,
722};
723
724enum {
725 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
726};
727
728enum {
729 NVME_AER_NOTICE_NS_CHANGED = 0x00,
730 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
731 NVME_AER_NOTICE_ANA = 0x03,
732 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
733};
734
735enum {
736 NVME_AEN_BIT_NS_ATTR = 8,
737 NVME_AEN_BIT_FW_ACT = 9,
738 NVME_AEN_BIT_ANA_CHANGE = 11,
739 NVME_AEN_BIT_DISC_CHANGE = 31,
740};
741
742enum {
743 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
744 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
745 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
746 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
747};
748
749struct nvme_lba_range_type {
750 __u8 type;
751 __u8 attributes;
752 __u8 rsvd2[14];
753 __le64 slba;
754 __le64 nlb;
755 __u8 guid[16];
756 __u8 rsvd48[16];
757};
758
759enum {
760 NVME_LBART_TYPE_FS = 0x01,
761 NVME_LBART_TYPE_RAID = 0x02,
762 NVME_LBART_TYPE_CACHE = 0x03,
763 NVME_LBART_TYPE_SWAP = 0x04,
764
765 NVME_LBART_ATTRIB_TEMP = 1 << 0,
766 NVME_LBART_ATTRIB_HIDE = 1 << 1,
767};
768
769enum nvme_pr_type {
770 NVME_PR_WRITE_EXCLUSIVE = 1,
771 NVME_PR_EXCLUSIVE_ACCESS = 2,
772 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3,
773 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4,
774 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5,
775 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6,
776};
777
778enum nvme_eds {
779 NVME_EXTENDED_DATA_STRUCT = 0x1,
780};
781
782struct nvme_registered_ctrl {
783 __le16 cntlid;
784 __u8 rcsts;
785 __u8 rsvd3[5];
786 __le64 hostid;
787 __le64 rkey;
788};
789
790struct nvme_reservation_status {
791 __le32 gen;
792 __u8 rtype;
793 __u8 regctl[2];
794 __u8 resv5[2];
795 __u8 ptpls;
796 __u8 resv10[14];
797 struct nvme_registered_ctrl regctl_ds[];
798};
799
800struct nvme_registered_ctrl_ext {
801 __le16 cntlid;
802 __u8 rcsts;
803 __u8 rsvd3[5];
804 __le64 rkey;
805 __u8 hostid[16];
806 __u8 rsvd32[32];
807};
808
809struct nvme_reservation_status_ext {
810 __le32 gen;
811 __u8 rtype;
812 __u8 regctl[2];
813 __u8 resv5[2];
814 __u8 ptpls;
815 __u8 resv10[14];
816 __u8 rsvd24[40];
817 struct nvme_registered_ctrl_ext regctl_eds[];
818};
819
820enum nvme_async_event_type {
821 NVME_AER_TYPE_ERROR = 0,
822 NVME_AER_TYPE_SMART = 1,
823 NVME_AER_TYPE_NOTICE = 2,
824};
825
826/* I/O commands */
827
828enum nvme_opcode {
829 nvme_cmd_flush = 0x00,
830 nvme_cmd_write = 0x01,
831 nvme_cmd_read = 0x02,
832 nvme_cmd_write_uncor = 0x04,
833 nvme_cmd_compare = 0x05,
834 nvme_cmd_write_zeroes = 0x08,
835 nvme_cmd_dsm = 0x09,
836 nvme_cmd_verify = 0x0c,
837 nvme_cmd_resv_register = 0x0d,
838 nvme_cmd_resv_report = 0x0e,
839 nvme_cmd_resv_acquire = 0x11,
840 nvme_cmd_resv_release = 0x15,
841 nvme_cmd_zone_mgmt_send = 0x79,
842 nvme_cmd_zone_mgmt_recv = 0x7a,
843 nvme_cmd_zone_append = 0x7d,
844 nvme_cmd_vendor_start = 0x80,
845};
846
847#define nvme_opcode_name(opcode) { opcode, #opcode }
848#define show_nvm_opcode_name(val) \
849 __print_symbolic(val, \
850 nvme_opcode_name(nvme_cmd_flush), \
851 nvme_opcode_name(nvme_cmd_write), \
852 nvme_opcode_name(nvme_cmd_read), \
853 nvme_opcode_name(nvme_cmd_write_uncor), \
854 nvme_opcode_name(nvme_cmd_compare), \
855 nvme_opcode_name(nvme_cmd_write_zeroes), \
856 nvme_opcode_name(nvme_cmd_dsm), \
857 nvme_opcode_name(nvme_cmd_verify), \
858 nvme_opcode_name(nvme_cmd_resv_register), \
859 nvme_opcode_name(nvme_cmd_resv_report), \
860 nvme_opcode_name(nvme_cmd_resv_acquire), \
861 nvme_opcode_name(nvme_cmd_resv_release), \
862 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
863 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
864 nvme_opcode_name(nvme_cmd_zone_append))
865
866
867
868/*
869 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
870 *
871 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
872 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
873 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
874 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
875 * request subtype
876 */
877enum {
878 NVME_SGL_FMT_ADDRESS = 0x00,
879 NVME_SGL_FMT_OFFSET = 0x01,
880 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
881 NVME_SGL_FMT_INVALIDATE = 0x0f,
882};
883
884/*
885 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
886 *
887 * For struct nvme_sgl_desc:
888 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
889 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
890 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
891 *
892 * For struct nvme_keyed_sgl_desc:
893 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
894 *
895 * Transport-specific SGL types:
896 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
897 */
898enum {
899 NVME_SGL_FMT_DATA_DESC = 0x00,
900 NVME_SGL_FMT_SEG_DESC = 0x02,
901 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
902 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
903 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
904};
905
906struct nvme_sgl_desc {
907 __le64 addr;
908 __le32 length;
909 __u8 rsvd[3];
910 __u8 type;
911};
912
913struct nvme_keyed_sgl_desc {
914 __le64 addr;
915 __u8 length[3];
916 __u8 key[4];
917 __u8 type;
918};
919
920union nvme_data_ptr {
921 struct {
922 __le64 prp1;
923 __le64 prp2;
924 };
925 struct nvme_sgl_desc sgl;
926 struct nvme_keyed_sgl_desc ksgl;
927};
928
929/*
930 * Lowest two bits of our flags field (FUSE field in the spec):
931 *
932 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
933 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
934 *
935 * Highest two bits in our flags field (PSDT field in the spec):
936 *
937 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
938 * If used, MPTR contains addr of single physical buffer (byte aligned).
939 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
940 * If used, MPTR contains an address of an SGL segment containing
941 * exactly 1 SGL descriptor (qword aligned).
942 */
943enum {
944 NVME_CMD_FUSE_FIRST = (1 << 0),
945 NVME_CMD_FUSE_SECOND = (1 << 1),
946
947 NVME_CMD_SGL_METABUF = (1 << 6),
948 NVME_CMD_SGL_METASEG = (1 << 7),
949 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
950};
951
952struct nvme_common_command {
953 __u8 opcode;
954 __u8 flags;
955 __u16 command_id;
956 __le32 nsid;
957 __le32 cdw2[2];
958 __le64 metadata;
959 union nvme_data_ptr dptr;
960 struct_group(cdws,
961 __le32 cdw10;
962 __le32 cdw11;
963 __le32 cdw12;
964 __le32 cdw13;
965 __le32 cdw14;
966 __le32 cdw15;
967 );
968};
969
970struct nvme_rw_command {
971 __u8 opcode;
972 __u8 flags;
973 __u16 command_id;
974 __le32 nsid;
975 __le32 cdw2;
976 __le32 cdw3;
977 __le64 metadata;
978 union nvme_data_ptr dptr;
979 __le64 slba;
980 __le16 length;
981 __le16 control;
982 __le32 dsmgmt;
983 __le32 reftag;
984 __le16 apptag;
985 __le16 appmask;
986};
987
988enum {
989 NVME_RW_LR = 1 << 15,
990 NVME_RW_FUA = 1 << 14,
991 NVME_RW_APPEND_PIREMAP = 1 << 9,
992 NVME_RW_DSM_FREQ_UNSPEC = 0,
993 NVME_RW_DSM_FREQ_TYPICAL = 1,
994 NVME_RW_DSM_FREQ_RARE = 2,
995 NVME_RW_DSM_FREQ_READS = 3,
996 NVME_RW_DSM_FREQ_WRITES = 4,
997 NVME_RW_DSM_FREQ_RW = 5,
998 NVME_RW_DSM_FREQ_ONCE = 6,
999 NVME_RW_DSM_FREQ_PREFETCH = 7,
1000 NVME_RW_DSM_FREQ_TEMP = 8,
1001 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
1002 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
1003 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
1004 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
1005 NVME_RW_DSM_SEQ_REQ = 1 << 6,
1006 NVME_RW_DSM_COMPRESSED = 1 << 7,
1007 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
1008 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
1009 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
1010 NVME_RW_PRINFO_PRACT = 1 << 13,
1011 NVME_RW_DTYPE_STREAMS = 1 << 4,
1012 NVME_WZ_DEAC = 1 << 9,
1013};
1014
1015struct nvme_dsm_cmd {
1016 __u8 opcode;
1017 __u8 flags;
1018 __u16 command_id;
1019 __le32 nsid;
1020 __u64 rsvd2[2];
1021 union nvme_data_ptr dptr;
1022 __le32 nr;
1023 __le32 attributes;
1024 __u32 rsvd12[4];
1025};
1026
1027enum {
1028 NVME_DSMGMT_IDR = 1 << 0,
1029 NVME_DSMGMT_IDW = 1 << 1,
1030 NVME_DSMGMT_AD = 1 << 2,
1031};
1032
1033#define NVME_DSM_MAX_RANGES 256
1034
1035struct nvme_dsm_range {
1036 __le32 cattr;
1037 __le32 nlb;
1038 __le64 slba;
1039};
1040
1041struct nvme_write_zeroes_cmd {
1042 __u8 opcode;
1043 __u8 flags;
1044 __u16 command_id;
1045 __le32 nsid;
1046 __u64 rsvd2;
1047 __le64 metadata;
1048 union nvme_data_ptr dptr;
1049 __le64 slba;
1050 __le16 length;
1051 __le16 control;
1052 __le32 dsmgmt;
1053 __le32 reftag;
1054 __le16 apptag;
1055 __le16 appmask;
1056};
1057
1058enum nvme_zone_mgmt_action {
1059 NVME_ZONE_CLOSE = 0x1,
1060 NVME_ZONE_FINISH = 0x2,
1061 NVME_ZONE_OPEN = 0x3,
1062 NVME_ZONE_RESET = 0x4,
1063 NVME_ZONE_OFFLINE = 0x5,
1064 NVME_ZONE_SET_DESC_EXT = 0x10,
1065};
1066
1067struct nvme_zone_mgmt_send_cmd {
1068 __u8 opcode;
1069 __u8 flags;
1070 __u16 command_id;
1071 __le32 nsid;
1072 __le32 cdw2[2];
1073 __le64 metadata;
1074 union nvme_data_ptr dptr;
1075 __le64 slba;
1076 __le32 cdw12;
1077 __u8 zsa;
1078 __u8 select_all;
1079 __u8 rsvd13[2];
1080 __le32 cdw14[2];
1081};
1082
1083struct nvme_zone_mgmt_recv_cmd {
1084 __u8 opcode;
1085 __u8 flags;
1086 __u16 command_id;
1087 __le32 nsid;
1088 __le64 rsvd2[2];
1089 union nvme_data_ptr dptr;
1090 __le64 slba;
1091 __le32 numd;
1092 __u8 zra;
1093 __u8 zrasf;
1094 __u8 pr;
1095 __u8 rsvd13;
1096 __le32 cdw14[2];
1097};
1098
1099enum {
1100 NVME_ZRA_ZONE_REPORT = 0,
1101 NVME_ZRASF_ZONE_REPORT_ALL = 0,
1102 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1103 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1104 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1105 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1106 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1107 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1108 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
1109 NVME_REPORT_ZONE_PARTIAL = 1,
1110};
1111
1112/* Features */
1113
1114enum {
1115 NVME_TEMP_THRESH_MASK = 0xffff,
1116 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1117 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1118};
1119
1120struct nvme_feat_auto_pst {
1121 __le64 entries[32];
1122};
1123
1124enum {
1125 NVME_HOST_MEM_ENABLE = (1 << 0),
1126 NVME_HOST_MEM_RETURN = (1 << 1),
1127};
1128
1129struct nvme_feat_host_behavior {
1130 __u8 acre;
1131 __u8 etdas;
1132 __u8 lbafee;
1133 __u8 resv1[509];
1134};
1135
1136enum {
1137 NVME_ENABLE_ACRE = 1,
1138 NVME_ENABLE_LBAFEE = 1,
1139};
1140
1141/* Admin commands */
1142
1143enum nvme_admin_opcode {
1144 nvme_admin_delete_sq = 0x00,
1145 nvme_admin_create_sq = 0x01,
1146 nvme_admin_get_log_page = 0x02,
1147 nvme_admin_delete_cq = 0x04,
1148 nvme_admin_create_cq = 0x05,
1149 nvme_admin_identify = 0x06,
1150 nvme_admin_abort_cmd = 0x08,
1151 nvme_admin_set_features = 0x09,
1152 nvme_admin_get_features = 0x0a,
1153 nvme_admin_async_event = 0x0c,
1154 nvme_admin_ns_mgmt = 0x0d,
1155 nvme_admin_activate_fw = 0x10,
1156 nvme_admin_download_fw = 0x11,
1157 nvme_admin_dev_self_test = 0x14,
1158 nvme_admin_ns_attach = 0x15,
1159 nvme_admin_keep_alive = 0x18,
1160 nvme_admin_directive_send = 0x19,
1161 nvme_admin_directive_recv = 0x1a,
1162 nvme_admin_virtual_mgmt = 0x1c,
1163 nvme_admin_nvme_mi_send = 0x1d,
1164 nvme_admin_nvme_mi_recv = 0x1e,
1165 nvme_admin_dbbuf = 0x7C,
1166 nvme_admin_format_nvm = 0x80,
1167 nvme_admin_security_send = 0x81,
1168 nvme_admin_security_recv = 0x82,
1169 nvme_admin_sanitize_nvm = 0x84,
1170 nvme_admin_get_lba_status = 0x86,
1171 nvme_admin_vendor_start = 0xC0,
1172};
1173
1174#define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1175#define show_admin_opcode_name(val) \
1176 __print_symbolic(val, \
1177 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1178 nvme_admin_opcode_name(nvme_admin_create_sq), \
1179 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1180 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1181 nvme_admin_opcode_name(nvme_admin_create_cq), \
1182 nvme_admin_opcode_name(nvme_admin_identify), \
1183 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1184 nvme_admin_opcode_name(nvme_admin_set_features), \
1185 nvme_admin_opcode_name(nvme_admin_get_features), \
1186 nvme_admin_opcode_name(nvme_admin_async_event), \
1187 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1188 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1189 nvme_admin_opcode_name(nvme_admin_download_fw), \
1190 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
1191 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1192 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1193 nvme_admin_opcode_name(nvme_admin_directive_send), \
1194 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1195 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1196 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1197 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
1198 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1199 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1200 nvme_admin_opcode_name(nvme_admin_security_send), \
1201 nvme_admin_opcode_name(nvme_admin_security_recv), \
1202 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1203 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1204
1205enum {
1206 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1207 NVME_CQ_IRQ_ENABLED = (1 << 1),
1208 NVME_SQ_PRIO_URGENT = (0 << 1),
1209 NVME_SQ_PRIO_HIGH = (1 << 1),
1210 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1211 NVME_SQ_PRIO_LOW = (3 << 1),
1212 NVME_FEAT_ARBITRATION = 0x01,
1213 NVME_FEAT_POWER_MGMT = 0x02,
1214 NVME_FEAT_LBA_RANGE = 0x03,
1215 NVME_FEAT_TEMP_THRESH = 0x04,
1216 NVME_FEAT_ERR_RECOVERY = 0x05,
1217 NVME_FEAT_VOLATILE_WC = 0x06,
1218 NVME_FEAT_NUM_QUEUES = 0x07,
1219 NVME_FEAT_IRQ_COALESCE = 0x08,
1220 NVME_FEAT_IRQ_CONFIG = 0x09,
1221 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1222 NVME_FEAT_ASYNC_EVENT = 0x0b,
1223 NVME_FEAT_AUTO_PST = 0x0c,
1224 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1225 NVME_FEAT_TIMESTAMP = 0x0e,
1226 NVME_FEAT_KATO = 0x0f,
1227 NVME_FEAT_HCTM = 0x10,
1228 NVME_FEAT_NOPSC = 0x11,
1229 NVME_FEAT_RRL = 0x12,
1230 NVME_FEAT_PLM_CONFIG = 0x13,
1231 NVME_FEAT_PLM_WINDOW = 0x14,
1232 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1233 NVME_FEAT_SANITIZE = 0x17,
1234 NVME_FEAT_SW_PROGRESS = 0x80,
1235 NVME_FEAT_HOST_ID = 0x81,
1236 NVME_FEAT_RESV_MASK = 0x82,
1237 NVME_FEAT_RESV_PERSIST = 0x83,
1238 NVME_FEAT_WRITE_PROTECT = 0x84,
1239 NVME_FEAT_VENDOR_START = 0xC0,
1240 NVME_FEAT_VENDOR_END = 0xFF,
1241 NVME_LOG_ERROR = 0x01,
1242 NVME_LOG_SMART = 0x02,
1243 NVME_LOG_FW_SLOT = 0x03,
1244 NVME_LOG_CHANGED_NS = 0x04,
1245 NVME_LOG_CMD_EFFECTS = 0x05,
1246 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1247 NVME_LOG_TELEMETRY_HOST = 0x07,
1248 NVME_LOG_TELEMETRY_CTRL = 0x08,
1249 NVME_LOG_ENDURANCE_GROUP = 0x09,
1250 NVME_LOG_ANA = 0x0c,
1251 NVME_LOG_DISC = 0x70,
1252 NVME_LOG_RESERVATION = 0x80,
1253 NVME_FWACT_REPL = (0 << 3),
1254 NVME_FWACT_REPL_ACTV = (1 << 3),
1255 NVME_FWACT_ACTV = (2 << 3),
1256};
1257
1258/* NVMe Namespace Write Protect State */
1259enum {
1260 NVME_NS_NO_WRITE_PROTECT = 0,
1261 NVME_NS_WRITE_PROTECT,
1262 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1263 NVME_NS_WRITE_PROTECT_PERMANENT,
1264};
1265
1266#define NVME_MAX_CHANGED_NAMESPACES 1024
1267
1268struct nvme_identify {
1269 __u8 opcode;
1270 __u8 flags;
1271 __u16 command_id;
1272 __le32 nsid;
1273 __u64 rsvd2[2];
1274 union nvme_data_ptr dptr;
1275 __u8 cns;
1276 __u8 rsvd3;
1277 __le16 ctrlid;
1278 __u8 rsvd11[3];
1279 __u8 csi;
1280 __u32 rsvd12[4];
1281};
1282
1283#define NVME_IDENTIFY_DATA_SIZE 4096
1284
1285struct nvme_features {
1286 __u8 opcode;
1287 __u8 flags;
1288 __u16 command_id;
1289 __le32 nsid;
1290 __u64 rsvd2[2];
1291 union nvme_data_ptr dptr;
1292 __le32 fid;
1293 __le32 dword11;
1294 __le32 dword12;
1295 __le32 dword13;
1296 __le32 dword14;
1297 __le32 dword15;
1298};
1299
1300struct nvme_host_mem_buf_desc {
1301 __le64 addr;
1302 __le32 size;
1303 __u32 rsvd;
1304};
1305
1306struct nvme_create_cq {
1307 __u8 opcode;
1308 __u8 flags;
1309 __u16 command_id;
1310 __u32 rsvd1[5];
1311 __le64 prp1;
1312 __u64 rsvd8;
1313 __le16 cqid;
1314 __le16 qsize;
1315 __le16 cq_flags;
1316 __le16 irq_vector;
1317 __u32 rsvd12[4];
1318};
1319
1320struct nvme_create_sq {
1321 __u8 opcode;
1322 __u8 flags;
1323 __u16 command_id;
1324 __u32 rsvd1[5];
1325 __le64 prp1;
1326 __u64 rsvd8;
1327 __le16 sqid;
1328 __le16 qsize;
1329 __le16 sq_flags;
1330 __le16 cqid;
1331 __u32 rsvd12[4];
1332};
1333
1334struct nvme_delete_queue {
1335 __u8 opcode;
1336 __u8 flags;
1337 __u16 command_id;
1338 __u32 rsvd1[9];
1339 __le16 qid;
1340 __u16 rsvd10;
1341 __u32 rsvd11[5];
1342};
1343
1344struct nvme_abort_cmd {
1345 __u8 opcode;
1346 __u8 flags;
1347 __u16 command_id;
1348 __u32 rsvd1[9];
1349 __le16 sqid;
1350 __u16 cid;
1351 __u32 rsvd11[5];
1352};
1353
1354struct nvme_download_firmware {
1355 __u8 opcode;
1356 __u8 flags;
1357 __u16 command_id;
1358 __u32 rsvd1[5];
1359 union nvme_data_ptr dptr;
1360 __le32 numd;
1361 __le32 offset;
1362 __u32 rsvd12[4];
1363};
1364
1365struct nvme_format_cmd {
1366 __u8 opcode;
1367 __u8 flags;
1368 __u16 command_id;
1369 __le32 nsid;
1370 __u64 rsvd2[4];
1371 __le32 cdw10;
1372 __u32 rsvd11[5];
1373};
1374
1375struct nvme_get_log_page_command {
1376 __u8 opcode;
1377 __u8 flags;
1378 __u16 command_id;
1379 __le32 nsid;
1380 __u64 rsvd2[2];
1381 union nvme_data_ptr dptr;
1382 __u8 lid;
1383 __u8 lsp; /* upper 4 bits reserved */
1384 __le16 numdl;
1385 __le16 numdu;
1386 __u16 rsvd11;
1387 union {
1388 struct {
1389 __le32 lpol;
1390 __le32 lpou;
1391 };
1392 __le64 lpo;
1393 };
1394 __u8 rsvd14[3];
1395 __u8 csi;
1396 __u32 rsvd15;
1397};
1398
1399struct nvme_directive_cmd {
1400 __u8 opcode;
1401 __u8 flags;
1402 __u16 command_id;
1403 __le32 nsid;
1404 __u64 rsvd2[2];
1405 union nvme_data_ptr dptr;
1406 __le32 numd;
1407 __u8 doper;
1408 __u8 dtype;
1409 __le16 dspec;
1410 __u8 endir;
1411 __u8 tdtype;
1412 __u16 rsvd15;
1413
1414 __u32 rsvd16[3];
1415};
1416
1417/*
1418 * Fabrics subcommands.
1419 */
1420enum nvmf_fabrics_opcode {
1421 nvme_fabrics_command = 0x7f,
1422};
1423
1424enum nvmf_capsule_command {
1425 nvme_fabrics_type_property_set = 0x00,
1426 nvme_fabrics_type_connect = 0x01,
1427 nvme_fabrics_type_property_get = 0x04,
1428 nvme_fabrics_type_auth_send = 0x05,
1429 nvme_fabrics_type_auth_receive = 0x06,
1430};
1431
1432#define nvme_fabrics_type_name(type) { type, #type }
1433#define show_fabrics_type_name(type) \
1434 __print_symbolic(type, \
1435 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1436 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1437 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1438 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1439 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1440
1441/*
1442 * If not fabrics command, fctype will be ignored.
1443 */
1444#define show_opcode_name(qid, opcode, fctype) \
1445 ((opcode) == nvme_fabrics_command ? \
1446 show_fabrics_type_name(fctype) : \
1447 ((qid) ? \
1448 show_nvm_opcode_name(opcode) : \
1449 show_admin_opcode_name(opcode)))
1450
1451struct nvmf_common_command {
1452 __u8 opcode;
1453 __u8 resv1;
1454 __u16 command_id;
1455 __u8 fctype;
1456 __u8 resv2[35];
1457 __u8 ts[24];
1458};
1459
1460/*
1461 * The legal cntlid range a NVMe Target will provide.
1462 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1463 * Devices based on earlier specs did not have the subsystem concept;
1464 * therefore, those devices had their cntlid value set to 0 as a result.
1465 */
1466#define NVME_CNTLID_MIN 1
1467#define NVME_CNTLID_MAX 0xffef
1468#define NVME_CNTLID_DYNAMIC 0xffff
1469
1470#define MAX_DISC_LOGS 255
1471
1472/* Discovery log page entry flags (EFLAGS): */
1473enum {
1474 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1475 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1476};
1477
1478/* Discovery log page entry */
1479struct nvmf_disc_rsp_page_entry {
1480 __u8 trtype;
1481 __u8 adrfam;
1482 __u8 subtype;
1483 __u8 treq;
1484 __le16 portid;
1485 __le16 cntlid;
1486 __le16 asqsz;
1487 __le16 eflags;
1488 __u8 resv10[20];
1489 char trsvcid[NVMF_TRSVCID_SIZE];
1490 __u8 resv64[192];
1491 char subnqn[NVMF_NQN_FIELD_LEN];
1492 char traddr[NVMF_TRADDR_SIZE];
1493 union tsas {
1494 char common[NVMF_TSAS_SIZE];
1495 struct rdma {
1496 __u8 qptype;
1497 __u8 prtype;
1498 __u8 cms;
1499 __u8 resv3[5];
1500 __u16 pkey;
1501 __u8 resv10[246];
1502 } rdma;
1503 struct tcp {
1504 __u8 sectype;
1505 } tcp;
1506 } tsas;
1507};
1508
1509/* Discovery log page header */
1510struct nvmf_disc_rsp_page_hdr {
1511 __le64 genctr;
1512 __le64 numrec;
1513 __le16 recfmt;
1514 __u8 resv14[1006];
1515 struct nvmf_disc_rsp_page_entry entries[];
1516};
1517
1518enum {
1519 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1520};
1521
1522struct nvmf_connect_command {
1523 __u8 opcode;
1524 __u8 resv1;
1525 __u16 command_id;
1526 __u8 fctype;
1527 __u8 resv2[19];
1528 union nvme_data_ptr dptr;
1529 __le16 recfmt;
1530 __le16 qid;
1531 __le16 sqsize;
1532 __u8 cattr;
1533 __u8 resv3;
1534 __le32 kato;
1535 __u8 resv4[12];
1536};
1537
1538enum {
1539 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1540 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
1541};
1542
1543struct nvmf_connect_data {
1544 uuid_t hostid;
1545 __le16 cntlid;
1546 char resv4[238];
1547 char subsysnqn[NVMF_NQN_FIELD_LEN];
1548 char hostnqn[NVMF_NQN_FIELD_LEN];
1549 char resv5[256];
1550};
1551
1552struct nvmf_property_set_command {
1553 __u8 opcode;
1554 __u8 resv1;
1555 __u16 command_id;
1556 __u8 fctype;
1557 __u8 resv2[35];
1558 __u8 attrib;
1559 __u8 resv3[3];
1560 __le32 offset;
1561 __le64 value;
1562 __u8 resv4[8];
1563};
1564
1565struct nvmf_property_get_command {
1566 __u8 opcode;
1567 __u8 resv1;
1568 __u16 command_id;
1569 __u8 fctype;
1570 __u8 resv2[35];
1571 __u8 attrib;
1572 __u8 resv3[3];
1573 __le32 offset;
1574 __u8 resv4[16];
1575};
1576
1577struct nvmf_auth_common_command {
1578 __u8 opcode;
1579 __u8 resv1;
1580 __u16 command_id;
1581 __u8 fctype;
1582 __u8 resv2[19];
1583 union nvme_data_ptr dptr;
1584 __u8 resv3;
1585 __u8 spsp0;
1586 __u8 spsp1;
1587 __u8 secp;
1588 __le32 al_tl;
1589 __u8 resv4[16];
1590};
1591
1592struct nvmf_auth_send_command {
1593 __u8 opcode;
1594 __u8 resv1;
1595 __u16 command_id;
1596 __u8 fctype;
1597 __u8 resv2[19];
1598 union nvme_data_ptr dptr;
1599 __u8 resv3;
1600 __u8 spsp0;
1601 __u8 spsp1;
1602 __u8 secp;
1603 __le32 tl;
1604 __u8 resv4[16];
1605};
1606
1607struct nvmf_auth_receive_command {
1608 __u8 opcode;
1609 __u8 resv1;
1610 __u16 command_id;
1611 __u8 fctype;
1612 __u8 resv2[19];
1613 union nvme_data_ptr dptr;
1614 __u8 resv3;
1615 __u8 spsp0;
1616 __u8 spsp1;
1617 __u8 secp;
1618 __le32 al;
1619 __u8 resv4[16];
1620};
1621
1622/* Value for secp */
1623enum {
1624 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1625};
1626
1627/* Defined value for auth_type */
1628enum {
1629 NVME_AUTH_COMMON_MESSAGES = 0x00,
1630 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1631};
1632
1633/* Defined messages for auth_id */
1634enum {
1635 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1636 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1637 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1638 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1639 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1640 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1641 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1642};
1643
1644struct nvmf_auth_dhchap_protocol_descriptor {
1645 __u8 authid;
1646 __u8 rsvd;
1647 __u8 halen;
1648 __u8 dhlen;
1649 __u8 idlist[60];
1650};
1651
1652enum {
1653 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1654};
1655
1656/* Defined hash functions for DH-HMAC-CHAP authentication */
1657enum {
1658 NVME_AUTH_HASH_SHA256 = 0x01,
1659 NVME_AUTH_HASH_SHA384 = 0x02,
1660 NVME_AUTH_HASH_SHA512 = 0x03,
1661 NVME_AUTH_HASH_INVALID = 0xff,
1662};
1663
1664/* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1665enum {
1666 NVME_AUTH_DHGROUP_NULL = 0x00,
1667 NVME_AUTH_DHGROUP_2048 = 0x01,
1668 NVME_AUTH_DHGROUP_3072 = 0x02,
1669 NVME_AUTH_DHGROUP_4096 = 0x03,
1670 NVME_AUTH_DHGROUP_6144 = 0x04,
1671 NVME_AUTH_DHGROUP_8192 = 0x05,
1672 NVME_AUTH_DHGROUP_INVALID = 0xff,
1673};
1674
1675union nvmf_auth_protocol {
1676 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1677};
1678
1679struct nvmf_auth_dhchap_negotiate_data {
1680 __u8 auth_type;
1681 __u8 auth_id;
1682 __le16 rsvd;
1683 __le16 t_id;
1684 __u8 sc_c;
1685 __u8 napd;
1686 union nvmf_auth_protocol auth_protocol[];
1687};
1688
1689struct nvmf_auth_dhchap_challenge_data {
1690 __u8 auth_type;
1691 __u8 auth_id;
1692 __u16 rsvd1;
1693 __le16 t_id;
1694 __u8 hl;
1695 __u8 rsvd2;
1696 __u8 hashid;
1697 __u8 dhgid;
1698 __le16 dhvlen;
1699 __le32 seqnum;
1700 /* 'hl' bytes of challenge value */
1701 __u8 cval[];
1702 /* followed by 'dhvlen' bytes of DH value */
1703};
1704
1705struct nvmf_auth_dhchap_reply_data {
1706 __u8 auth_type;
1707 __u8 auth_id;
1708 __le16 rsvd1;
1709 __le16 t_id;
1710 __u8 hl;
1711 __u8 rsvd2;
1712 __u8 cvalid;
1713 __u8 rsvd3;
1714 __le16 dhvlen;
1715 __le32 seqnum;
1716 /* 'hl' bytes of response data */
1717 __u8 rval[];
1718 /* followed by 'hl' bytes of Challenge value */
1719 /* followed by 'dhvlen' bytes of DH value */
1720};
1721
1722enum {
1723 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1724};
1725
1726struct nvmf_auth_dhchap_success1_data {
1727 __u8 auth_type;
1728 __u8 auth_id;
1729 __le16 rsvd1;
1730 __le16 t_id;
1731 __u8 hl;
1732 __u8 rsvd2;
1733 __u8 rvalid;
1734 __u8 rsvd3[7];
1735 /* 'hl' bytes of response value if 'rvalid' is set */
1736 __u8 rval[];
1737};
1738
1739struct nvmf_auth_dhchap_success2_data {
1740 __u8 auth_type;
1741 __u8 auth_id;
1742 __le16 rsvd1;
1743 __le16 t_id;
1744 __u8 rsvd2[10];
1745};
1746
1747struct nvmf_auth_dhchap_failure_data {
1748 __u8 auth_type;
1749 __u8 auth_id;
1750 __le16 rsvd1;
1751 __le16 t_id;
1752 __u8 rescode;
1753 __u8 rescode_exp;
1754};
1755
1756enum {
1757 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1758};
1759
1760enum {
1761 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1762 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1763 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1764 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1765 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1766 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1767 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1768};
1769
1770
1771struct nvme_dbbuf {
1772 __u8 opcode;
1773 __u8 flags;
1774 __u16 command_id;
1775 __u32 rsvd1[5];
1776 __le64 prp1;
1777 __le64 prp2;
1778 __u32 rsvd12[6];
1779};
1780
1781struct streams_directive_params {
1782 __le16 msl;
1783 __le16 nssa;
1784 __le16 nsso;
1785 __u8 rsvd[10];
1786 __le32 sws;
1787 __le16 sgs;
1788 __le16 nsa;
1789 __le16 nso;
1790 __u8 rsvd2[6];
1791};
1792
1793struct nvme_command {
1794 union {
1795 struct nvme_common_command common;
1796 struct nvme_rw_command rw;
1797 struct nvme_identify identify;
1798 struct nvme_features features;
1799 struct nvme_create_cq create_cq;
1800 struct nvme_create_sq create_sq;
1801 struct nvme_delete_queue delete_queue;
1802 struct nvme_download_firmware dlfw;
1803 struct nvme_format_cmd format;
1804 struct nvme_dsm_cmd dsm;
1805 struct nvme_write_zeroes_cmd write_zeroes;
1806 struct nvme_zone_mgmt_send_cmd zms;
1807 struct nvme_zone_mgmt_recv_cmd zmr;
1808 struct nvme_abort_cmd abort;
1809 struct nvme_get_log_page_command get_log_page;
1810 struct nvmf_common_command fabrics;
1811 struct nvmf_connect_command connect;
1812 struct nvmf_property_set_command prop_set;
1813 struct nvmf_property_get_command prop_get;
1814 struct nvmf_auth_common_command auth_common;
1815 struct nvmf_auth_send_command auth_send;
1816 struct nvmf_auth_receive_command auth_receive;
1817 struct nvme_dbbuf dbbuf;
1818 struct nvme_directive_cmd directive;
1819 };
1820};
1821
1822static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1823{
1824 return cmd->common.opcode == nvme_fabrics_command;
1825}
1826
1827struct nvme_error_slot {
1828 __le64 error_count;
1829 __le16 sqid;
1830 __le16 cmdid;
1831 __le16 status_field;
1832 __le16 param_error_location;
1833 __le64 lba;
1834 __le32 nsid;
1835 __u8 vs;
1836 __u8 resv[3];
1837 __le64 cs;
1838 __u8 resv2[24];
1839};
1840
1841static inline bool nvme_is_write(struct nvme_command *cmd)
1842{
1843 /*
1844 * What a mess...
1845 *
1846 * Why can't we simply have a Fabrics In and Fabrics out command?
1847 */
1848 if (unlikely(nvme_is_fabrics(cmd)))
1849 return cmd->fabrics.fctype & 1;
1850 return cmd->common.opcode & 1;
1851}
1852
1853enum {
1854 /*
1855 * Generic Command Status:
1856 */
1857 NVME_SC_SUCCESS = 0x0,
1858 NVME_SC_INVALID_OPCODE = 0x1,
1859 NVME_SC_INVALID_FIELD = 0x2,
1860 NVME_SC_CMDID_CONFLICT = 0x3,
1861 NVME_SC_DATA_XFER_ERROR = 0x4,
1862 NVME_SC_POWER_LOSS = 0x5,
1863 NVME_SC_INTERNAL = 0x6,
1864 NVME_SC_ABORT_REQ = 0x7,
1865 NVME_SC_ABORT_QUEUE = 0x8,
1866 NVME_SC_FUSED_FAIL = 0x9,
1867 NVME_SC_FUSED_MISSING = 0xa,
1868 NVME_SC_INVALID_NS = 0xb,
1869 NVME_SC_CMD_SEQ_ERROR = 0xc,
1870 NVME_SC_SGL_INVALID_LAST = 0xd,
1871 NVME_SC_SGL_INVALID_COUNT = 0xe,
1872 NVME_SC_SGL_INVALID_DATA = 0xf,
1873 NVME_SC_SGL_INVALID_METADATA = 0x10,
1874 NVME_SC_SGL_INVALID_TYPE = 0x11,
1875 NVME_SC_CMB_INVALID_USE = 0x12,
1876 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1877 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1878 NVME_SC_OP_DENIED = 0x15,
1879 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1880 NVME_SC_RESERVED = 0x17,
1881 NVME_SC_HOST_ID_INCONSIST = 0x18,
1882 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1883 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1884 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1885 NVME_SC_SANITIZE_FAILED = 0x1C,
1886 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1887 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1888 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1889 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1890 NVME_SC_CMD_INTERRUPTED = 0x21,
1891 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1892 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1893 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1894
1895 NVME_SC_LBA_RANGE = 0x80,
1896 NVME_SC_CAP_EXCEEDED = 0x81,
1897 NVME_SC_NS_NOT_READY = 0x82,
1898 NVME_SC_RESERVATION_CONFLICT = 0x83,
1899 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1900
1901 /*
1902 * Command Specific Status:
1903 */
1904 NVME_SC_CQ_INVALID = 0x100,
1905 NVME_SC_QID_INVALID = 0x101,
1906 NVME_SC_QUEUE_SIZE = 0x102,
1907 NVME_SC_ABORT_LIMIT = 0x103,
1908 NVME_SC_ABORT_MISSING = 0x104,
1909 NVME_SC_ASYNC_LIMIT = 0x105,
1910 NVME_SC_FIRMWARE_SLOT = 0x106,
1911 NVME_SC_FIRMWARE_IMAGE = 0x107,
1912 NVME_SC_INVALID_VECTOR = 0x108,
1913 NVME_SC_INVALID_LOG_PAGE = 0x109,
1914 NVME_SC_INVALID_FORMAT = 0x10a,
1915 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1916 NVME_SC_INVALID_QUEUE = 0x10c,
1917 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1918 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1919 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1920 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1921 NVME_SC_FW_NEEDS_RESET = 0x111,
1922 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1923 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1924 NVME_SC_OVERLAPPING_RANGE = 0x114,
1925 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1926 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1927 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1928 NVME_SC_NS_IS_PRIVATE = 0x119,
1929 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1930 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1931 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1932 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1933 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1934 NVME_SC_CTRL_ID_INVALID = 0x11f,
1935 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1936 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1937 NVME_SC_RES_ID_INVALID = 0x122,
1938 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1939 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1940 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1941
1942 /*
1943 * I/O Command Set Specific - NVM commands:
1944 */
1945 NVME_SC_BAD_ATTRIBUTES = 0x180,
1946 NVME_SC_INVALID_PI = 0x181,
1947 NVME_SC_READ_ONLY = 0x182,
1948 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1949
1950 /*
1951 * I/O Command Set Specific - Fabrics commands:
1952 */
1953 NVME_SC_CONNECT_FORMAT = 0x180,
1954 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1955 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1956 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1957 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1958
1959 NVME_SC_DISCOVERY_RESTART = 0x190,
1960 NVME_SC_AUTH_REQUIRED = 0x191,
1961
1962 /*
1963 * I/O Command Set Specific - Zoned commands:
1964 */
1965 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1966 NVME_SC_ZONE_FULL = 0x1b9,
1967 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1968 NVME_SC_ZONE_OFFLINE = 0x1bb,
1969 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1970 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1971 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1972 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1973
1974 /*
1975 * Media and Data Integrity Errors:
1976 */
1977 NVME_SC_WRITE_FAULT = 0x280,
1978 NVME_SC_READ_ERROR = 0x281,
1979 NVME_SC_GUARD_CHECK = 0x282,
1980 NVME_SC_APPTAG_CHECK = 0x283,
1981 NVME_SC_REFTAG_CHECK = 0x284,
1982 NVME_SC_COMPARE_FAILED = 0x285,
1983 NVME_SC_ACCESS_DENIED = 0x286,
1984 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1985
1986 /*
1987 * Path-related Errors:
1988 */
1989 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1990 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1991 NVME_SC_ANA_INACCESSIBLE = 0x302,
1992 NVME_SC_ANA_TRANSITION = 0x303,
1993 NVME_SC_CTRL_PATH_ERROR = 0x360,
1994 NVME_SC_HOST_PATH_ERROR = 0x370,
1995 NVME_SC_HOST_ABORTED_CMD = 0x371,
1996
1997 NVME_SC_CRD = 0x1800,
1998 NVME_SC_MORE = 0x2000,
1999 NVME_SC_DNR = 0x4000,
2000};
2001
2002struct nvme_completion {
2003 /*
2004 * Used by Admin and Fabrics commands to return data:
2005 */
2006 union nvme_result {
2007 __le16 u16;
2008 __le32 u32;
2009 __le64 u64;
2010 } result;
2011 __le16 sq_head; /* how much of this queue may be reclaimed */
2012 __le16 sq_id; /* submission queue that generated this entry */
2013 __u16 command_id; /* of the command which completed */
2014 __le16 status; /* did the command fail, and if so, why? */
2015};
2016
2017#define NVME_VS(major, minor, tertiary) \
2018 (((major) << 16) | ((minor) << 8) | (tertiary))
2019
2020#define NVME_MAJOR(ver) ((ver) >> 16)
2021#define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
2022#define NVME_TERTIARY(ver) ((ver) & 0xff)
2023
2024#endif /* _LINUX_NVME_H */
2025

source code of linux/include/linux/nvme.h