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1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
---|---|
2 | /* |
3 | * TI DaVinci Audio Serial Port support |
4 | * |
5 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
6 | */ |
7 | |
8 | #ifndef __DAVINCI_ASP_H |
9 | #define __DAVINCI_ASP_H |
10 | |
11 | #include <linux/genalloc.h> |
12 | |
13 | struct davinci_mcasp_pdata { |
14 | u32 tx_dma_offset; |
15 | u32 rx_dma_offset; |
16 | int asp_chan_q; /* event queue number for ASP channel */ |
17 | int ram_chan_q; /* event queue number for RAM channel */ |
18 | /* |
19 | * Allowing this is more efficient and eliminates left and right swaps |
20 | * caused by underruns, but will swap the left and right channels |
21 | * when compared to previous behavior. |
22 | */ |
23 | unsigned enable_channel_combine:1; |
24 | unsigned sram_size_playback; |
25 | unsigned sram_size_capture; |
26 | struct gen_pool *sram_pool; |
27 | |
28 | /* |
29 | * If McBSP peripheral gets the clock from an external pin, |
30 | * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR |
31 | * and MCBSP_CLKS. |
32 | * Depending on different hardware connections it is possible |
33 | * to use this setting to change the behaviour of McBSP |
34 | * driver. |
35 | */ |
36 | int clk_input_pin; |
37 | |
38 | /* |
39 | * This flag works when both clock and FS are outputs for the cpu |
40 | * and makes clock more accurate (FS is not symmetrical and the |
41 | * clock is very fast. |
42 | * The clock becoming faster is named |
43 | * i2s continuous serial clock (I2S_SCK) and it is an externally |
44 | * visible bit clock. |
45 | * |
46 | * first line : WordSelect |
47 | * second line : ContinuousSerialClock |
48 | * third line: SerialData |
49 | * |
50 | * SYMMETRICAL APPROACH: |
51 | * _______________________ LEFT |
52 | * _| RIGHT |______________________| |
53 | * _ _ _ _ _ _ _ _ |
54 | * _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_ |
55 | * _ _ _ _ _ _ _ _ |
56 | * _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_ |
57 | * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ |
58 | * |
59 | * ACCURATE CLOCK APPROACH: |
60 | * ______________ LEFT |
61 | * _| RIGHT |_______________________________| |
62 | * _ _ _ _ _ _ _ _ _ |
63 | * _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| | |
64 | * _ _ _ _ dummy cycles |
65 | * _/ \_ ... _/ \_/ \_ ... _/ \__________________ |
66 | * \_/ \_/ \_/ \_/ |
67 | * |
68 | */ |
69 | bool i2s_accurate_sck; |
70 | |
71 | /* McASP specific fields */ |
72 | int tdm_slots; |
73 | u8 op_mode; |
74 | u8 dismod; |
75 | u8 num_serializer; |
76 | u8 *serial_dir; |
77 | u8 version; |
78 | u8 txnumevt; |
79 | u8 rxnumevt; |
80 | int tx_dma_channel; |
81 | int rx_dma_channel; |
82 | }; |
83 | /* TODO: Fix arch/arm/mach-davinci/ users and remove this define */ |
84 | #define snd_platform_data davinci_mcasp_pdata |
85 | |
86 | enum { |
87 | MCASP_VERSION_1 = 0, /* DM646x */ |
88 | MCASP_VERSION_2, /* DA8xx/OMAPL1x */ |
89 | MCASP_VERSION_3, /* TI81xx/AM33xx */ |
90 | MCASP_VERSION_4, /* DRA7xxx */ |
91 | MCASP_VERSION_OMAP, /* OMAP4/5 */ |
92 | }; |
93 | |
94 | enum mcbsp_clk_input_pin { |
95 | MCBSP_CLKR = 0, /* as in DM365 */ |
96 | MCBSP_CLKS, |
97 | }; |
98 | |
99 | #define INACTIVE_MODE 0 |
100 | #define TX_MODE 1 |
101 | #define RX_MODE 2 |
102 | |
103 | #define DAVINCI_MCASP_IIS_MODE 0 |
104 | #define DAVINCI_MCASP_DIT_MODE 1 |
105 | |
106 | #endif |
107 |
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