1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * OMAP GPMC Platform data |
4 | * |
5 | * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com |
6 | * Roger Quadros <rogerq@ti.com> |
7 | */ |
8 | |
9 | #ifndef _GPMC_OMAP_H_ |
10 | #define _GPMC_OMAP_H_ |
11 | |
12 | /* Maximum Number of Chip Selects */ |
13 | #define GPMC_CS_NUM 8 |
14 | |
15 | /* bool type time settings */ |
16 | struct gpmc_bool_timings { |
17 | bool cycle2cyclediffcsen; |
18 | bool cycle2cyclesamecsen; |
19 | bool ; |
20 | bool ; |
21 | bool ; |
22 | bool ; |
23 | bool time_para_granularity; |
24 | }; |
25 | |
26 | /* |
27 | * Note that all values in this struct are in nanoseconds except sync_clk |
28 | * (which is in picoseconds), while the register values are in gpmc_fck cycles. |
29 | */ |
30 | struct gpmc_timings { |
31 | /* Minimum clock period for synchronous mode (in picoseconds) */ |
32 | u32 sync_clk; |
33 | |
34 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ |
35 | u32 cs_on; /* Assertion time */ |
36 | u32 cs_rd_off; /* Read deassertion time */ |
37 | u32 cs_wr_off; /* Write deassertion time */ |
38 | |
39 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ |
40 | u32 adv_on; /* Assertion time */ |
41 | u32 adv_rd_off; /* Read deassertion time */ |
42 | u32 adv_wr_off; /* Write deassertion time */ |
43 | u32 adv_aad_mux_on; /* ADV assertion time for AAD */ |
44 | u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */ |
45 | u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */ |
46 | |
47 | /* WE signals timings corresponding to GPMC_CONFIG4 */ |
48 | u32 we_on; /* WE assertion time */ |
49 | u32 we_off; /* WE deassertion time */ |
50 | |
51 | /* OE signals timings corresponding to GPMC_CONFIG4 */ |
52 | u32 oe_on; /* OE assertion time */ |
53 | u32 oe_off; /* OE deassertion time */ |
54 | u32 oe_aad_mux_on; /* OE assertion time for AAD */ |
55 | u32 oe_aad_mux_off; /* OE deassertion time for AAD */ |
56 | |
57 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ |
58 | u32 page_burst_access; /* Multiple access word delay */ |
59 | u32 access; /* Start-cycle to first data valid delay */ |
60 | u32 rd_cycle; /* Total read cycle time */ |
61 | u32 wr_cycle; /* Total write cycle time */ |
62 | |
63 | u32 bus_turnaround; |
64 | u32 cycle2cycle_delay; |
65 | |
66 | u32 wait_monitoring; |
67 | u32 clk_activation; |
68 | |
69 | /* The following are only on OMAP3430 */ |
70 | u32 wr_access; /* WRACCESSTIME */ |
71 | u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */ |
72 | |
73 | struct gpmc_bool_timings bool_timings; |
74 | }; |
75 | |
76 | /* Device timings in picoseconds */ |
77 | struct gpmc_device_timings { |
78 | u32 t_ceasu; /* address setup to CS valid */ |
79 | u32 t_avdasu; /* address setup to ADV valid */ |
80 | /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is |
81 | * of tusb using these timings even for sync whilst |
82 | * ideally for adv_rd/(wr)_off it should have considered |
83 | * t_avdh instead. This indirectly necessitates r/w |
84 | * variations of t_avdp as it is possible to have one |
85 | * sync & other async |
86 | */ |
87 | u32 t_avdp_r; /* ADV low time (what about t_cer ?) */ |
88 | u32 t_avdp_w; |
89 | u32 t_aavdh; /* address hold time */ |
90 | u32 t_oeasu; /* address setup to OE valid */ |
91 | u32 t_aa; /* access time from ADV assertion */ |
92 | u32 t_iaa; /* initial access time */ |
93 | u32 t_oe; /* access time from OE assertion */ |
94 | u32 t_ce; /* access time from CS asertion */ |
95 | u32 t_rd_cycle; /* read cycle time */ |
96 | u32 t_cez_r; /* read CS deassertion to high Z */ |
97 | u32 t_cez_w; /* write CS deassertion to high Z */ |
98 | u32 t_oez; /* OE deassertion to high Z */ |
99 | u32 t_weasu; /* address setup to WE valid */ |
100 | u32 t_wpl; /* write assertion time */ |
101 | u32 t_wph; /* write deassertion time */ |
102 | u32 t_wr_cycle; /* write cycle time */ |
103 | |
104 | u32 clk; |
105 | u32 t_bacc; /* burst access valid clock to output delay */ |
106 | u32 t_ces; /* CS setup time to clk */ |
107 | u32 t_avds; /* ADV setup time to clk */ |
108 | u32 t_avdh; /* ADV hold time from clk */ |
109 | u32 t_ach; /* address hold time from clk */ |
110 | u32 t_rdyo; /* clk to ready valid */ |
111 | |
112 | u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */ |
113 | u32 t_ce_avd; /* CS on to ADV on delay */ |
114 | |
115 | /* XXX: check the possibility of combining |
116 | * cyc_aavhd_oe & cyc_aavdh_we |
117 | */ |
118 | u8 cyc_aavdh_oe;/* read address hold time in cycles */ |
119 | u8 cyc_aavdh_we;/* write address hold time in cycles */ |
120 | u8 cyc_oe; /* access time from OE assertion in cycles */ |
121 | u8 cyc_wpl; /* write deassertion time in cycles */ |
122 | u32 cyc_iaa; /* initial access time in cycles */ |
123 | |
124 | /* extra delays */ |
125 | bool ce_xdelay; |
126 | bool avd_xdelay; |
127 | bool oe_xdelay; |
128 | bool we_xdelay; |
129 | }; |
130 | |
131 | #define GPMC_BURST_4 4 /* 4 word burst */ |
132 | #define GPMC_BURST_8 8 /* 8 word burst */ |
133 | #define GPMC_BURST_16 16 /* 16 word burst */ |
134 | #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */ |
135 | #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */ |
136 | #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */ |
137 | #define GPMC_MUX_AD 2 /* Addr-Data multiplex */ |
138 | |
139 | /* Wait pin polarity values */ |
140 | #define GPMC_WAITPINPOLARITY_INVALID UINT_MAX |
141 | #define GPMC_WAITPINPOLARITY_ACTIVE_LOW 0 |
142 | #define GPMC_WAITPINPOLARITY_ACTIVE_HIGH 1 |
143 | |
144 | #define GPMC_WAITPIN_INVALID UINT_MAX |
145 | |
146 | struct gpmc_settings { |
147 | bool burst_wrap; /* enables wrap bursting */ |
148 | bool burst_read; /* enables read page/burst mode */ |
149 | bool burst_write; /* enables write page/burst mode */ |
150 | bool device_nand; /* device is NAND */ |
151 | bool sync_read; /* enables synchronous reads */ |
152 | bool sync_write; /* enables synchronous writes */ |
153 | bool wait_on_read; /* monitor wait on reads */ |
154 | bool wait_on_write; /* monitor wait on writes */ |
155 | u32 burst_len; /* page/burst length */ |
156 | u32 device_width; /* device bus width (8 or 16 bit) */ |
157 | u32 mux_add_data; /* multiplex address & data */ |
158 | u32 wait_pin; /* wait-pin to be used */ |
159 | u32 wait_pin_polarity; |
160 | }; |
161 | |
162 | /* Data for each chip select */ |
163 | struct gpmc_omap_cs_data { |
164 | bool valid; /* data is valid */ |
165 | bool is_nand; /* device within this CS is NAND */ |
166 | struct gpmc_settings *settings; |
167 | struct gpmc_device_timings *device_timings; |
168 | struct gpmc_timings *gpmc_timings; |
169 | struct platform_device *pdev; /* device within this CS region */ |
170 | unsigned int pdata_size; |
171 | }; |
172 | |
173 | struct gpmc_omap_platform_data { |
174 | struct gpmc_omap_cs_data cs[GPMC_CS_NUM]; |
175 | }; |
176 | |
177 | #endif /* _GPMC_OMAP_H */ |
178 | |