1/* Copyright (c) 2010-2015, 2018, The Linux Foundation. All rights reserved.
2 * Copyright (C) 2015 Linaro Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __QCOM_SCM_H
14#define __QCOM_SCM_H
15
16#include <linux/err.h>
17#include <linux/types.h>
18#include <linux/cpumask.h>
19
20#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
21#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
22#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
23#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
24
25struct qcom_scm_hdcp_req {
26 u32 addr;
27 u32 val;
28};
29
30struct qcom_scm_vmperm {
31 int vmid;
32 int perm;
33};
34
35#define QCOM_SCM_VMID_HLOS 0x3
36#define QCOM_SCM_VMID_MSS_MSA 0xF
37#define QCOM_SCM_VMID_WLAN 0x18
38#define QCOM_SCM_VMID_WLAN_CE 0x19
39#define QCOM_SCM_PERM_READ 0x4
40#define QCOM_SCM_PERM_WRITE 0x2
41#define QCOM_SCM_PERM_EXEC 0x1
42#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
43#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
44
45#if IS_ENABLED(CONFIG_QCOM_SCM)
46extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
47extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
48extern bool qcom_scm_is_available(void);
49extern bool qcom_scm_hdcp_available(void);
50extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
51 u32 *resp);
52extern bool qcom_scm_pas_supported(u32 peripheral);
53extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
54 size_t size);
55extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
56 phys_addr_t size);
57extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
58extern int qcom_scm_pas_shutdown(u32 peripheral);
59extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
60 unsigned int *src, struct qcom_scm_vmperm *newvm,
61 int dest_cnt);
62extern void qcom_scm_cpu_power_down(u32 flags);
63extern u32 qcom_scm_get_version(void);
64extern int qcom_scm_set_remote_state(u32 state, u32 id);
65extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
66extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
67extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
68extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
69extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
70#else
71
72#include <linux/errno.h>
73
74static inline
75int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
76{
77 return -ENODEV;
78}
79static inline
80int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
81{
82 return -ENODEV;
83}
84static inline bool qcom_scm_is_available(void) { return false; }
85static inline bool qcom_scm_hdcp_available(void) { return false; }
86static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
87 u32 *resp) { return -ENODEV; }
88static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
89static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
90 size_t size) { return -ENODEV; }
91static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
92 phys_addr_t size) { return -ENODEV; }
93static inline int
94qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
95static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
96static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
97 unsigned int *src,
98 struct qcom_scm_vmperm *newvm,
99 int dest_cnt) { return -ENODEV; }
100static inline void qcom_scm_cpu_power_down(u32 flags) {}
101static inline u32 qcom_scm_get_version(void) { return 0; }
102static inline u32
103qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
104static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
105static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
106static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
107static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
108static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
109#endif
110#endif
111