1/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 */
21
22#ifndef __RTSX_PCI_H
23#define __RTSX_PCI_H
24
25#include <linux/sched.h>
26#include <linux/pci.h>
27#include <linux/rtsx_common.h>
28
29#define MAX_RW_REG_CNT 1024
30
31#define RTSX_HCBAR 0x00
32#define RTSX_HCBCTLR 0x04
33#define STOP_CMD (0x01 << 28)
34#define READ_REG_CMD 0
35#define WRITE_REG_CMD 1
36#define CHECK_REG_CMD 2
37
38#define RTSX_HDBAR 0x08
39#define RTSX_SG_INT 0x04
40#define RTSX_SG_END 0x02
41#define RTSX_SG_VALID 0x01
42#define RTSX_SG_NO_OP 0x00
43#define RTSX_SG_TRANS_DATA (0x02 << 4)
44#define RTSX_SG_LINK_DESC (0x03 << 4)
45#define RTSX_HDBCTLR 0x0C
46#define SDMA_MODE 0x00
47#define ADMA_MODE (0x02 << 26)
48#define STOP_DMA (0x01 << 28)
49#define TRIG_DMA (0x01 << 31)
50
51#define RTSX_HAIMR 0x10
52#define HAIMR_TRANS_START (0x01 << 31)
53#define HAIMR_READ 0x00
54#define HAIMR_WRITE (0x01 << 30)
55#define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ)
56#define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE)
57#define HAIMR_TRANS_END (HAIMR_TRANS_START)
58
59#define RTSX_BIPR 0x14
60#define CMD_DONE_INT (1 << 31)
61#define DATA_DONE_INT (1 << 30)
62#define TRANS_OK_INT (1 << 29)
63#define TRANS_FAIL_INT (1 << 28)
64#define XD_INT (1 << 27)
65#define MS_INT (1 << 26)
66#define SD_INT (1 << 25)
67#define GPIO0_INT (1 << 24)
68#define OC_INT (1 << 23)
69#define SD_WRITE_PROTECT (1 << 19)
70#define XD_EXIST (1 << 18)
71#define MS_EXIST (1 << 17)
72#define SD_EXIST (1 << 16)
73#define DELINK_INT GPIO0_INT
74#define MS_OC_INT (1 << 23)
75#define SD_OC_INT (1 << 22)
76
77#define CARD_INT (XD_INT | MS_INT | SD_INT)
78#define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
79#define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \
80 CARD_INT | GPIO0_INT | OC_INT)
81#define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST)
82
83#define RTSX_BIER 0x18
84#define CMD_DONE_INT_EN (1 << 31)
85#define DATA_DONE_INT_EN (1 << 30)
86#define TRANS_OK_INT_EN (1 << 29)
87#define TRANS_FAIL_INT_EN (1 << 28)
88#define XD_INT_EN (1 << 27)
89#define MS_INT_EN (1 << 26)
90#define SD_INT_EN (1 << 25)
91#define GPIO0_INT_EN (1 << 24)
92#define OC_INT_EN (1 << 23)
93#define DELINK_INT_EN GPIO0_INT_EN
94#define MS_OC_INT_EN (1 << 23)
95#define SD_OC_INT_EN (1 << 22)
96
97
98/*
99 * macros for easy use
100 */
101#define rtsx_pci_writel(pcr, reg, value) \
102 iowrite32(value, (pcr)->remap_addr + reg)
103#define rtsx_pci_readl(pcr, reg) \
104 ioread32((pcr)->remap_addr + reg)
105#define rtsx_pci_writew(pcr, reg, value) \
106 iowrite16(value, (pcr)->remap_addr + reg)
107#define rtsx_pci_readw(pcr, reg) \
108 ioread16((pcr)->remap_addr + reg)
109#define rtsx_pci_writeb(pcr, reg, value) \
110 iowrite8(value, (pcr)->remap_addr + reg)
111#define rtsx_pci_readb(pcr, reg) \
112 ioread8((pcr)->remap_addr + reg)
113
114#define rtsx_pci_read_config_byte(pcr, where, val) \
115 pci_read_config_byte((pcr)->pci, where, val)
116
117#define rtsx_pci_write_config_byte(pcr, where, val) \
118 pci_write_config_byte((pcr)->pci, where, val)
119
120#define rtsx_pci_read_config_dword(pcr, where, val) \
121 pci_read_config_dword((pcr)->pci, where, val)
122
123#define rtsx_pci_write_config_dword(pcr, where, val) \
124 pci_write_config_dword((pcr)->pci, where, val)
125
126#define STATE_TRANS_NONE 0
127#define STATE_TRANS_CMD 1
128#define STATE_TRANS_BUF 2
129#define STATE_TRANS_SG 3
130
131#define TRANS_NOT_READY 0
132#define TRANS_RESULT_OK 1
133#define TRANS_RESULT_FAIL 2
134#define TRANS_NO_DEVICE 3
135
136#define RTSX_RESV_BUF_LEN 4096
137#define HOST_CMDS_BUF_LEN 1024
138#define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
139#define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8)
140#define MAX_SG_ITEM_LEN 0x80000
141#define HOST_TO_DEVICE 0
142#define DEVICE_TO_HOST 1
143
144#define OUTPUT_3V3 0
145#define OUTPUT_1V8 1
146
147#define RTSX_PHASE_MAX 32
148#define RX_TUNING_CNT 3
149
150#define MS_CFG 0xFD40
151#define SAMPLE_TIME_RISING 0x00
152#define SAMPLE_TIME_FALLING 0x80
153#define PUSH_TIME_DEFAULT 0x00
154#define PUSH_TIME_ODD 0x40
155#define NO_EXTEND_TOGGLE 0x00
156#define EXTEND_TOGGLE_CHK 0x20
157#define MS_BUS_WIDTH_1 0x00
158#define MS_BUS_WIDTH_4 0x10
159#define MS_BUS_WIDTH_8 0x18
160#define MS_2K_SECTOR_MODE 0x04
161#define MS_512_SECTOR_MODE 0x00
162#define MS_TOGGLE_TIMEOUT_EN 0x00
163#define MS_TOGGLE_TIMEOUT_DISEN 0x01
164#define MS_NO_CHECK_INT 0x02
165#define MS_TPC 0xFD41
166#define MS_TRANS_CFG 0xFD42
167#define WAIT_INT 0x80
168#define NO_WAIT_INT 0x00
169#define NO_AUTO_READ_INT_REG 0x00
170#define AUTO_READ_INT_REG 0x40
171#define MS_CRC16_ERR 0x20
172#define MS_RDY_TIMEOUT 0x10
173#define MS_INT_CMDNK 0x08
174#define MS_INT_BREQ 0x04
175#define MS_INT_ERR 0x02
176#define MS_INT_CED 0x01
177#define MS_TRANSFER 0xFD43
178#define MS_TRANSFER_START 0x80
179#define MS_TRANSFER_END 0x40
180#define MS_TRANSFER_ERR 0x20
181#define MS_BS_STATE 0x10
182#define MS_TM_READ_BYTES 0x00
183#define MS_TM_NORMAL_READ 0x01
184#define MS_TM_WRITE_BYTES 0x04
185#define MS_TM_NORMAL_WRITE 0x05
186#define MS_TM_AUTO_READ 0x08
187#define MS_TM_AUTO_WRITE 0x0C
188#define MS_INT_REG 0xFD44
189#define MS_BYTE_CNT 0xFD45
190#define MS_SECTOR_CNT_L 0xFD46
191#define MS_SECTOR_CNT_H 0xFD47
192#define MS_DBUS_H 0xFD48
193
194#define SD_CFG1 0xFDA0
195#define SD_CLK_DIVIDE_0 0x00
196#define SD_CLK_DIVIDE_256 0xC0
197#define SD_CLK_DIVIDE_128 0x80
198#define SD_BUS_WIDTH_1BIT 0x00
199#define SD_BUS_WIDTH_4BIT 0x01
200#define SD_BUS_WIDTH_8BIT 0x02
201#define SD_ASYNC_FIFO_NOT_RST 0x10
202#define SD_20_MODE 0x00
203#define SD_DDR_MODE 0x04
204#define SD_30_MODE 0x08
205#define SD_CLK_DIVIDE_MASK 0xC0
206#define SD_MODE_SELECT_MASK 0x0C
207#define SD_CFG2 0xFDA1
208#define SD_CALCULATE_CRC7 0x00
209#define SD_NO_CALCULATE_CRC7 0x80
210#define SD_CHECK_CRC16 0x00
211#define SD_NO_CHECK_CRC16 0x40
212#define SD_NO_CHECK_WAIT_CRC_TO 0x20
213#define SD_WAIT_BUSY_END 0x08
214#define SD_NO_WAIT_BUSY_END 0x00
215#define SD_CHECK_CRC7 0x00
216#define SD_NO_CHECK_CRC7 0x04
217#define SD_RSP_LEN_0 0x00
218#define SD_RSP_LEN_6 0x01
219#define SD_RSP_LEN_17 0x02
220#define SD_RSP_TYPE_R0 0x04
221#define SD_RSP_TYPE_R1 0x01
222#define SD_RSP_TYPE_R1b 0x09
223#define SD_RSP_TYPE_R2 0x02
224#define SD_RSP_TYPE_R3 0x05
225#define SD_RSP_TYPE_R4 0x05
226#define SD_RSP_TYPE_R5 0x01
227#define SD_RSP_TYPE_R6 0x01
228#define SD_RSP_TYPE_R7 0x01
229#define SD_CFG3 0xFDA2
230#define SD30_CLK_END_EN 0x10
231#define SD_RSP_80CLK_TIMEOUT_EN 0x01
232
233#define SD_STAT1 0xFDA3
234#define SD_CRC7_ERR 0x80
235#define SD_CRC16_ERR 0x40
236#define SD_CRC_WRITE_ERR 0x20
237#define SD_CRC_WRITE_ERR_MASK 0x1C
238#define GET_CRC_TIME_OUT 0x02
239#define SD_TUNING_COMPARE_ERR 0x01
240#define SD_STAT2 0xFDA4
241#define SD_RSP_80CLK_TIMEOUT 0x01
242
243#define SD_BUS_STAT 0xFDA5
244#define SD_CLK_TOGGLE_EN 0x80
245#define SD_CLK_FORCE_STOP 0x40
246#define SD_DAT3_STATUS 0x10
247#define SD_DAT2_STATUS 0x08
248#define SD_DAT1_STATUS 0x04
249#define SD_DAT0_STATUS 0x02
250#define SD_CMD_STATUS 0x01
251#define SD_PAD_CTL 0xFDA6
252#define SD_IO_USING_1V8 0x80
253#define SD_IO_USING_3V3 0x7F
254#define TYPE_A_DRIVING 0x00
255#define TYPE_B_DRIVING 0x01
256#define TYPE_C_DRIVING 0x02
257#define TYPE_D_DRIVING 0x03
258#define SD_SAMPLE_POINT_CTL 0xFDA7
259#define DDR_FIX_RX_DAT 0x00
260#define DDR_VAR_RX_DAT 0x80
261#define DDR_FIX_RX_DAT_EDGE 0x00
262#define DDR_FIX_RX_DAT_14_DELAY 0x40
263#define DDR_FIX_RX_CMD 0x00
264#define DDR_VAR_RX_CMD 0x20
265#define DDR_FIX_RX_CMD_POS_EDGE 0x00
266#define DDR_FIX_RX_CMD_14_DELAY 0x10
267#define SD20_RX_POS_EDGE 0x00
268#define SD20_RX_14_DELAY 0x08
269#define SD20_RX_SEL_MASK 0x08
270#define SD_PUSH_POINT_CTL 0xFDA8
271#define DDR_FIX_TX_CMD_DAT 0x00
272#define DDR_VAR_TX_CMD_DAT 0x80
273#define DDR_FIX_TX_DAT_14_TSU 0x00
274#define DDR_FIX_TX_DAT_12_TSU 0x40
275#define DDR_FIX_TX_CMD_NEG_EDGE 0x00
276#define DDR_FIX_TX_CMD_14_AHEAD 0x20
277#define SD20_TX_NEG_EDGE 0x00
278#define SD20_TX_14_AHEAD 0x10
279#define SD20_TX_SEL_MASK 0x10
280#define DDR_VAR_SDCLK_POL_SWAP 0x01
281#define SD_CMD0 0xFDA9
282#define SD_CMD_START 0x40
283#define SD_CMD1 0xFDAA
284#define SD_CMD2 0xFDAB
285#define SD_CMD3 0xFDAC
286#define SD_CMD4 0xFDAD
287#define SD_CMD5 0xFDAE
288#define SD_BYTE_CNT_L 0xFDAF
289#define SD_BYTE_CNT_H 0xFDB0
290#define SD_BLOCK_CNT_L 0xFDB1
291#define SD_BLOCK_CNT_H 0xFDB2
292#define SD_TRANSFER 0xFDB3
293#define SD_TRANSFER_START 0x80
294#define SD_TRANSFER_END 0x40
295#define SD_STAT_IDLE 0x20
296#define SD_TRANSFER_ERR 0x10
297#define SD_TM_NORMAL_WRITE 0x00
298#define SD_TM_AUTO_WRITE_3 0x01
299#define SD_TM_AUTO_WRITE_4 0x02
300#define SD_TM_AUTO_READ_3 0x05
301#define SD_TM_AUTO_READ_4 0x06
302#define SD_TM_CMD_RSP 0x08
303#define SD_TM_AUTO_WRITE_1 0x09
304#define SD_TM_AUTO_WRITE_2 0x0A
305#define SD_TM_NORMAL_READ 0x0C
306#define SD_TM_AUTO_READ_1 0x0D
307#define SD_TM_AUTO_READ_2 0x0E
308#define SD_TM_AUTO_TUNING 0x0F
309#define SD_CMD_STATE 0xFDB5
310#define SD_CMD_IDLE 0x80
311
312#define SD_DATA_STATE 0xFDB6
313#define SD_DATA_IDLE 0x80
314#define REG_SD_STOP_SDCLK_CFG 0xFDB8
315#define SD30_CLK_STOP_CFG_EN 0x04
316#define SD30_CLK_STOP_CFG1 0x02
317#define SD30_CLK_STOP_CFG0 0x01
318#define REG_PRE_RW_MODE 0xFD70
319#define EN_INFINITE_MODE 0x01
320
321#define SRCTL 0xFC13
322
323#define DCM_DRP_CTL 0xFC23
324#define DCM_RESET 0x08
325#define DCM_LOCKED 0x04
326#define DCM_208M 0x00
327#define DCM_TX 0x01
328#define DCM_RX 0x02
329#define DCM_DRP_TRIG 0xFC24
330#define DRP_START 0x80
331#define DRP_DONE 0x40
332#define DCM_DRP_CFG 0xFC25
333#define DRP_WRITE 0x80
334#define DRP_READ 0x00
335#define DCM_WRITE_ADDRESS_50 0x50
336#define DCM_WRITE_ADDRESS_51 0x51
337#define DCM_READ_ADDRESS_00 0x00
338#define DCM_READ_ADDRESS_51 0x51
339#define DCM_DRP_WR_DATA_L 0xFC26
340#define DCM_DRP_WR_DATA_H 0xFC27
341#define DCM_DRP_RD_DATA_L 0xFC28
342#define DCM_DRP_RD_DATA_H 0xFC29
343#define SD_VPCLK0_CTL 0xFC2A
344#define SD_VPCLK1_CTL 0xFC2B
345#define PHASE_SELECT_MASK 0x1F
346#define SD_DCMPS0_CTL 0xFC2C
347#define SD_DCMPS1_CTL 0xFC2D
348#define SD_VPTX_CTL SD_VPCLK0_CTL
349#define SD_VPRX_CTL SD_VPCLK1_CTL
350#define PHASE_CHANGE 0x80
351#define PHASE_NOT_RESET 0x40
352#define SD_DCMPS_TX_CTL SD_DCMPS0_CTL
353#define SD_DCMPS_RX_CTL SD_DCMPS1_CTL
354#define DCMPS_CHANGE 0x80
355#define DCMPS_CHANGE_DONE 0x40
356#define DCMPS_ERROR 0x20
357#define DCMPS_CURRENT_PHASE 0x1F
358#define CARD_CLK_SOURCE 0xFC2E
359#define CRC_FIX_CLK (0x00 << 0)
360#define CRC_VAR_CLK0 (0x01 << 0)
361#define CRC_VAR_CLK1 (0x02 << 0)
362#define SD30_FIX_CLK (0x00 << 2)
363#define SD30_VAR_CLK0 (0x01 << 2)
364#define SD30_VAR_CLK1 (0x02 << 2)
365#define SAMPLE_FIX_CLK (0x00 << 4)
366#define SAMPLE_VAR_CLK0 (0x01 << 4)
367#define SAMPLE_VAR_CLK1 (0x02 << 4)
368#define CARD_PWR_CTL 0xFD50
369#define PMOS_STRG_MASK 0x10
370#define PMOS_STRG_800mA 0x10
371#define PMOS_STRG_400mA 0x00
372#define SD_POWER_OFF 0x03
373#define SD_PARTIAL_POWER_ON 0x01
374#define SD_POWER_ON 0x00
375#define SD_POWER_MASK 0x03
376#define MS_POWER_OFF 0x0C
377#define MS_PARTIAL_POWER_ON 0x04
378#define MS_POWER_ON 0x00
379#define MS_POWER_MASK 0x0C
380#define BPP_POWER_OFF 0x0F
381#define BPP_POWER_5_PERCENT_ON 0x0E
382#define BPP_POWER_10_PERCENT_ON 0x0C
383#define BPP_POWER_15_PERCENT_ON 0x08
384#define BPP_POWER_ON 0x00
385#define BPP_POWER_MASK 0x0F
386#define SD_VCC_PARTIAL_POWER_ON 0x02
387#define SD_VCC_POWER_ON 0x00
388#define CARD_CLK_SWITCH 0xFD51
389#define RTL8411B_PACKAGE_MODE 0xFD51
390#define CARD_SHARE_MODE 0xFD52
391#define CARD_SHARE_MASK 0x0F
392#define CARD_SHARE_MULTI_LUN 0x00
393#define CARD_SHARE_NORMAL 0x00
394#define CARD_SHARE_48_SD 0x04
395#define CARD_SHARE_48_MS 0x08
396#define CARD_SHARE_BAROSSA_SD 0x01
397#define CARD_SHARE_BAROSSA_MS 0x02
398#define CARD_DRIVE_SEL 0xFD53
399#define MS_DRIVE_8mA (0x01 << 6)
400#define MMC_DRIVE_8mA (0x01 << 4)
401#define XD_DRIVE_8mA (0x01 << 2)
402#define GPIO_DRIVE_8mA 0x01
403#define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
404 XD_DRIVE_8mA | GPIO_DRIVE_8mA)
405#define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\
406 XD_DRIVE_8mA)
407#define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA)
408
409#define CARD_STOP 0xFD54
410#define SPI_STOP 0x01
411#define XD_STOP 0x02
412#define SD_STOP 0x04
413#define MS_STOP 0x08
414#define SPI_CLR_ERR 0x10
415#define XD_CLR_ERR 0x20
416#define SD_CLR_ERR 0x40
417#define MS_CLR_ERR 0x80
418#define CARD_OE 0xFD55
419#define SD_OUTPUT_EN 0x04
420#define MS_OUTPUT_EN 0x08
421#define CARD_AUTO_BLINK 0xFD56
422#define CARD_GPIO_DIR 0xFD57
423#define CARD_GPIO 0xFD58
424#define CARD_DATA_SOURCE 0xFD5B
425#define PINGPONG_BUFFER 0x01
426#define RING_BUFFER 0x00
427#define SD30_CLK_DRIVE_SEL 0xFD5A
428#define DRIVER_TYPE_A 0x05
429#define DRIVER_TYPE_B 0x03
430#define DRIVER_TYPE_C 0x02
431#define DRIVER_TYPE_D 0x01
432#define CARD_SELECT 0xFD5C
433#define SD_MOD_SEL 2
434#define MS_MOD_SEL 3
435#define SD30_DRIVE_SEL 0xFD5E
436#define CFG_DRIVER_TYPE_A 0x02
437#define CFG_DRIVER_TYPE_B 0x03
438#define CFG_DRIVER_TYPE_C 0x01
439#define CFG_DRIVER_TYPE_D 0x00
440#define SD30_CMD_DRIVE_SEL 0xFD5E
441#define SD30_DAT_DRIVE_SEL 0xFD5F
442#define CARD_CLK_EN 0xFD69
443#define SD_CLK_EN 0x04
444#define MS_CLK_EN 0x08
445#define SD40_CLK_EN 0x10
446#define SDIO_CTRL 0xFD6B
447#define CD_PAD_CTL 0xFD73
448#define CD_DISABLE_MASK 0x07
449#define MS_CD_DISABLE 0x04
450#define SD_CD_DISABLE 0x02
451#define XD_CD_DISABLE 0x01
452#define CD_DISABLE 0x07
453#define CD_ENABLE 0x00
454#define MS_CD_EN_ONLY 0x03
455#define SD_CD_EN_ONLY 0x05
456#define XD_CD_EN_ONLY 0x06
457#define FORCE_CD_LOW_MASK 0x38
458#define FORCE_CD_XD_LOW 0x08
459#define FORCE_CD_SD_LOW 0x10
460#define FORCE_CD_MS_LOW 0x20
461#define CD_AUTO_DISABLE 0x40
462#define FPDCTL 0xFC00
463#define SSC_POWER_DOWN 0x01
464#define SD_OC_POWER_DOWN 0x02
465#define ALL_POWER_DOWN 0x03
466#define OC_POWER_DOWN 0x02
467#define PDINFO 0xFC01
468
469#define CLK_CTL 0xFC02
470#define CHANGE_CLK 0x01
471#define CLK_LOW_FREQ 0x01
472
473#define CLK_DIV 0xFC03
474#define CLK_DIV_1 0x01
475#define CLK_DIV_2 0x02
476#define CLK_DIV_4 0x03
477#define CLK_DIV_8 0x04
478#define CLK_SEL 0xFC04
479
480#define SSC_DIV_N_0 0xFC0F
481#define SSC_DIV_N_1 0xFC10
482#define SSC_CTL1 0xFC11
483#define SSC_RSTB 0x80
484#define SSC_8X_EN 0x40
485#define SSC_FIX_FRAC 0x20
486#define SSC_SEL_1M 0x00
487#define SSC_SEL_2M 0x08
488#define SSC_SEL_4M 0x10
489#define SSC_SEL_8M 0x18
490#define SSC_CTL2 0xFC12
491#define SSC_DEPTH_MASK 0x07
492#define SSC_DEPTH_DISALBE 0x00
493#define SSC_DEPTH_4M 0x01
494#define SSC_DEPTH_2M 0x02
495#define SSC_DEPTH_1M 0x03
496#define SSC_DEPTH_500K 0x04
497#define SSC_DEPTH_250K 0x05
498#define RCCTL 0xFC14
499
500#define FPGA_PULL_CTL 0xFC1D
501#define OLT_LED_CTL 0xFC1E
502#define LED_SHINE_MASK 0x08
503#define LED_SHINE_EN 0x08
504#define LED_SHINE_DISABLE 0x00
505#define GPIO_CTL 0xFC1F
506
507#define LDO_CTL 0xFC1E
508#define BPP_ASIC_1V7 0x00
509#define BPP_ASIC_1V8 0x01
510#define BPP_ASIC_1V9 0x02
511#define BPP_ASIC_2V0 0x03
512#define BPP_ASIC_2V7 0x04
513#define BPP_ASIC_2V8 0x05
514#define BPP_ASIC_3V2 0x06
515#define BPP_ASIC_3V3 0x07
516#define BPP_REG_TUNED18 0x07
517#define BPP_TUNED18_SHIFT_8402 5
518#define BPP_TUNED18_SHIFT_8411 4
519#define BPP_PAD_MASK 0x04
520#define BPP_PAD_3V3 0x04
521#define BPP_PAD_1V8 0x00
522#define BPP_LDO_POWB 0x03
523#define BPP_LDO_ON 0x00
524#define BPP_LDO_SUSPEND 0x02
525#define BPP_LDO_OFF 0x03
526#define EFUSE_CTL 0xFC30
527#define EFUSE_ADD 0xFC31
528#define SYS_VER 0xFC32
529#define EFUSE_DATAL 0xFC34
530#define EFUSE_DATAH 0xFC35
531
532#define CARD_PULL_CTL1 0xFD60
533#define CARD_PULL_CTL2 0xFD61
534#define CARD_PULL_CTL3 0xFD62
535#define CARD_PULL_CTL4 0xFD63
536#define CARD_PULL_CTL5 0xFD64
537#define CARD_PULL_CTL6 0xFD65
538
539/* PCI Express Related Registers */
540#define IRQEN0 0xFE20
541#define IRQSTAT0 0xFE21
542#define DMA_DONE_INT 0x80
543#define SUSPEND_INT 0x40
544#define LINK_RDY_INT 0x20
545#define LINK_DOWN_INT 0x10
546#define IRQEN1 0xFE22
547#define IRQSTAT1 0xFE23
548#define TLPRIEN 0xFE24
549#define TLPRISTAT 0xFE25
550#define TLPTIEN 0xFE26
551#define TLPTISTAT 0xFE27
552#define DMATC0 0xFE28
553#define DMATC1 0xFE29
554#define DMATC2 0xFE2A
555#define DMATC3 0xFE2B
556#define DMACTL 0xFE2C
557#define DMA_RST 0x80
558#define DMA_BUSY 0x04
559#define DMA_DIR_TO_CARD 0x00
560#define DMA_DIR_FROM_CARD 0x02
561#define DMA_EN 0x01
562#define DMA_128 (0 << 4)
563#define DMA_256 (1 << 4)
564#define DMA_512 (2 << 4)
565#define DMA_1024 (3 << 4)
566#define DMA_PACK_SIZE_MASK 0x30
567#define BCTL 0xFE2D
568#define RBBC0 0xFE2E
569#define RBBC1 0xFE2F
570#define RBDAT 0xFE30
571#define RBCTL 0xFE34
572#define U_AUTO_DMA_EN_MASK 0x20
573#define U_AUTO_DMA_DISABLE 0x00
574#define RB_FLUSH 0x80
575#define CFGADDR0 0xFE35
576#define CFGADDR1 0xFE36
577#define CFGDATA0 0xFE37
578#define CFGDATA1 0xFE38
579#define CFGDATA2 0xFE39
580#define CFGDATA3 0xFE3A
581#define CFGRWCTL 0xFE3B
582#define PHYRWCTL 0xFE3C
583#define PHYDATA0 0xFE3D
584#define PHYDATA1 0xFE3E
585#define PHYADDR 0xFE3F
586#define MSGRXDATA0 0xFE40
587#define MSGRXDATA1 0xFE41
588#define MSGRXDATA2 0xFE42
589#define MSGRXDATA3 0xFE43
590#define MSGTXDATA0 0xFE44
591#define MSGTXDATA1 0xFE45
592#define MSGTXDATA2 0xFE46
593#define MSGTXDATA3 0xFE47
594#define MSGTXCTL 0xFE48
595#define LTR_CTL 0xFE4A
596#define LTR_TX_EN_MASK BIT(7)
597#define LTR_TX_EN_1 BIT(7)
598#define LTR_TX_EN_0 0
599#define LTR_LATENCY_MODE_MASK BIT(6)
600#define LTR_LATENCY_MODE_HW 0
601#define LTR_LATENCY_MODE_SW BIT(6)
602#define OBFF_CFG 0xFE4C
603#define OBFF_EN_MASK 0x03
604#define OBFF_DISABLE 0x00
605
606#define CDRESUMECTL 0xFE52
607#define WAKE_SEL_CTL 0xFE54
608#define PCLK_CTL 0xFE55
609#define PCLK_MODE_SEL 0x20
610#define PME_FORCE_CTL 0xFE56
611
612#define ASPM_FORCE_CTL 0xFE57
613#define FORCE_ASPM_CTL0 0x10
614#define FORCE_ASPM_VAL_MASK 0x03
615#define FORCE_ASPM_L1_EN 0x02
616#define FORCE_ASPM_L0_EN 0x01
617#define FORCE_ASPM_NO_ASPM 0x00
618#define PM_CLK_FORCE_CTL 0xFE58
619#define CLK_PM_EN 0x01
620#define FUNC_FORCE_CTL 0xFE59
621#define FUNC_FORCE_UPME_XMT_DBG 0x02
622#define PERST_GLITCH_WIDTH 0xFE5C
623#define CHANGE_LINK_STATE 0xFE5B
624#define RESET_LOAD_REG 0xFE5E
625#define EFUSE_CONTENT 0xFE5F
626#define HOST_SLEEP_STATE 0xFE60
627#define HOST_ENTER_S1 1
628#define HOST_ENTER_S3 2
629
630#define SDIO_CFG 0xFE70
631#define PM_EVENT_DEBUG 0xFE71
632#define PME_DEBUG_0 0x08
633#define NFTS_TX_CTRL 0xFE72
634
635#define PWR_GATE_CTRL 0xFE75
636#define PWR_GATE_EN 0x01
637#define LDO3318_PWR_MASK 0x06
638#define LDO_ON 0x00
639#define LDO_SUSPEND 0x04
640#define LDO_OFF 0x06
641#define PWD_SUSPEND_EN 0xFE76
642#define LDO_PWR_SEL 0xFE78
643
644#define L1SUB_CONFIG1 0xFE8D
645#define AUX_CLK_ACTIVE_SEL_MASK 0x01
646#define MAC_CKSW_DONE 0x00
647#define L1SUB_CONFIG2 0xFE8E
648#define L1SUB_AUTO_CFG 0x02
649#define L1SUB_CONFIG3 0xFE8F
650#define L1OFF_MBIAS2_EN_5250 BIT(7)
651
652#define DUMMY_REG_RESET_0 0xFE90
653#define IC_VERSION_MASK 0x0F
654
655#define REG_VREF 0xFE97
656#define PWD_SUSPND_EN 0x10
657#define RTS5260_DMA_RST_CTL_0 0xFEBF
658#define RTS5260_DMA_RST 0x80
659#define RTS5260_ADMA3_RST 0x40
660#define AUTOLOAD_CFG_BASE 0xFF00
661#define RELINK_TIME_MASK 0x01
662#define PETXCFG 0xFF03
663#define FORCE_CLKREQ_DELINK_MASK BIT(7)
664#define FORCE_CLKREQ_LOW 0x80
665#define FORCE_CLKREQ_HIGH 0x00
666
667#define PM_CTRL1 0xFF44
668#define CD_RESUME_EN_MASK 0xF0
669
670#define PM_CTRL2 0xFF45
671#define PM_CTRL3 0xFF46
672#define SDIO_SEND_PME_EN 0x80
673#define FORCE_RC_MODE_ON 0x40
674#define FORCE_RX50_LINK_ON 0x20
675#define D3_DELINK_MODE_EN 0x10
676#define USE_PESRTB_CTL_DELINK 0x08
677#define DELAY_PIN_WAKE 0x04
678#define RESET_PIN_WAKE 0x02
679#define PM_WAKE_EN 0x01
680#define PM_CTRL4 0xFF47
681
682/* Memory mapping */
683#define SRAM_BASE 0xE600
684#define RBUF_BASE 0xF400
685#define PPBUF_BASE1 0xF800
686#define PPBUF_BASE2 0xFA00
687#define IMAGE_FLAG_ADDR0 0xCE80
688#define IMAGE_FLAG_ADDR1 0xCE81
689
690#define RREF_CFG 0xFF6C
691#define RREF_VBGSEL_MASK 0x38
692#define RREF_VBGSEL_1V25 0x28
693
694#define OOBS_CONFIG 0xFF6E
695#define OOBS_AUTOK_DIS 0x80
696#define OOBS_VAL_MASK 0x1F
697
698#define LDO_DV18_CFG 0xFF70
699#define LDO_DV18_SR_MASK 0xC0
700#define LDO_DV18_SR_DF 0x40
701#define DV331812_MASK 0x70
702#define DV331812_33 0x70
703#define DV331812_17 0x30
704
705#define LDO_CONFIG2 0xFF71
706#define LDO_D3318_MASK 0x07
707#define LDO_D3318_33V 0x07
708#define LDO_D3318_18V 0x02
709#define DV331812_VDD1 0x04
710#define DV331812_POWERON 0x08
711#define DV331812_POWEROFF 0x00
712
713#define LDO_VCC_CFG0 0xFF72
714#define LDO_VCC_LMTVTH_MASK 0x30
715#define LDO_VCC_LMTVTH_2A 0x10
716/*RTS5260*/
717#define RTS5260_DVCC_TUNE_MASK 0x70
718#define RTS5260_DVCC_33 0x70
719
720#define LDO_VCC_CFG1 0xFF73
721#define LDO_VCC_REF_TUNE_MASK 0x30
722#define LDO_VCC_REF_1V2 0x20
723#define LDO_VCC_TUNE_MASK 0x07
724#define LDO_VCC_1V8 0x04
725#define LDO_VCC_3V3 0x07
726#define LDO_VCC_LMT_EN 0x08
727/*RTS5260*/
728#define LDO_POW_SDVDD1_MASK 0x08
729#define LDO_POW_SDVDD1_ON 0x08
730#define LDO_POW_SDVDD1_OFF 0x00
731
732#define LDO_VIO_CFG 0xFF75
733#define LDO_VIO_SR_MASK 0xC0
734#define LDO_VIO_SR_DF 0x40
735#define LDO_VIO_REF_TUNE_MASK 0x30
736#define LDO_VIO_REF_1V2 0x20
737#define LDO_VIO_TUNE_MASK 0x07
738#define LDO_VIO_1V7 0x03
739#define LDO_VIO_1V8 0x04
740#define LDO_VIO_3V3 0x07
741
742#define LDO_DV12S_CFG 0xFF76
743#define LDO_REF12_TUNE_MASK 0x18
744#define LDO_REF12_TUNE_DF 0x10
745#define LDO_D12_TUNE_MASK 0x07
746#define LDO_D12_TUNE_DF 0x04
747
748#define LDO_AV12S_CFG 0xFF77
749#define LDO_AV12S_TUNE_MASK 0x07
750#define LDO_AV12S_TUNE_DF 0x04
751
752#define SD40_LDO_CTL1 0xFE7D
753#define SD40_VIO_TUNE_MASK 0x70
754#define SD40_VIO_TUNE_1V7 0x30
755#define SD_VIO_LDO_1V8 0x40
756#define SD_VIO_LDO_3V3 0x70
757
758#define RTS5260_AUTOLOAD_CFG4 0xFF7F
759#define RTS5260_MIMO_DISABLE 0x8A
760
761#define RTS5260_REG_GPIO_CTL0 0xFC1A
762#define RTS5260_REG_GPIO_MASK 0x01
763#define RTS5260_REG_GPIO_ON 0x01
764#define RTS5260_REG_GPIO_OFF 0x00
765
766#define PWR_GLOBAL_CTRL 0xF200
767#define PCIE_L1_2_EN 0x0C
768#define PCIE_L1_1_EN 0x0A
769#define PCIE_L1_0_EN 0x09
770#define PWR_FE_CTL 0xF201
771#define PCIE_L1_2_PD_FE_EN 0x0C
772#define PCIE_L1_1_PD_FE_EN 0x0A
773#define PCIE_L1_0_PD_FE_EN 0x09
774#define CFG_PCIE_APHY_OFF_0 0xF204
775#define CFG_PCIE_APHY_OFF_0_DEFAULT 0xBF
776#define CFG_PCIE_APHY_OFF_1 0xF205
777#define CFG_PCIE_APHY_OFF_1_DEFAULT 0xFF
778#define CFG_PCIE_APHY_OFF_2 0xF206
779#define CFG_PCIE_APHY_OFF_2_DEFAULT 0x01
780#define CFG_PCIE_APHY_OFF_3 0xF207
781#define CFG_PCIE_APHY_OFF_3_DEFAULT 0x00
782#define CFG_L1_0_PCIE_MAC_RET_VALUE 0xF20C
783#define CFG_L1_0_PCIE_DPHY_RET_VALUE 0xF20E
784#define CFG_L1_0_SYS_RET_VALUE 0xF210
785#define CFG_L1_0_CRC_MISC_RET_VALUE 0xF212
786#define CFG_L1_0_CRC_SD30_RET_VALUE 0xF214
787#define CFG_L1_0_CRC_SD40_RET_VALUE 0xF216
788#define CFG_LP_FPWM_VALUE 0xF219
789#define CFG_LP_FPWM_VALUE_DEFAULT 0x18
790#define PWC_CDR 0xF253
791#define PWC_CDR_DEFAULT 0x03
792#define CFG_L1_0_RET_VALUE_DEFAULT 0x1B
793#define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT 0x0C
794
795/* OCPCTL */
796#define SD_DETECT_EN 0x08
797#define SD_OCP_INT_EN 0x04
798#define SD_OCP_INT_CLR 0x02
799#define SD_OC_CLR 0x01
800
801#define SDVIO_DETECT_EN (1 << 7)
802#define SDVIO_OCP_INT_EN (1 << 6)
803#define SDVIO_OCP_INT_CLR (1 << 5)
804#define SDVIO_OC_CLR (1 << 4)
805
806/* OCPSTAT */
807#define SD_OCP_DETECT 0x08
808#define SD_OC_NOW 0x04
809#define SD_OC_EVER 0x02
810
811#define SDVIO_OC_NOW (1 << 6)
812#define SDVIO_OC_EVER (1 << 5)
813
814#define REG_OCPCTL 0xFD6A
815#define REG_OCPSTAT 0xFD6E
816#define REG_OCPGLITCH 0xFD6C
817#define REG_OCPPARA1 0xFD6B
818#define REG_OCPPARA2 0xFD6D
819
820/* rts5260 DV3318 OCP-related registers */
821#define REG_DV3318_OCPCTL 0xFD89
822#define DV3318_OCP_TIME_MASK 0xF0
823#define DV3318_DETECT_EN 0x08
824#define DV3318_OCP_INT_EN 0x04
825#define DV3318_OCP_INT_CLR 0x02
826#define DV3318_OCP_CLR 0x01
827
828#define REG_DV3318_OCPSTAT 0xFD8A
829#define DV3318_OCP_GlITCH_TIME_MASK 0xF0
830#define DV3318_OCP_DETECT 0x08
831#define DV3318_OCP_NOW 0x04
832#define DV3318_OCP_EVER 0x02
833
834#define SD_OCP_GLITCH_MASK 0x0F
835
836/* OCPPARA1 */
837#define SDVIO_OCP_TIME_60 0x00
838#define SDVIO_OCP_TIME_100 0x10
839#define SDVIO_OCP_TIME_200 0x20
840#define SDVIO_OCP_TIME_400 0x30
841#define SDVIO_OCP_TIME_600 0x40
842#define SDVIO_OCP_TIME_800 0x50
843#define SDVIO_OCP_TIME_1100 0x60
844#define SDVIO_OCP_TIME_MASK 0x70
845
846#define SD_OCP_TIME_60 0x00
847#define SD_OCP_TIME_100 0x01
848#define SD_OCP_TIME_200 0x02
849#define SD_OCP_TIME_400 0x03
850#define SD_OCP_TIME_600 0x04
851#define SD_OCP_TIME_800 0x05
852#define SD_OCP_TIME_1100 0x06
853#define SD_OCP_TIME_MASK 0x07
854
855/* OCPPARA2 */
856#define SDVIO_OCP_THD_190 0x00
857#define SDVIO_OCP_THD_250 0x10
858#define SDVIO_OCP_THD_320 0x20
859#define SDVIO_OCP_THD_380 0x30
860#define SDVIO_OCP_THD_440 0x40
861#define SDVIO_OCP_THD_500 0x50
862#define SDVIO_OCP_THD_570 0x60
863#define SDVIO_OCP_THD_630 0x70
864#define SDVIO_OCP_THD_MASK 0x70
865
866#define SD_OCP_THD_450 0x00
867#define SD_OCP_THD_550 0x01
868#define SD_OCP_THD_650 0x02
869#define SD_OCP_THD_750 0x03
870#define SD_OCP_THD_850 0x04
871#define SD_OCP_THD_950 0x05
872#define SD_OCP_THD_1050 0x06
873#define SD_OCP_THD_1150 0x07
874#define SD_OCP_THD_MASK 0x07
875
876#define SDVIO_OCP_GLITCH_MASK 0xF0
877#define SDVIO_OCP_GLITCH_NONE 0x00
878#define SDVIO_OCP_GLITCH_50U 0x10
879#define SDVIO_OCP_GLITCH_100U 0x20
880#define SDVIO_OCP_GLITCH_200U 0x30
881#define SDVIO_OCP_GLITCH_600U 0x40
882#define SDVIO_OCP_GLITCH_800U 0x50
883#define SDVIO_OCP_GLITCH_1M 0x60
884#define SDVIO_OCP_GLITCH_2M 0x70
885#define SDVIO_OCP_GLITCH_3M 0x80
886#define SDVIO_OCP_GLITCH_4M 0x90
887#define SDVIO_OCP_GLIVCH_5M 0xA0
888#define SDVIO_OCP_GLITCH_6M 0xB0
889#define SDVIO_OCP_GLITCH_7M 0xC0
890#define SDVIO_OCP_GLITCH_8M 0xD0
891#define SDVIO_OCP_GLITCH_9M 0xE0
892#define SDVIO_OCP_GLITCH_10M 0xF0
893
894#define SD_OCP_GLITCH_MASK 0x0F
895#define SD_OCP_GLITCH_NONE 0x00
896#define SD_OCP_GLITCH_50U 0x01
897#define SD_OCP_GLITCH_100U 0x02
898#define SD_OCP_GLITCH_200U 0x03
899#define SD_OCP_GLITCH_600U 0x04
900#define SD_OCP_GLITCH_800U 0x05
901#define SD_OCP_GLITCH_1M 0x06
902#define SD_OCP_GLITCH_2M 0x07
903#define SD_OCP_GLITCH_3M 0x08
904#define SD_OCP_GLITCH_4M 0x09
905#define SD_OCP_GLIVCH_5M 0x0A
906#define SD_OCP_GLITCH_6M 0x0B
907#define SD_OCP_GLITCH_7M 0x0C
908#define SD_OCP_GLITCH_8M 0x0D
909#define SD_OCP_GLITCH_9M 0x0E
910#define SD_OCP_GLITCH_10M 0x0F
911
912/* Phy register */
913#define PHY_PCR 0x00
914#define PHY_PCR_FORCE_CODE 0xB000
915#define PHY_PCR_OOBS_CALI_50 0x0800
916#define PHY_PCR_OOBS_VCM_08 0x0200
917#define PHY_PCR_OOBS_SEN_90 0x0040
918#define PHY_PCR_RSSI_EN 0x0002
919#define PHY_PCR_RX10K 0x0001
920
921#define PHY_RCR0 0x01
922#define PHY_RCR1 0x02
923#define PHY_RCR1_ADP_TIME_4 0x0400
924#define PHY_RCR1_VCO_COARSE 0x001F
925#define PHY_RCR1_INIT_27S 0x0A1F
926#define PHY_SSCCR2 0x02
927#define PHY_SSCCR2_PLL_NCODE 0x0A00
928#define PHY_SSCCR2_TIME0 0x001C
929#define PHY_SSCCR2_TIME2_WIDTH 0x0003
930
931#define PHY_RCR2 0x03
932#define PHY_RCR2_EMPHASE_EN 0x8000
933#define PHY_RCR2_NADJR 0x4000
934#define PHY_RCR2_CDR_SR_2 0x0100
935#define PHY_RCR2_FREQSEL_12 0x0040
936#define PHY_RCR2_CDR_SC_12P 0x0010
937#define PHY_RCR2_CALIB_LATE 0x0002
938#define PHY_RCR2_INIT_27S 0xC152
939#define PHY_SSCCR3 0x03
940#define PHY_SSCCR3_STEP_IN 0x2740
941#define PHY_SSCCR3_CHECK_DELAY 0x0008
942#define _PHY_ANA03 0x03
943#define _PHY_ANA03_TIMER_MAX 0x2700
944#define _PHY_ANA03_OOBS_DEB_EN 0x0040
945#define _PHY_CMU_DEBUG_EN 0x0008
946
947#define PHY_RTCR 0x04
948#define PHY_RDR 0x05
949#define PHY_RDR_RXDSEL_1_9 0x4000
950#define PHY_SSC_AUTO_PWD 0x0600
951#define PHY_TCR0 0x06
952#define PHY_TCR1 0x07
953#define PHY_TUNE 0x08
954#define PHY_TUNE_TUNEREF_1_0 0x4000
955#define PHY_TUNE_VBGSEL_1252 0x0C00
956#define PHY_TUNE_SDBUS_33 0x0200
957#define PHY_TUNE_TUNED18 0x01C0
958#define PHY_TUNE_TUNED12 0X0020
959#define PHY_TUNE_TUNEA12 0x0004
960#define PHY_TUNE_VOLTAGE_MASK 0xFC3F
961#define PHY_TUNE_VOLTAGE_3V3 0x03C0
962#define PHY_TUNE_D18_1V8 0x0100
963#define PHY_TUNE_D18_1V7 0x0080
964#define PHY_ANA08 0x08
965#define PHY_ANA08_RX_EQ_DCGAIN 0x5000
966#define PHY_ANA08_SEL_RX_EN 0x0400
967#define PHY_ANA08_RX_EQ_VAL 0x03C0
968#define PHY_ANA08_SCP 0x0020
969#define PHY_ANA08_SEL_IPI 0x0004
970
971#define PHY_IMR 0x09
972#define PHY_BPCR 0x0A
973#define PHY_BPCR_IBRXSEL 0x0400
974#define PHY_BPCR_IBTXSEL 0x0100
975#define PHY_BPCR_IB_FILTER 0x0080
976#define PHY_BPCR_CMIRROR_EN 0x0040
977
978#define PHY_BIST 0x0B
979#define PHY_RAW_L 0x0C
980#define PHY_RAW_H 0x0D
981#define PHY_RAW_DATA 0x0E
982#define PHY_HOST_CLK_CTRL 0x0F
983#define PHY_DMR 0x10
984#define PHY_BACR 0x11
985#define PHY_BACR_BASIC_MASK 0xFFF3
986#define PHY_IER 0x12
987#define PHY_BCSR 0x13
988#define PHY_BPR 0x14
989#define PHY_BPNR2 0x15
990#define PHY_BPNR 0x16
991#define PHY_BRNR2 0x17
992#define PHY_BENR 0x18
993#define PHY_REV 0x19
994#define PHY_REV_RESV 0xE000
995#define PHY_REV_RXIDLE_LATCHED 0x1000
996#define PHY_REV_P1_EN 0x0800
997#define PHY_REV_RXIDLE_EN 0x0400
998#define PHY_REV_CLKREQ_TX_EN 0x0200
999#define PHY_REV_CLKREQ_RX_EN 0x0100
1000#define PHY_REV_CLKREQ_DT_1_0 0x0040
1001#define PHY_REV_STOP_CLKRD 0x0020
1002#define PHY_REV_RX_PWST 0x0008
1003#define PHY_REV_STOP_CLKWR 0x0004
1004#define _PHY_REV0 0x19
1005#define _PHY_REV0_FILTER_OUT 0x3800
1006#define _PHY_REV0_CDR_BYPASS_PFD 0x0100
1007#define _PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002
1008
1009#define PHY_FLD0 0x1A
1010#define PHY_ANA1A 0x1A
1011#define PHY_ANA1A_TXR_LOOPBACK 0x2000
1012#define PHY_ANA1A_RXT_BIST 0x0500
1013#define PHY_ANA1A_TXR_BIST 0x0040
1014#define PHY_ANA1A_REV 0x0006
1015#define PHY_FLD0_INIT_27S 0x2546
1016#define PHY_FLD1 0x1B
1017#define PHY_FLD2 0x1C
1018#define PHY_FLD3 0x1D
1019#define PHY_FLD3_TIMER_4 0x0800
1020#define PHY_FLD3_TIMER_6 0x0020
1021#define PHY_FLD3_RXDELINK 0x0004
1022#define PHY_FLD3_INIT_27S 0x0004
1023#define PHY_ANA1D 0x1D
1024#define PHY_ANA1D_DEBUG_ADDR 0x0004
1025#define _PHY_FLD0 0x1D
1026#define _PHY_FLD0_CLK_REQ_20C 0x8000
1027#define _PHY_FLD0_RX_IDLE_EN 0x1000
1028#define _PHY_FLD0_BIT_ERR_RSTN 0x0800
1029#define _PHY_FLD0_BER_COUNT 0x01E0
1030#define _PHY_FLD0_BER_TIMER 0x001E
1031#define _PHY_FLD0_CHECK_EN 0x0001
1032
1033#define PHY_FLD4 0x1E
1034#define PHY_FLD4_FLDEN_SEL 0x4000
1035#define PHY_FLD4_REQ_REF 0x2000
1036#define PHY_FLD4_RXAMP_OFF 0x1000
1037#define PHY_FLD4_REQ_ADDA 0x0800
1038#define PHY_FLD4_BER_COUNT 0x00E0
1039#define PHY_FLD4_BER_TIMER 0x000A
1040#define PHY_FLD4_BER_CHK_EN 0x0001
1041#define PHY_FLD4_INIT_27S 0x5C7F
1042#define PHY_DIG1E 0x1E
1043#define PHY_DIG1E_REV 0x4000
1044#define PHY_DIG1E_D0_X_D1 0x1000
1045#define PHY_DIG1E_RX_ON_HOST 0x0800
1046#define PHY_DIG1E_RCLK_REF_HOST 0x0400
1047#define PHY_DIG1E_RCLK_TX_EN_KEEP 0x0040
1048#define PHY_DIG1E_RCLK_TX_TERM_KEEP 0x0020
1049#define PHY_DIG1E_RCLK_RX_EIDLE_ON 0x0010
1050#define PHY_DIG1E_TX_TERM_KEEP 0x0008
1051#define PHY_DIG1E_RX_TERM_KEEP 0x0004
1052#define PHY_DIG1E_TX_EN_KEEP 0x0002
1053#define PHY_DIG1E_RX_EN_KEEP 0x0001
1054#define PHY_DUM_REG 0x1F
1055
1056#define PCR_ASPM_SETTING_REG1 0x160
1057#define PCR_ASPM_SETTING_REG2 0x168
1058#define PCR_ASPM_SETTING_5260 0x178
1059
1060#define PCR_SETTING_REG1 0x724
1061#define PCR_SETTING_REG2 0x814
1062#define PCR_SETTING_REG3 0x747
1063
1064#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
1065
1066#define RTS5227_DEVICE_ID 0x5227
1067#define RTS_MAX_TIMES_FREQ_REDUCTION 8
1068
1069struct rtsx_pcr;
1070
1071struct pcr_handle {
1072 struct rtsx_pcr *pcr;
1073};
1074
1075struct pcr_ops {
1076 int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
1077 int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1078 int (*extra_init_hw)(struct rtsx_pcr *pcr);
1079 int (*optimize_phy)(struct rtsx_pcr *pcr);
1080 int (*turn_on_led)(struct rtsx_pcr *pcr);
1081 int (*turn_off_led)(struct rtsx_pcr *pcr);
1082 int (*enable_auto_blink)(struct rtsx_pcr *pcr);
1083 int (*disable_auto_blink)(struct rtsx_pcr *pcr);
1084 int (*card_power_on)(struct rtsx_pcr *pcr, int card);
1085 int (*card_power_off)(struct rtsx_pcr *pcr, int card);
1086 int (*switch_output_voltage)(struct rtsx_pcr *pcr,
1087 u8 voltage);
1088 unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr);
1089 int (*conv_clk_and_div_n)(int clk, int dir);
1090 void (*fetch_vendor_settings)(struct rtsx_pcr *pcr);
1091 void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
1092 void (*stop_cmd)(struct rtsx_pcr *pcr);
1093
1094 void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
1095 int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
1096 int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
1097 void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
1098 void (*full_on)(struct rtsx_pcr *pcr);
1099 void (*power_saving)(struct rtsx_pcr *pcr);
1100 void (*enable_ocp)(struct rtsx_pcr *pcr);
1101 void (*disable_ocp)(struct rtsx_pcr *pcr);
1102 void (*init_ocp)(struct rtsx_pcr *pcr);
1103 void (*process_ocp)(struct rtsx_pcr *pcr);
1104 int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
1105 void (*clear_ocpstat)(struct rtsx_pcr *pcr);
1106};
1107
1108enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN};
1109
1110#define ASPM_L1_1_EN_MASK BIT(3)
1111#define ASPM_L1_2_EN_MASK BIT(2)
1112#define PM_L1_1_EN_MASK BIT(1)
1113#define PM_L1_2_EN_MASK BIT(0)
1114
1115#define ASPM_L1_1_EN BIT(0)
1116#define ASPM_L1_2_EN BIT(1)
1117#define PM_L1_1_EN BIT(2)
1118#define PM_L1_2_EN BIT(3)
1119#define LTR_L1SS_PWR_GATE_EN BIT(4)
1120#define L1_SNOOZE_TEST_EN BIT(5)
1121#define LTR_L1SS_PWR_GATE_CHECK_CARD_EN BIT(6)
1122
1123enum dev_aspm_mode {
1124 DEV_ASPM_DYNAMIC,
1125 DEV_ASPM_BACKDOOR,
1126 DEV_ASPM_STATIC,
1127 DEV_ASPM_DISABLE,
1128};
1129
1130/*
1131 * struct rtsx_cr_option - card reader option
1132 * @dev_flags: device flags
1133 * @force_clkreq_0: force clock request
1134 * @ltr_en: enable ltr mode flag
1135 * @ltr_enabled: ltr mode in configure space flag
1136 * @ltr_active: ltr mode status
1137 * @ltr_active_latency: ltr mode active latency
1138 * @ltr_idle_latency: ltr mode idle latency
1139 * @ltr_l1off_latency: ltr mode l1off latency
1140 * @dev_aspm_mode: device aspm mode
1141 * @l1_snooze_delay: l1 snooze delay
1142 * @ltr_l1off_sspwrgate: ltr l1off sspwrgate
1143 * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
1144 * @ocp_en: enable ocp flag
1145 * @sd_400mA_ocp_thd: 400mA ocp thd
1146 * @sd_800mA_ocp_thd: 800mA ocp thd
1147 */
1148struct rtsx_cr_option {
1149 u32 dev_flags;
1150 bool force_clkreq_0;
1151 bool ltr_en;
1152 bool ltr_enabled;
1153 bool ltr_active;
1154 u32 ltr_active_latency;
1155 u32 ltr_idle_latency;
1156 u32 ltr_l1off_latency;
1157 enum dev_aspm_mode dev_aspm_mode;
1158 u32 l1_snooze_delay;
1159 u8 ltr_l1off_sspwrgate;
1160 u8 ltr_l1off_snooze_sspwrgate;
1161 bool ocp_en;
1162 u8 sd_400mA_ocp_thd;
1163 u8 sd_800mA_ocp_thd;
1164};
1165
1166/*
1167 * struct rtsx_hw_param - card reader hardware param
1168 * @interrupt_en: indicate which interrutp enable
1169 * @ocp_glitch: ocp glitch time
1170 */
1171struct rtsx_hw_param {
1172 u32 interrupt_en;
1173 u8 ocp_glitch;
1174};
1175
1176#define rtsx_set_dev_flag(cr, flag) \
1177 ((cr)->option.dev_flags |= (flag))
1178#define rtsx_clear_dev_flag(cr, flag) \
1179 ((cr)->option.dev_flags &= ~(flag))
1180#define rtsx_check_dev_flag(cr, flag) \
1181 ((cr)->option.dev_flags & (flag))
1182
1183struct rtsx_pcr {
1184 struct pci_dev *pci;
1185 unsigned int id;
1186 int pcie_cap;
1187 struct rtsx_cr_option option;
1188 struct rtsx_hw_param hw_param;
1189
1190 /* pci resources */
1191 unsigned long addr;
1192 void __iomem *remap_addr;
1193 int irq;
1194
1195 /* host reserved buffer */
1196 void *rtsx_resv_buf;
1197 dma_addr_t rtsx_resv_buf_addr;
1198
1199 void *host_cmds_ptr;
1200 dma_addr_t host_cmds_addr;
1201 int ci;
1202
1203 void *host_sg_tbl_ptr;
1204 dma_addr_t host_sg_tbl_addr;
1205 int sgi;
1206
1207 u32 bier;
1208 char trans_result;
1209
1210 unsigned int card_inserted;
1211 unsigned int card_removed;
1212 unsigned int card_exist;
1213
1214 struct delayed_work carddet_work;
1215 struct delayed_work idle_work;
1216
1217 spinlock_t lock;
1218 struct mutex pcr_mutex;
1219 struct completion *done;
1220 struct completion *finish_me;
1221
1222 unsigned int cur_clock;
1223 bool remove_pci;
1224 bool msi_en;
1225
1226#define EXTRA_CAPS_SD_SDR50 (1 << 0)
1227#define EXTRA_CAPS_SD_SDR104 (1 << 1)
1228#define EXTRA_CAPS_SD_DDR50 (1 << 2)
1229#define EXTRA_CAPS_MMC_HSDDR (1 << 3)
1230#define EXTRA_CAPS_MMC_HS200 (1 << 4)
1231#define EXTRA_CAPS_MMC_8BIT (1 << 5)
1232 u32 extra_caps;
1233
1234#define IC_VER_A 0
1235#define IC_VER_B 1
1236#define IC_VER_C 2
1237#define IC_VER_D 3
1238 u8 ic_version;
1239
1240 u8 sd30_drive_sel_1v8;
1241 u8 sd30_drive_sel_3v3;
1242 u8 card_drive_sel;
1243#define ASPM_L1_EN 0x02
1244 u8 aspm_en;
1245 bool aspm_enabled;
1246
1247#define PCR_MS_PMOS (1 << 0)
1248#define PCR_REVERSE_SOCKET (1 << 1)
1249 u32 flags;
1250
1251 u32 tx_initial_phase;
1252 u32 rx_initial_phase;
1253
1254 const u32 *sd_pull_ctl_enable_tbl;
1255 const u32 *sd_pull_ctl_disable_tbl;
1256 const u32 *ms_pull_ctl_enable_tbl;
1257 const u32 *ms_pull_ctl_disable_tbl;
1258
1259 const struct pcr_ops *ops;
1260 enum PDEV_STAT state;
1261
1262 u16 reg_pm_ctrl3;
1263
1264 int num_slots;
1265 struct rtsx_slot *slots;
1266
1267 u8 dma_error_count;
1268 u8 ocp_stat;
1269 u8 ocp_stat2;
1270};
1271
1272#define PID_524A 0x524A
1273#define PID_5249 0x5249
1274#define PID_5250 0x5250
1275#define PID_525A 0x525A
1276#define PID_5260 0x5260
1277
1278#define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid))
1279#define PCI_VID(pcr) ((pcr)->pci->vendor)
1280#define PCI_PID(pcr) ((pcr)->pci->device)
1281#define is_version(pcr, pid, ver) \
1282 (CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
1283#define pcr_dbg(pcr, fmt, arg...) \
1284 dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
1285
1286#define SDR104_PHASE(val) ((val) & 0xFF)
1287#define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
1288#define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
1289#define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
1290#define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
1291#define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
1292#define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
1293#define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
1294#define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
1295#define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
1296 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
1297
1298void rtsx_pci_start_run(struct rtsx_pcr *pcr);
1299int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
1300int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
1301int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
1302int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1303void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
1304void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1305 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
1306void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
1307int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
1308int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1309 int num_sg, bool read, int timeout);
1310int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1311 int num_sg, bool read);
1312void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1313 int num_sg, bool read);
1314int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1315 int count, bool read, int timeout);
1316int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1317int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1318int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
1319int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
1320int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
1321 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
1322int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
1323int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
1324int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
1325int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
1326unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
1327void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
1328
1329static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
1330{
1331 return (u8 *)(pcr->host_cmds_ptr);
1332}
1333
1334static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
1335 u8 mask, u8 append)
1336{
1337 int err;
1338 u8 val;
1339
1340 err = pci_read_config_byte(pcr->pci, addr, &val);
1341 if (err < 0)
1342 return err;
1343 return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
1344}
1345
1346static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
1347{
1348 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24);
1349 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
1350 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
1351 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
1352}
1353
1354static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
1355 u16 mask, u16 append)
1356{
1357 int err;
1358 u16 val;
1359
1360 err = rtsx_pci_read_phy_register(pcr, addr, &val);
1361 if (err < 0)
1362 return err;
1363
1364 return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
1365}
1366
1367#endif
1368