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1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
4 *
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 *
7 * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
8 *
9 * Adapted from:
10 *
11 * Internal header file for MX1ADS serial ports (UART1 & 2)
12 *
13 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
14 */
15
16#ifndef __ASM_ARM_REGS_SERIAL_H
17#define __ASM_ARM_REGS_SERIAL_H
18
19#define S3C2410_URXH (0x24)
20#define S3C2410_UTXH (0x20)
21#define S3C2410_ULCON (0x00)
22#define S3C2410_UCON (0x04)
23#define S3C2410_UFCON (0x08)
24#define S3C2410_UMCON (0x0C)
25#define S3C2410_UBRDIV (0x28)
26#define S3C2410_UTRSTAT (0x10)
27#define S3C2410_UERSTAT (0x14)
28#define S3C2410_UFSTAT (0x18)
29#define S3C2410_UMSTAT (0x1C)
30
31#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
32
33#define S3C2410_LCON_CS5 (0x0)
34#define S3C2410_LCON_CS6 (0x1)
35#define S3C2410_LCON_CS7 (0x2)
36#define S3C2410_LCON_CS8 (0x3)
37#define S3C2410_LCON_CSMASK (0x3)
38
39#define S3C2410_LCON_PNONE (0x0)
40#define S3C2410_LCON_PEVEN (0x5 << 3)
41#define S3C2410_LCON_PODD (0x4 << 3)
42#define S3C2410_LCON_PMASK (0x7 << 3)
43
44#define S3C2410_LCON_STOPB (1<<2)
45#define S3C2410_LCON_IRM (1<<6)
46
47#define S3C2440_UCON_CLKMASK (3<<10)
48#define S3C2440_UCON_CLKSHIFT (10)
49#define S3C2440_UCON_PCLK (0<<10)
50#define S3C2440_UCON_UCLK (1<<10)
51#define S3C2440_UCON_PCLK2 (2<<10)
52#define S3C2440_UCON_FCLK (3<<10)
53#define S3C2443_UCON_EPLL (3<<10)
54
55#define S3C6400_UCON_CLKMASK (3<<10)
56#define S3C6400_UCON_CLKSHIFT (10)
57#define S3C6400_UCON_PCLK (0<<10)
58#define S3C6400_UCON_PCLK2 (2<<10)
59#define S3C6400_UCON_UCLK0 (1<<10)
60#define S3C6400_UCON_UCLK1 (3<<10)
61
62#define S3C2440_UCON2_FCLK_EN (1<<15)
63#define S3C2440_UCON0_DIVMASK (15 << 12)
64#define S3C2440_UCON1_DIVMASK (15 << 12)
65#define S3C2440_UCON2_DIVMASK (7 << 12)
66#define S3C2440_UCON_DIVSHIFT (12)
67
68#define S3C2412_UCON_CLKMASK (3<<10)
69#define S3C2412_UCON_CLKSHIFT (10)
70#define S3C2412_UCON_UCLK (1<<10)
71#define S3C2412_UCON_USYSCLK (3<<10)
72#define S3C2412_UCON_PCLK (0<<10)
73#define S3C2412_UCON_PCLK2 (2<<10)
74
75#define S3C2410_UCON_CLKMASK (1 << 10)
76#define S3C2410_UCON_CLKSHIFT (10)
77#define S3C2410_UCON_UCLK (1<<10)
78#define S3C2410_UCON_SBREAK (1<<4)
79
80#define S3C2410_UCON_TXILEVEL (1<<9)
81#define S3C2410_UCON_RXILEVEL (1<<8)
82#define S3C2410_UCON_TXIRQMODE (1<<2)
83#define S3C2410_UCON_RXIRQMODE (1<<0)
84#define S3C2410_UCON_RXFIFO_TOI (1<<7)
85#define S3C2443_UCON_RXERR_IRQEN (1<<6)
86#define S3C2443_UCON_LOOPBACK (1<<5)
87
88#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
89 S3C2410_UCON_RXILEVEL | \
90 S3C2410_UCON_TXIRQMODE | \
91 S3C2410_UCON_RXIRQMODE | \
92 S3C2410_UCON_RXFIFO_TOI)
93
94#define S3C64XX_UCON_TXBURST_1 (0<<20)
95#define S3C64XX_UCON_TXBURST_4 (1<<20)
96#define S3C64XX_UCON_TXBURST_8 (2<<20)
97#define S3C64XX_UCON_TXBURST_16 (3<<20)
98#define S3C64XX_UCON_TXBURST_MASK (0xf<<20)
99#define S3C64XX_UCON_RXBURST_1 (0<<16)
100#define S3C64XX_UCON_RXBURST_4 (1<<16)
101#define S3C64XX_UCON_RXBURST_8 (2<<16)
102#define S3C64XX_UCON_RXBURST_16 (3<<16)
103#define S3C64XX_UCON_RXBURST_MASK (0xf<<16)
104#define S3C64XX_UCON_TIMEOUT_SHIFT (12)
105#define S3C64XX_UCON_TIMEOUT_MASK (0xf<<12)
106#define S3C64XX_UCON_EMPTYINT_EN (1<<11)
107#define S3C64XX_UCON_DMASUS_EN (1<<10)
108#define S3C64XX_UCON_TXINT_LEVEL (1<<9)
109#define S3C64XX_UCON_RXINT_LEVEL (1<<8)
110#define S3C64XX_UCON_TIMEOUT_EN (1<<7)
111#define S3C64XX_UCON_ERRINT_EN (1<<6)
112#define S3C64XX_UCON_TXMODE_DMA (2<<2)
113#define S3C64XX_UCON_TXMODE_CPU (1<<2)
114#define S3C64XX_UCON_TXMODE_MASK (3<<2)
115#define S3C64XX_UCON_RXMODE_DMA (2<<0)
116#define S3C64XX_UCON_RXMODE_CPU (1<<0)
117#define S3C64XX_UCON_RXMODE_MASK (3<<0)
118
119#define S3C2410_UFCON_FIFOMODE (1<<0)
120#define S3C2410_UFCON_TXTRIG0 (0<<6)
121#define S3C2410_UFCON_RXTRIG8 (1<<4)
122#define S3C2410_UFCON_RXTRIG12 (2<<4)
123
124/* S3C2440 FIFO trigger levels */
125#define S3C2440_UFCON_RXTRIG1 (0<<4)
126#define S3C2440_UFCON_RXTRIG8 (1<<4)
127#define S3C2440_UFCON_RXTRIG16 (2<<4)
128#define S3C2440_UFCON_RXTRIG32 (3<<4)
129
130#define S3C2440_UFCON_TXTRIG0 (0<<6)
131#define S3C2440_UFCON_TXTRIG16 (1<<6)
132#define S3C2440_UFCON_TXTRIG32 (2<<6)
133#define S3C2440_UFCON_TXTRIG48 (3<<6)
134
135#define S3C2410_UFCON_RESETBOTH (3<<1)
136#define S3C2410_UFCON_RESETTX (1<<2)
137#define S3C2410_UFCON_RESETRX (1<<1)
138
139#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
140 S3C2410_UFCON_TXTRIG0 | \
141 S3C2410_UFCON_RXTRIG8 )
142
143#define S3C2410_UMCOM_AFC (1<<4)
144#define S3C2410_UMCOM_RTS_LOW (1<<0)
145
146#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
147#define S3C2412_UMCON_AFC_56 (1<<5)
148#define S3C2412_UMCON_AFC_48 (2<<5)
149#define S3C2412_UMCON_AFC_40 (3<<5)
150#define S3C2412_UMCON_AFC_32 (4<<5)
151#define S3C2412_UMCON_AFC_24 (5<<5)
152#define S3C2412_UMCON_AFC_16 (6<<5)
153#define S3C2412_UMCON_AFC_8 (7<<5)
154
155#define S3C2410_UFSTAT_TXFULL (1<<9)
156#define S3C2410_UFSTAT_RXFULL (1<<8)
157#define S3C2410_UFSTAT_TXMASK (15<<4)
158#define S3C2410_UFSTAT_TXSHIFT (4)
159#define S3C2410_UFSTAT_RXMASK (15<<0)
160#define S3C2410_UFSTAT_RXSHIFT (0)
161
162/* UFSTAT S3C2443 same as S3C2440 */
163#define S3C2440_UFSTAT_TXFULL (1<<14)
164#define S3C2440_UFSTAT_RXFULL (1<<6)
165#define S3C2440_UFSTAT_TXSHIFT (8)
166#define S3C2440_UFSTAT_RXSHIFT (0)
167#define S3C2440_UFSTAT_TXMASK (63<<8)
168#define S3C2440_UFSTAT_RXMASK (63)
169
170#define S3C2410_UTRSTAT_TIMEOUT (1<<3)
171#define S3C2410_UTRSTAT_TXE (1<<2)
172#define S3C2410_UTRSTAT_TXFE (1<<1)
173#define S3C2410_UTRSTAT_RXDR (1<<0)
174
175#define S3C2410_UERSTAT_OVERRUN (1<<0)
176#define S3C2410_UERSTAT_FRAME (1<<2)
177#define S3C2410_UERSTAT_BREAK (1<<3)
178#define S3C2443_UERSTAT_PARITY (1<<1)
179
180#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
181 S3C2410_UERSTAT_FRAME | \
182 S3C2410_UERSTAT_BREAK)
183
184#define S3C2410_UMSTAT_CTS (1<<0)
185#define S3C2410_UMSTAT_DeltaCTS (1<<2)
186
187#define S3C2443_DIVSLOT (0x2C)
188
189/* S3C64XX interrupt registers. */
190#define S3C64XX_UINTP 0x30
191#define S3C64XX_UINTSP 0x34
192#define S3C64XX_UINTM 0x38
193
194#define S3C64XX_UINTM_RXD (0)
195#define S3C64XX_UINTM_ERROR (1)
196#define S3C64XX_UINTM_TXD (2)
197#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
198#define S3C64XX_UINTM_ERR_MSK (1 << S3C64XX_UINTM_ERROR)
199#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
200
201/* Following are specific to S5PV210 */
202#define S5PV210_UCON_CLKMASK (1<<10)
203#define S5PV210_UCON_CLKSHIFT (10)
204#define S5PV210_UCON_PCLK (0<<10)
205#define S5PV210_UCON_UCLK (1<<10)
206
207#define S5PV210_UFCON_TXTRIG0 (0<<8)
208#define S5PV210_UFCON_TXTRIG4 (1<<8)
209#define S5PV210_UFCON_TXTRIG8 (2<<8)
210#define S5PV210_UFCON_TXTRIG16 (3<<8)
211#define S5PV210_UFCON_TXTRIG32 (4<<8)
212#define S5PV210_UFCON_TXTRIG64 (5<<8)
213#define S5PV210_UFCON_TXTRIG128 (6<<8)
214#define S5PV210_UFCON_TXTRIG256 (7<<8)
215
216#define S5PV210_UFCON_RXTRIG1 (0<<4)
217#define S5PV210_UFCON_RXTRIG4 (1<<4)
218#define S5PV210_UFCON_RXTRIG8 (2<<4)
219#define S5PV210_UFCON_RXTRIG16 (3<<4)
220#define S5PV210_UFCON_RXTRIG32 (4<<4)
221#define S5PV210_UFCON_RXTRIG64 (5<<4)
222#define S5PV210_UFCON_RXTRIG128 (6<<4)
223#define S5PV210_UFCON_RXTRIG256 (7<<4)
224
225#define S5PV210_UFSTAT_TXFULL (1<<24)
226#define S5PV210_UFSTAT_RXFULL (1<<8)
227#define S5PV210_UFSTAT_TXMASK (255<<16)
228#define S5PV210_UFSTAT_TXSHIFT (16)
229#define S5PV210_UFSTAT_RXMASK (255<<0)
230#define S5PV210_UFSTAT_RXSHIFT (0)
231
232#define S3C2410_UCON_CLKSEL0 (1 << 0)
233#define S3C2410_UCON_CLKSEL1 (1 << 1)
234#define S3C2410_UCON_CLKSEL2 (1 << 2)
235#define S3C2410_UCON_CLKSEL3 (1 << 3)
236
237/* Default values for s5pv210 UCON and UFCON uart registers */
238#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
239 S3C2410_UCON_RXILEVEL | \
240 S3C2410_UCON_TXIRQMODE | \
241 S3C2410_UCON_RXIRQMODE | \
242 S3C2410_UCON_RXFIFO_TOI | \
243 S3C2443_UCON_RXERR_IRQEN)
244
245#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
246 S5PV210_UFCON_TXTRIG4 | \
247 S5PV210_UFCON_RXTRIG4)
248
249#ifndef __ASSEMBLY__
250
251#include <linux/serial_core.h>
252
253/* configuration structure for per-machine configurations for the
254 * serial port
255 *
256 * the pointer is setup by the machine specific initialisation from the
257 * arch/arm/mach-s3c2410/ directory.
258*/
259
260struct s3c2410_uartcfg {
261 unsigned char hwport; /* hardware port number */
262 unsigned char unused;
263 unsigned short flags;
264 upf_t uart_flags; /* default uart flags */
265 unsigned int clk_sel;
266
267 unsigned int has_fracval;
268
269 unsigned long ucon; /* value of ucon for port */
270 unsigned long ulcon; /* value of ulcon for port */
271 unsigned long ufcon; /* value of ufcon for port */
272};
273
274#endif /* __ASSEMBLY__ */
275
276#endif /* __ASM_ARM_REGS_SERIAL_H */
277
278

Warning: That file was not part of the compilation database. It may have many parsing errors.