| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2010-2015 Samsung Electronics Co., Ltd. |
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| 4 | * http://www.samsung.com |
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| 5 | * |
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| 6 | * Exynos - Power management unit definition |
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| 7 | * |
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| 8 | * Notice: |
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| 9 | * This is not a list of all Exynos Power Management Unit SFRs. |
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| 10 | * There are too many of them, not mentioning subtle differences |
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| 11 | * between SoCs. For now, put here only the used registers. |
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| 12 | */ |
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| 13 | |
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| 14 | #ifndef __LINUX_SOC_EXYNOS_REGS_PMU_H |
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| 15 | #define __LINUX_SOC_EXYNOS_REGS_PMU_H __FILE__ |
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| 16 | |
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| 17 | #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200 |
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| 18 | |
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| 19 | #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) |
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| 20 | |
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| 21 | #define S5P_CENTRAL_SEQ_OPTION 0x0208 |
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| 22 | |
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| 23 | #define S5P_USE_STANDBY_WFI0 (1 << 16) |
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| 24 | #define S5P_USE_STANDBY_WFI1 (1 << 17) |
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| 25 | #define S5P_USE_STANDBY_WFI2 (1 << 19) |
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| 26 | #define S5P_USE_STANDBY_WFI3 (1 << 20) |
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| 27 | #define S5P_USE_STANDBY_WFE0 (1 << 24) |
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| 28 | #define S5P_USE_STANDBY_WFE1 (1 << 25) |
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| 29 | #define S5P_USE_STANDBY_WFE2 (1 << 27) |
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| 30 | #define S5P_USE_STANDBY_WFE3 (1 << 28) |
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| 31 | |
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| 32 | #define S5P_USE_STANDBY_WFI_ALL \ |
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| 33 | (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \ |
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| 34 | S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \ |
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| 35 | S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \ |
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| 36 | S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3) |
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| 37 | |
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| 38 | #define S5P_USE_DELAYED_RESET_ASSERTION BIT(12) |
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| 39 | |
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| 40 | #define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n) |
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| 41 | #define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28) |
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| 42 | #define EXYNOS_SWRESET 0x0400 |
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| 43 | |
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| 44 | #define S5P_WAKEUP_STAT 0x0600 |
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| 45 | /* Value for EXYNOS_EINT_WAKEUP_MASK disabling all external wakeup interrupts */ |
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| 46 | #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff |
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| 47 | #define EXYNOS_EINT_WAKEUP_MASK 0x0604 |
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| 48 | #define S5P_WAKEUP_MASK 0x0608 |
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| 49 | #define S5P_WAKEUP_MASK2 0x0614 |
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| 50 | |
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| 51 | /* MIPI_PHYn_CONTROL, valid for Exynos3250, Exynos4, Exynos5250 and Exynos5433 */ |
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| 52 | #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4) |
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| 53 | /* Phy enable bit, common for all phy registers, not only MIPI */ |
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| 54 | #define EXYNOS4_PHY_ENABLE (1 << 0) |
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| 55 | #define EXYNOS4_MIPI_PHY_SRESETN (1 << 1) |
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| 56 | #define EXYNOS4_MIPI_PHY_MRESETN (1 << 2) |
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| 57 | #define EXYNOS4_MIPI_PHY_RESET_MASK (3 << 1) |
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| 58 | |
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| 59 | #define S5P_INFORM0 0x0800 |
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| 60 | #define S5P_INFORM1 0x0804 |
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| 61 | #define S5P_INFORM5 0x0814 |
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| 62 | #define S5P_INFORM6 0x0818 |
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| 63 | #define S5P_INFORM7 0x081C |
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| 64 | #define S5P_PMU_SPARE2 0x0908 |
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| 65 | #define S5P_PMU_SPARE3 0x090C |
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| 66 | |
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| 67 | #define EXYNOS_IROM_DATA2 0x0988 |
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| 68 | #define S5P_ARM_CORE0_LOWPWR 0x1000 |
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| 69 | #define S5P_DIS_IRQ_CORE0 0x1004 |
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| 70 | #define S5P_DIS_IRQ_CENTRAL0 0x1008 |
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| 71 | #define S5P_ARM_CORE1_LOWPWR 0x1010 |
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| 72 | #define S5P_DIS_IRQ_CORE1 0x1014 |
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| 73 | #define S5P_DIS_IRQ_CENTRAL1 0x1018 |
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| 74 | #define S5P_ARM_COMMON_LOWPWR 0x1080 |
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| 75 | #define S5P_L2_0_LOWPWR 0x10C0 |
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| 76 | #define S5P_L2_1_LOWPWR 0x10C4 |
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| 77 | #define S5P_CMU_ACLKSTOP_LOWPWR 0x1100 |
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| 78 | #define S5P_CMU_SCLKSTOP_LOWPWR 0x1104 |
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| 79 | #define S5P_CMU_RESET_LOWPWR 0x110C |
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| 80 | #define S5P_APLL_SYSCLK_LOWPWR 0x1120 |
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| 81 | #define S5P_MPLL_SYSCLK_LOWPWR 0x1124 |
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| 82 | #define S5P_VPLL_SYSCLK_LOWPWR 0x1128 |
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| 83 | #define S5P_EPLL_SYSCLK_LOWPWR 0x112C |
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| 84 | #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138 |
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| 85 | #define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C |
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| 86 | #define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140 |
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| 87 | #define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144 |
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| 88 | #define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148 |
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| 89 | #define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C |
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| 90 | #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150 |
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| 91 | #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158 |
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| 92 | #define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C |
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| 93 | #define S5P_CMU_RESET_CAM_LOWPWR 0x1160 |
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| 94 | #define S5P_CMU_RESET_TV_LOWPWR 0x1164 |
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| 95 | #define S5P_CMU_RESET_MFC_LOWPWR 0x1168 |
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| 96 | #define S5P_CMU_RESET_G3D_LOWPWR 0x116C |
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| 97 | #define S5P_CMU_RESET_LCD0_LOWPWR 0x1170 |
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| 98 | #define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178 |
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| 99 | #define S5P_CMU_RESET_GPS_LOWPWR 0x117C |
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| 100 | #define S5P_TOP_BUS_LOWPWR 0x1180 |
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| 101 | #define S5P_TOP_RETENTION_LOWPWR 0x1184 |
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| 102 | #define S5P_TOP_PWR_LOWPWR 0x1188 |
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| 103 | #define S5P_LOGIC_RESET_LOWPWR 0x11A0 |
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| 104 | #define S5P_ONENAND_MEM_LOWPWR 0x11C0 |
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| 105 | #define S5P_G2D_ACP_MEM_LOWPWR 0x11C8 |
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| 106 | #define S5P_USBOTG_MEM_LOWPWR 0x11CC |
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| 107 | #define S5P_HSMMC_MEM_LOWPWR 0x11D0 |
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| 108 | #define S5P_CSSYS_MEM_LOWPWR 0x11D4 |
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| 109 | #define S5P_SECSS_MEM_LOWPWR 0x11D8 |
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| 110 | #define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200 |
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| 111 | #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204 |
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| 112 | #define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220 |
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| 113 | #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 |
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| 114 | #define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228 |
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| 115 | #define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C |
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| 116 | #define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230 |
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| 117 | #define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234 |
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| 118 | #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240 |
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| 119 | #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260 |
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| 120 | #define S5P_XUSBXTI_LOWPWR 0x1280 |
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| 121 | #define S5P_XXTI_LOWPWR 0x1284 |
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| 122 | #define S5P_EXT_REGULATOR_LOWPWR 0x12C0 |
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| 123 | #define S5P_GPIO_MODE_LOWPWR 0x1300 |
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| 124 | #define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340 |
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| 125 | #define S5P_CAM_LOWPWR 0x1380 |
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| 126 | #define S5P_TV_LOWPWR 0x1384 |
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| 127 | #define S5P_MFC_LOWPWR 0x1388 |
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| 128 | #define S5P_G3D_LOWPWR 0x138C |
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| 129 | #define S5P_LCD0_LOWPWR 0x1390 |
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| 130 | #define S5P_MAUDIO_LOWPWR 0x1398 |
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| 131 | #define S5P_GPS_LOWPWR 0x139C |
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| 132 | #define S5P_GPS_ALIVE_LOWPWR 0x13A0 |
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| 133 | |
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| 134 | #define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000 |
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| 135 | #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ |
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| 136 | (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) |
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| 137 | #define EXYNOS_ARM_CORE_STATUS(_nr) \ |
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| 138 | (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) |
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| 139 | #define EXYNOS_ARM_CORE_OPTION(_nr) \ |
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| 140 | (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8) |
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| 141 | |
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| 142 | #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 |
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| 143 | #define EXYNOS_COMMON_CONFIGURATION(_nr) \ |
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| 144 | (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) |
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| 145 | #define EXYNOS_COMMON_STATUS(_nr) \ |
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| 146 | (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) |
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| 147 | #define EXYNOS_COMMON_OPTION(_nr) \ |
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| 148 | (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) |
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| 149 | |
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| 150 | #define EXYNOS_ARM_L2_CONFIGURATION 0x2600 |
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| 151 | #define EXYNOS_L2_CONFIGURATION(_nr) \ |
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| 152 | (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80)) |
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| 153 | #define EXYNOS_L2_STATUS(_nr) \ |
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| 154 | (EXYNOS_L2_CONFIGURATION(_nr) + 0x4) |
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| 155 | #define EXYNOS_L2_OPTION(_nr) \ |
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| 156 | (EXYNOS_L2_CONFIGURATION(_nr) + 0x8) |
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| 157 | |
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| 158 | #define EXYNOS_L2_USE_RETENTION BIT(4) |
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| 159 | |
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| 160 | #define S5P_PAD_RET_MAUDIO_OPTION 0x3028 |
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| 161 | #define S5P_PAD_RET_MMC2_OPTION 0x30c8 |
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| 162 | #define S5P_PAD_RET_GPIO_OPTION 0x3108 |
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| 163 | #define S5P_PAD_RET_UART_OPTION 0x3128 |
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| 164 | #define S5P_PAD_RET_MMCA_OPTION 0x3148 |
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| 165 | #define S5P_PAD_RET_MMCB_OPTION 0x3168 |
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| 166 | #define S5P_PAD_RET_EBIA_OPTION 0x3188 |
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| 167 | #define S5P_PAD_RET_EBIB_OPTION 0x31A8 |
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| 168 | #define S5P_PAD_RET_SPI_OPTION 0x31c8 |
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| 169 | |
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| 170 | #define S5P_PS_HOLD_CONTROL 0x330C |
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| 171 | #define S5P_PS_HOLD_EN (1 << 31) |
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| 172 | #define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8) |
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| 173 | |
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| 174 | #define S5P_CAM_OPTION 0x3C08 |
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| 175 | #define S5P_MFC_OPTION 0x3C48 |
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| 176 | #define S5P_G3D_OPTION 0x3C68 |
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| 177 | #define S5P_LCD0_OPTION 0x3C88 |
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| 178 | #define S5P_LCD1_OPTION 0x3CA8 |
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| 179 | #define S5P_ISP_OPTION S5P_LCD1_OPTION |
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| 180 | |
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| 181 | #define S5P_CORE_LOCAL_PWR_EN 0x3 |
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| 182 | #define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) |
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| 183 | #define S5P_CORE_AUTOWAKEUP_EN (1 << 31) |
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| 184 | |
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| 185 | /* Only for S5Pv210 */ |
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| 186 | #define S5PV210_EINT_WAKEUP_MASK 0xC004 |
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| 187 | |
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| 188 | /* Only for Exynos4210 */ |
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| 189 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 |
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| 190 | #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 |
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| 191 | #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 |
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| 192 | #define S5P_PCIE_MEM_LOWPWR 0x11E0 |
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| 193 | #define S5P_SATA_MEM_LOWPWR 0x11E4 |
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| 194 | #define S5P_LCD1_LOWPWR 0x1394 |
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| 195 | |
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| 196 | /* Only for Exynos4x12 */ |
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| 197 | #define S5P_ISP_ARM_LOWPWR 0x1050 |
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| 198 | #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054 |
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| 199 | #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058 |
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| 200 | #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110 |
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| 201 | #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114 |
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| 202 | #define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C |
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| 203 | #define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130 |
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| 204 | #define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154 |
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| 205 | #define S5P_CMU_RESET_ISP_LOWPWR 0x1174 |
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| 206 | #define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190 |
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| 207 | #define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194 |
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| 208 | #define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198 |
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| 209 | #define S5P_OSCCLK_GATE_LOWPWR 0x11A4 |
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| 210 | #define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0 |
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| 211 | #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4 |
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| 212 | #define S5P_HSI_MEM_LOWPWR 0x11C4 |
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| 213 | #define S5P_ROTATOR_MEM_LOWPWR 0x11DC |
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| 214 | #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C |
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| 215 | #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250 |
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| 216 | #define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320 |
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| 217 | #define S5P_TOP_ASB_RESET_LOWPWR 0x1344 |
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| 218 | #define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348 |
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| 219 | #define S5P_ISP_LOWPWR 0x1394 |
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| 220 | #define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0 |
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| 221 | #define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4 |
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| 222 | #define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8 |
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| 223 | #define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC |
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| 224 | #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0 |
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| 225 | |
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| 226 | #define S5P_ARM_L2_0_OPTION 0x2608 |
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| 227 | #define S5P_ARM_L2_1_OPTION 0x2628 |
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| 228 | #define S5P_ONENAND_MEM_OPTION 0x2E08 |
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| 229 | #define S5P_HSI_MEM_OPTION 0x2E28 |
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| 230 | #define S5P_G2D_ACP_MEM_OPTION 0x2E48 |
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| 231 | #define S5P_USBOTG_MEM_OPTION 0x2E68 |
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| 232 | #define S5P_HSMMC_MEM_OPTION 0x2E88 |
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| 233 | #define S5P_CSSYS_MEM_OPTION 0x2EA8 |
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| 234 | #define S5P_SECSS_MEM_OPTION 0x2EC8 |
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| 235 | #define S5P_ROTATOR_MEM_OPTION 0x2F48 |
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| 236 | |
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| 237 | /* Only for Exynos4412 */ |
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| 238 | #define S5P_ARM_CORE2_LOWPWR 0x1020 |
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| 239 | #define S5P_DIS_IRQ_CORE2 0x1024 |
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| 240 | #define S5P_DIS_IRQ_CENTRAL2 0x1028 |
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| 241 | #define S5P_ARM_CORE3_LOWPWR 0x1030 |
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| 242 | #define S5P_DIS_IRQ_CORE3 0x1034 |
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| 243 | #define S5P_DIS_IRQ_CENTRAL3 0x1038 |
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| 244 | |
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| 245 | /* Only for Exynos3XXX */ |
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| 246 | #define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000 |
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| 247 | #define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 |
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| 248 | #define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 |
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| 249 | #define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010 |
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| 250 | #define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 |
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| 251 | #define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 |
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| 252 | #define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050 |
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| 253 | #define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 |
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| 254 | #define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 |
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| 255 | #define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080 |
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| 256 | #define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0 |
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| 257 | #define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 |
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| 258 | #define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 |
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| 259 | #define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C |
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| 260 | #define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110 |
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| 261 | #define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114 |
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| 262 | #define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C |
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| 263 | #define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120 |
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| 264 | #define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124 |
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| 265 | #define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128 |
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| 266 | #define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C |
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| 267 | #define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130 |
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| 268 | #define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134 |
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| 269 | #define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138 |
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| 270 | #define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 |
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| 271 | #define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 |
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| 272 | #define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C |
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| 273 | #define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 |
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| 274 | #define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154 |
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| 275 | #define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 |
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| 276 | #define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160 |
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| 277 | #define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168 |
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| 278 | #define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C |
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| 279 | #define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170 |
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| 280 | #define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174 |
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| 281 | #define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 |
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| 282 | #define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180 |
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| 283 | #define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184 |
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| 284 | #define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188 |
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| 285 | #define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190 |
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| 286 | #define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194 |
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| 287 | #define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198 |
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| 288 | #define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0 |
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| 289 | #define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4 |
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| 290 | #define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0 |
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| 291 | #define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4 |
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| 292 | #define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 |
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| 293 | #define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 |
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| 294 | #define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208 |
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| 295 | #define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218 |
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| 296 | #define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 |
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| 297 | #define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 |
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| 298 | #define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228 |
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| 299 | #define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C |
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| 300 | #define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 |
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| 301 | #define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 |
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| 302 | #define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238 |
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| 303 | #define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240 |
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| 304 | #define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260 |
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| 305 | #define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280 |
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| 306 | #define EXYNOS3_XXTI_SYS_PWR_REG 0x1284 |
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| 307 | #define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0 |
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| 308 | #define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4 |
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| 309 | #define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300 |
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| 310 | #define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 |
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| 311 | #define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344 |
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| 312 | #define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 |
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| 313 | #define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350 |
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| 314 | #define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354 |
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| 315 | #define EXYNOS3_CAM_SYS_PWR_REG 0x1380 |
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| 316 | #define EXYNOS3_MFC_SYS_PWR_REG 0x1388 |
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| 317 | #define EXYNOS3_G3D_SYS_PWR_REG 0x138C |
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| 318 | #define EXYNOS3_LCD0_SYS_PWR_REG 0x1390 |
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| 319 | #define EXYNOS3_ISP_SYS_PWR_REG 0x1394 |
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| 320 | #define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398 |
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| 321 | #define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0 |
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| 322 | #define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4 |
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| 323 | #define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8 |
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| 324 | #define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0 |
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| 325 | #define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4 |
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| 326 | #define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8 |
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| 327 | |
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| 328 | #define EXYNOS3_ARM_CORE0_OPTION 0x2008 |
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| 329 | #define EXYNOS3_ARM_CORE_OPTION(_nr) \ |
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| 330 | (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80)) |
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| 331 | |
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| 332 | #define EXYNOS3_ARM_COMMON_OPTION 0x2408 |
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| 333 | #define EXYNOS3_ARM_L2_OPTION 0x2608 |
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| 334 | #define EXYNOS3_TOP_PWR_OPTION 0x2C48 |
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| 335 | #define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8 |
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| 336 | #define EXYNOS3_XUSBXTI_DURATION 0x341C |
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| 337 | #define EXYNOS3_XXTI_DURATION 0x343C |
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| 338 | #define EXYNOS3_EXT_REGULATOR_DURATION 0x361C |
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| 339 | #define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C |
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| 340 | #define XUSBXTI_DURATION 0x00000BB8 |
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| 341 | #define XXTI_DURATION XUSBXTI_DURATION |
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| 342 | #define EXT_REGULATOR_DURATION 0x00001D4C |
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| 343 | #define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION |
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| 344 | |
|---|
| 345 | /* for XXX_OPTION */ |
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| 346 | #define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0) |
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| 347 | #define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1) |
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| 348 | #define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) |
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| 349 | |
|---|
| 350 | /* For Exynos5 */ |
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| 351 | |
|---|
| 352 | #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 |
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| 353 | #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C |
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| 354 | #define EXYNOS5_USBDRD_PHY_CONTROL 0x0704 |
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| 355 | #define EXYNOS5_DPTX_PHY_CONTROL 0x0720 |
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| 356 | |
|---|
| 357 | #define EXYNOS5_USE_RETENTION BIT(4) |
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| 358 | #define EXYNOS5_SYS_WDTRESET (1 << 20) |
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| 359 | |
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| 360 | #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 |
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| 361 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 |
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| 362 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 |
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| 363 | #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010 |
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| 364 | #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 |
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| 365 | #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 |
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| 366 | #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040 |
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| 367 | #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048 |
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| 368 | #define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050 |
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| 369 | #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 |
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| 370 | #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 |
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| 371 | #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080 |
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| 372 | #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 |
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| 373 | #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 |
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| 374 | #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 |
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| 375 | #define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C |
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| 376 | #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120 |
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| 377 | #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124 |
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| 378 | #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C |
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| 379 | #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130 |
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| 380 | #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134 |
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| 381 | #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138 |
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| 382 | #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140 |
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| 383 | #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144 |
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| 384 | #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148 |
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| 385 | #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C |
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| 386 | #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150 |
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| 387 | #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154 |
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| 388 | #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164 |
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| 389 | #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170 |
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| 390 | #define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180 |
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| 391 | #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184 |
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| 392 | #define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188 |
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| 393 | #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190 |
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| 394 | #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194 |
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| 395 | #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198 |
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| 396 | #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0 |
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| 397 | #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 |
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| 398 | #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0 |
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| 399 | #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 |
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| 400 | #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0 |
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| 401 | #define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8 |
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| 402 | #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC |
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| 403 | #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0 |
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| 404 | #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4 |
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| 405 | #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8 |
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| 406 | #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC |
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| 407 | #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0 |
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| 408 | #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4 |
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| 409 | #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8 |
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| 410 | #define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC |
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| 411 | #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4 |
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| 412 | #define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC |
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| 413 | #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 |
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| 414 | #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204 |
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| 415 | #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 |
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| 416 | #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 |
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| 417 | #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 |
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| 418 | #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C |
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| 419 | #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 |
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| 420 | #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 |
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| 421 | #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 |
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| 422 | #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C |
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| 423 | #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240 |
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| 424 | #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250 |
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| 425 | #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 |
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| 426 | #define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280 |
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| 427 | #define EXYNOS5_XXTI_SYS_PWR_REG 0x1284 |
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| 428 | #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0 |
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| 429 | #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300 |
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| 430 | #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320 |
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| 431 | #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340 |
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| 432 | #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344 |
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| 433 | #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 |
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| 434 | #define EXYNOS5_GSCL_SYS_PWR_REG 0x1400 |
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| 435 | #define EXYNOS5_ISP_SYS_PWR_REG 0x1404 |
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| 436 | #define EXYNOS5_MFC_SYS_PWR_REG 0x1408 |
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| 437 | #define EXYNOS5_G3D_SYS_PWR_REG 0x140C |
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| 438 | #define EXYNOS5_DISP1_SYS_PWR_REG 0x1414 |
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| 439 | #define EXYNOS5_MAU_SYS_PWR_REG 0x1418 |
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| 440 | #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480 |
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| 441 | #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484 |
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| 442 | #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488 |
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| 443 | #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C |
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| 444 | #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494 |
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| 445 | #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498 |
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| 446 | #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 |
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| 447 | #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4 |
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| 448 | #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8 |
|---|
| 449 | #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC |
|---|
| 450 | #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4 |
|---|
| 451 | #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8 |
|---|
| 452 | #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580 |
|---|
| 453 | #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584 |
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| 454 | #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588 |
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| 455 | #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C |
|---|
| 456 | #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594 |
|---|
| 457 | #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598 |
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| 458 | |
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| 459 | #define EXYNOS5_ARM_CORE0_OPTION 0x2008 |
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| 460 | #define EXYNOS5_ARM_CORE1_OPTION 0x2088 |
|---|
| 461 | #define EXYNOS5_FSYS_ARM_OPTION 0x2208 |
|---|
| 462 | #define EXYNOS5_ISP_ARM_OPTION 0x2288 |
|---|
| 463 | #define EXYNOS5_ARM_COMMON_OPTION 0x2408 |
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| 464 | #define EXYNOS5_ARM_L2_OPTION 0x2608 |
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| 465 | #define EXYNOS5_TOP_PWR_OPTION 0x2C48 |
|---|
| 466 | #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8 |
|---|
| 467 | #define EXYNOS5_JPEG_MEM_OPTION 0x2F48 |
|---|
| 468 | #define EXYNOS5_GSCL_OPTION 0x4008 |
|---|
| 469 | #define EXYNOS5_ISP_OPTION 0x4028 |
|---|
| 470 | #define EXYNOS5_MFC_OPTION 0x4048 |
|---|
| 471 | #define EXYNOS5_G3D_OPTION 0x4068 |
|---|
| 472 | #define EXYNOS5_DISP1_OPTION 0x40A8 |
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| 473 | #define EXYNOS5_MAU_OPTION 0x40C8 |
|---|
| 474 | |
|---|
| 475 | #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) |
|---|
| 476 | #define EXYNOS5_USE_SC_COUNTER (1 << 0) |
|---|
| 477 | |
|---|
| 478 | #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) |
|---|
| 479 | |
|---|
| 480 | #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) |
|---|
| 481 | #define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16) |
|---|
| 482 | |
|---|
| 483 | #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) |
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| 484 | |
|---|
| 485 | #define EXYNOS5420_SWRESET_KFC_SEL 0x3 |
|---|
| 486 | |
|---|
| 487 | /* Only for Exynos5420 */ |
|---|
| 488 | #define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) |
|---|
| 489 | |
|---|
| 490 | #define EXYNOS5420_LPI_MASK 0x0004 |
|---|
| 491 | #define EXYNOS5420_LPI_MASK1 0x0008 |
|---|
| 492 | #define EXYNOS5420_UFS BIT(8) |
|---|
| 493 | #define EXYNOS5420_ATB_KFC BIT(13) |
|---|
| 494 | #define EXYNOS5420_ATB_ISP_ARM BIT(19) |
|---|
| 495 | #define EXYNOS5420_EMULATION BIT(31) |
|---|
| 496 | |
|---|
| 497 | #define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100 |
|---|
| 498 | #define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104 |
|---|
| 499 | #define EXYNOS5420_UP_SCHEDULER 0x0120 |
|---|
| 500 | #define SPREAD_ENABLE 0xF |
|---|
| 501 | #define SPREAD_USE_STANDWFI 0xF |
|---|
| 502 | |
|---|
| 503 | #define EXYNOS5420_KFC_CORE_RESET0 BIT(8) |
|---|
| 504 | #define EXYNOS5420_KFC_ETM_RESET0 BIT(20) |
|---|
| 505 | |
|---|
| 506 | #define EXYNOS5420_KFC_CORE_RESET(_nr) \ |
|---|
| 507 | ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) |
|---|
| 508 | |
|---|
| 509 | #define EXYNOS5420_USBDRD1_PHY_CONTROL 0x0708 |
|---|
| 510 | #define EXYNOS5420_MIPI_PHY_CONTROL(n) (0x0714 + (n) * 4) |
|---|
| 511 | #define EXYNOS5420_DPTX_PHY_CONTROL 0x0728 |
|---|
| 512 | #define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020 |
|---|
| 513 | #define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024 |
|---|
| 514 | #define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028 |
|---|
| 515 | #define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030 |
|---|
| 516 | #define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034 |
|---|
| 517 | #define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038 |
|---|
| 518 | #define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040 |
|---|
| 519 | #define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044 |
|---|
| 520 | #define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048 |
|---|
| 521 | #define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050 |
|---|
| 522 | #define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054 |
|---|
| 523 | #define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058 |
|---|
| 524 | #define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060 |
|---|
| 525 | #define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064 |
|---|
| 526 | #define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068 |
|---|
| 527 | #define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070 |
|---|
| 528 | #define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074 |
|---|
| 529 | #define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078 |
|---|
| 530 | #define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090 |
|---|
| 531 | #define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094 |
|---|
| 532 | #define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098 |
|---|
| 533 | #define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0 |
|---|
| 534 | #define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0 |
|---|
| 535 | #define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0 |
|---|
| 536 | #define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158 |
|---|
| 537 | #define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C |
|---|
| 538 | #define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160 |
|---|
| 539 | #define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174 |
|---|
| 540 | #define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178 |
|---|
| 541 | #define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8 |
|---|
| 542 | #define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC |
|---|
| 543 | #define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208 |
|---|
| 544 | #define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210 |
|---|
| 545 | #define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214 |
|---|
| 546 | #define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218 |
|---|
| 547 | #define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C |
|---|
| 548 | #define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220 |
|---|
| 549 | #define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224 |
|---|
| 550 | #define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228 |
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| 551 | #define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C |
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| 552 | #define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230 |
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| 553 | #define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234 |
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| 554 | #define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410 |
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| 555 | #define EXYNOS5420_MAU_SYS_PWR_REG 0x1414 |
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| 556 | #define EXYNOS5420_G2D_SYS_PWR_REG 0x1418 |
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| 557 | #define EXYNOS5420_MSC_SYS_PWR_REG 0x141C |
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| 558 | #define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420 |
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| 559 | #define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424 |
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| 560 | #define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428 |
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| 561 | #define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C |
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| 562 | #define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430 |
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| 563 | #define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490 |
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| 564 | #define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494 |
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| 565 | #define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498 |
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| 566 | #define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C |
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| 567 | #define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0 |
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| 568 | #define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4 |
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| 569 | #define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8 |
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| 570 | #define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC |
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| 571 | #define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0 |
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| 572 | #define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC |
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| 573 | #define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0 |
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| 574 | #define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4 |
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| 575 | #define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8 |
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| 576 | #define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC |
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| 577 | #define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0 |
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| 578 | #define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4 |
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| 579 | #define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8 |
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| 580 | #define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC |
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| 581 | #define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0 |
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| 582 | #define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4 |
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| 583 | #define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570 |
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| 584 | #define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574 |
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| 585 | #define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578 |
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| 586 | #define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C |
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| 587 | #define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590 |
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| 588 | #define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594 |
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| 589 | #define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598 |
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| 590 | #define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C |
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| 591 | #define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0 |
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| 592 | #define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4 |
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| 593 | #define EXYNOS5420_ARM_COMMON_OPTION 0x2508 |
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| 594 | #define EXYNOS5420_KFC_COMMON_OPTION 0x2588 |
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| 595 | #define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C |
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| 596 | |
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| 597 | #define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8 |
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| 598 | #define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8 |
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| 599 | #define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108 |
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| 600 | #define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128 |
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| 601 | #define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148 |
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| 602 | #define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168 |
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| 603 | #define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8 |
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| 604 | #define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8 |
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| 605 | #define EXYNOS_PAD_RET_DRAM_OPTION 0x3008 |
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| 606 | #define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028 |
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| 607 | #define EXYNOS_PAD_RET_JTAG_OPTION 0x3048 |
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| 608 | #define EXYNOS_PAD_RET_EBIA_OPTION 0x3188 |
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| 609 | #define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8 |
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| 610 | |
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| 611 | #define EXYNOS5420_FSYS2_OPTION 0x4168 |
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| 612 | #define EXYNOS5420_PSGEN_OPTION 0x4188 |
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| 613 | |
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| 614 | #define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4) |
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| 615 | #define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5) |
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| 616 | #define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6) |
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| 617 | #define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7) |
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| 618 | #define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8) |
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| 619 | #define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9) |
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| 620 | #define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10) |
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| 621 | #define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11) |
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| 622 | #define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16) |
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| 623 | #define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17) |
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| 624 | #define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18) |
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| 625 | #define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19) |
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| 626 | #define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20) |
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| 627 | #define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21) |
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| 628 | #define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22) |
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| 629 | #define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23) |
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| 630 | |
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| 631 | #define DUR_WAIT_RESET 0xF |
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| 632 | |
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| 633 | #define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \ |
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| 634 | | EXYNOS5420_ARM_USE_STANDBY_WFI1 \ |
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| 635 | | EXYNOS5420_ARM_USE_STANDBY_WFI2 \ |
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| 636 | | EXYNOS5420_ARM_USE_STANDBY_WFI3 \ |
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| 637 | | EXYNOS5420_KFC_USE_STANDBY_WFI0 \ |
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| 638 | | EXYNOS5420_KFC_USE_STANDBY_WFI1 \ |
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| 639 | | EXYNOS5420_KFC_USE_STANDBY_WFI2 \ |
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| 640 | | EXYNOS5420_KFC_USE_STANDBY_WFI3) |
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| 641 | |
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| 642 | /* For Exynos5433 */ |
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| 643 | #define EXYNOS5433_EINT_WAKEUP_MASK (0x060C) |
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| 644 | #define EXYNOS5433_USBHOST30_PHY_CONTROL (0x0728) |
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| 645 | #define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028) |
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| 646 | #define EXYNOS5433_PAD_RETENTION_MMC2_OPTION (0x30C8) |
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| 647 | #define EXYNOS5433_PAD_RETENTION_TOP_OPTION (0x3108) |
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| 648 | #define EXYNOS5433_PAD_RETENTION_UART_OPTION (0x3128) |
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| 649 | #define EXYNOS5433_PAD_RETENTION_MMC0_OPTION (0x3148) |
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| 650 | #define EXYNOS5433_PAD_RETENTION_MMC1_OPTION (0x3168) |
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| 651 | #define EXYNOS5433_PAD_RETENTION_EBIA_OPTION (0x3188) |
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| 652 | #define EXYNOS5433_PAD_RETENTION_EBIB_OPTION (0x31A8) |
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| 653 | #define EXYNOS5433_PAD_RETENTION_SPI_OPTION (0x31C8) |
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| 654 | #define EXYNOS5433_PAD_RETENTION_MIF_OPTION (0x31E8) |
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| 655 | #define EXYNOS5433_PAD_RETENTION_USBXTI_OPTION (0x3228) |
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| 656 | #define EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION (0x3248) |
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| 657 | #define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268) |
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| 658 | #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8) |
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| 659 | |
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| 660 | #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ |
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| 661 | |
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