1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __SUNGEM_PHY_H__
3#define __SUNGEM_PHY_H__
4
5struct mii_phy;
6
7/* Operations supported by any kind of PHY */
8struct mii_phy_ops
9{
10 int (*init)(struct mii_phy *phy);
11 int (*suspend)(struct mii_phy *phy);
12 int (*setup_aneg)(struct mii_phy *phy, u32 advertise);
13 int (*setup_forced)(struct mii_phy *phy, int speed, int fd);
14 int (*poll_link)(struct mii_phy *phy);
15 int (*read_link)(struct mii_phy *phy);
16 int (*enable_fiber)(struct mii_phy *phy, int autoneg);
17};
18
19/* Structure used to statically define an mii/gii based PHY */
20struct mii_phy_def
21{
22 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
23 u32 phy_id_mask; /* Significant bits */
24 u32 features; /* Ethtool SUPPORTED_* defines */
25 int magic_aneg; /* Autoneg does all speed test for us */
26 const char* name;
27 const struct mii_phy_ops* ops;
28};
29
30enum {
31 BCM54XX_COPPER,
32 BCM54XX_FIBER,
33 BCM54XX_GBIC,
34 BCM54XX_SGMII,
35 BCM54XX_UNKNOWN,
36};
37
38/* An instance of a PHY, partially borrowed from mii_if_info */
39struct mii_phy
40{
41 struct mii_phy_def* def;
42 u32 advertising;
43 int mii_id;
44
45 /* 1: autoneg enabled, 0: disabled */
46 int autoneg;
47
48 /* forced speed & duplex (no autoneg)
49 * partner speed & duplex & pause (autoneg)
50 */
51 int speed;
52 int duplex;
53 int pause;
54
55 /* Provided by host chip */
56 struct net_device *dev;
57 int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
58 void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
59 void *platform_data;
60};
61
62/* Pass in a struct mii_phy with dev, mdio_read and mdio_write
63 * filled, the remaining fields will be filled on return
64 */
65extern int sungem_phy_probe(struct mii_phy *phy, int mii_id);
66
67
68/* MII definitions missing from mii.h */
69
70#define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
71#define LPA_PAUSE 0x0400
72
73/* More PHY registers (model specific) */
74
75/* MII BCM5201 MULTIPHY interrupt register */
76#define MII_BCM5201_INTERRUPT 0x1A
77#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
78
79#define MII_BCM5201_AUXMODE2 0x1B
80#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
81
82#define MII_BCM5201_MULTIPHY 0x1E
83
84/* MII BCM5201 MULTIPHY register bits */
85#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
86#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
87
88/* MII BCM5221 Additional registers */
89#define MII_BCM5221_TEST 0x1f
90#define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080
91#define MII_BCM5221_SHDOW_AUX_STAT2 0x1b
92#define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020
93#define MII_BCM5221_SHDOW_AUX_MODE4 0x1a
94#define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001
95#define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
96
97/* MII BCM5241 Additional registers */
98#define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR 0x0008
99
100/* MII BCM5400 1000-BASET Control register */
101#define MII_BCM5400_GB_CONTROL 0x09
102#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
103
104/* MII BCM5400 AUXCONTROL register */
105#define MII_BCM5400_AUXCONTROL 0x18
106#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
107
108/* MII BCM5400 AUXSTATUS register */
109#define MII_BCM5400_AUXSTATUS 0x19
110#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
111#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
112
113/* 1000BT control (Marvell & BCM54xx at least) */
114#define MII_1000BASETCONTROL 0x09
115#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
116#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
117
118/* Marvell 88E1011 PHY control */
119#define MII_M1011_PHY_SPEC_CONTROL 0x10
120#define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
121#define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
122
123/* Marvell 88E1011 PHY status */
124#define MII_M1011_PHY_SPEC_STATUS 0x11
125#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
126#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
127#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
128#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
129#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
130#define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008
131#define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004
132
133#endif /* __SUNGEM_PHY_H__ */
134