1/*
2 * Microsemi Switchtec PCIe Driver
3 * Copyright (c) 2017, Microsemi Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#ifndef _SWITCHTEC_H
17#define _SWITCHTEC_H
18
19#include <linux/pci.h>
20#include <linux/cdev.h>
21
22#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
23#define SWITCHTEC_MAX_PFF_CSR 48
24
25#define SWITCHTEC_EVENT_OCCURRED BIT(0)
26#define SWITCHTEC_EVENT_CLEAR BIT(0)
27#define SWITCHTEC_EVENT_EN_LOG BIT(1)
28#define SWITCHTEC_EVENT_EN_CLI BIT(2)
29#define SWITCHTEC_EVENT_EN_IRQ BIT(3)
30#define SWITCHTEC_EVENT_FATAL BIT(4)
31
32#define SWITCHTEC_DMA_MRPC_EN BIT(0)
33enum {
34 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
35 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
36 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
37 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
38 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
39 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
40 SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
41 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
42};
43
44struct mrpc_regs {
45 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
46 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
47 u32 cmd;
48 u32 status;
49 u32 ret_value;
50 u32 dma_en;
51 u64 dma_addr;
52 u32 dma_vector;
53 u32 dma_ver;
54} __packed;
55
56enum mrpc_status {
57 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
58 SWITCHTEC_MRPC_STATUS_DONE = 2,
59 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
60 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
61};
62
63struct sw_event_regs {
64 u64 event_report_ctrl;
65 u64 reserved1;
66 u64 part_event_bitmap;
67 u64 reserved2;
68 u32 global_summary;
69 u32 reserved3[3];
70 u32 stack_error_event_hdr;
71 u32 stack_error_event_data;
72 u32 reserved4[4];
73 u32 ppu_error_event_hdr;
74 u32 ppu_error_event_data;
75 u32 reserved5[4];
76 u32 isp_error_event_hdr;
77 u32 isp_error_event_data;
78 u32 reserved6[4];
79 u32 sys_reset_event_hdr;
80 u32 reserved7[5];
81 u32 fw_exception_hdr;
82 u32 reserved8[5];
83 u32 fw_nmi_hdr;
84 u32 reserved9[5];
85 u32 fw_non_fatal_hdr;
86 u32 reserved10[5];
87 u32 fw_fatal_hdr;
88 u32 reserved11[5];
89 u32 twi_mrpc_comp_hdr;
90 u32 twi_mrpc_comp_data;
91 u32 reserved12[4];
92 u32 twi_mrpc_comp_async_hdr;
93 u32 twi_mrpc_comp_async_data;
94 u32 reserved13[4];
95 u32 cli_mrpc_comp_hdr;
96 u32 cli_mrpc_comp_data;
97 u32 reserved14[4];
98 u32 cli_mrpc_comp_async_hdr;
99 u32 cli_mrpc_comp_async_data;
100 u32 reserved15[4];
101 u32 gpio_interrupt_hdr;
102 u32 gpio_interrupt_data;
103 u32 reserved16[4];
104 u32 gfms_event_hdr;
105 u32 gfms_event_data;
106 u32 reserved17[4];
107} __packed;
108
109enum {
110 SWITCHTEC_CFG0_RUNNING = 0x04,
111 SWITCHTEC_CFG1_RUNNING = 0x05,
112 SWITCHTEC_IMG0_RUNNING = 0x03,
113 SWITCHTEC_IMG1_RUNNING = 0x07,
114};
115
116struct sys_info_regs {
117 u32 device_id;
118 u32 device_version;
119 u32 firmware_version;
120 u32 reserved1;
121 u32 vendor_table_revision;
122 u32 table_format_version;
123 u32 partition_id;
124 u32 cfg_file_fmt_version;
125 u16 cfg_running;
126 u16 img_running;
127 u32 reserved2[57];
128 char vendor_id[8];
129 char product_id[16];
130 char product_revision[4];
131 char component_vendor[8];
132 u16 component_id;
133 u8 component_revision;
134} __packed;
135
136struct flash_info_regs {
137 u32 flash_part_map_upd_idx;
138
139 struct active_partition_info {
140 u32 address;
141 u32 build_version;
142 u32 build_string;
143 } active_img;
144
145 struct active_partition_info active_cfg;
146 struct active_partition_info inactive_img;
147 struct active_partition_info inactive_cfg;
148
149 u32 flash_length;
150
151 struct partition_info {
152 u32 address;
153 u32 length;
154 } cfg0;
155
156 struct partition_info cfg1;
157 struct partition_info img0;
158 struct partition_info img1;
159 struct partition_info nvlog;
160 struct partition_info vendor[8];
161};
162
163enum {
164 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
165 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
166 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
167};
168
169struct ntb_info_regs {
170 u8 partition_count;
171 u8 partition_id;
172 u16 reserved1;
173 u64 ep_map;
174 u16 requester_id;
175 u16 reserved2;
176 u32 reserved3[4];
177 struct nt_partition_info {
178 u32 xlink_enabled;
179 u32 target_part_low;
180 u32 target_part_high;
181 u32 reserved;
182 } ntp_info[48];
183} __packed;
184
185struct part_cfg_regs {
186 u32 status;
187 u32 state;
188 u32 port_cnt;
189 u32 usp_port_mode;
190 u32 usp_pff_inst_id;
191 u32 vep_pff_inst_id;
192 u32 dsp_pff_inst_id[47];
193 u32 reserved1[11];
194 u16 vep_vector_number;
195 u16 usp_vector_number;
196 u32 port_event_bitmap;
197 u32 reserved2[3];
198 u32 part_event_summary;
199 u32 reserved3[3];
200 u32 part_reset_hdr;
201 u32 part_reset_data[5];
202 u32 mrpc_comp_hdr;
203 u32 mrpc_comp_data[5];
204 u32 mrpc_comp_async_hdr;
205 u32 mrpc_comp_async_data[5];
206 u32 dyn_binding_hdr;
207 u32 dyn_binding_data[5];
208 u32 reserved4[159];
209} __packed;
210
211enum {
212 NTB_CTRL_PART_OP_LOCK = 0x1,
213 NTB_CTRL_PART_OP_CFG = 0x2,
214 NTB_CTRL_PART_OP_RESET = 0x3,
215
216 NTB_CTRL_PART_STATUS_NORMAL = 0x1,
217 NTB_CTRL_PART_STATUS_LOCKED = 0x2,
218 NTB_CTRL_PART_STATUS_LOCKING = 0x3,
219 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
220 NTB_CTRL_PART_STATUS_RESETTING = 0x5,
221
222 NTB_CTRL_BAR_VALID = 1 << 0,
223 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
224 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
225
226 NTB_CTRL_REQ_ID_EN = 1 << 0,
227
228 NTB_CTRL_LUT_EN = 1 << 0,
229
230 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
231};
232
233struct ntb_ctrl_regs {
234 u32 partition_status;
235 u32 partition_op;
236 u32 partition_ctrl;
237 u32 bar_setup;
238 u32 bar_error;
239 u16 lut_table_entries;
240 u16 lut_table_offset;
241 u32 lut_error;
242 u16 req_id_table_size;
243 u16 req_id_table_offset;
244 u32 req_id_error;
245 u32 reserved1[7];
246 struct {
247 u32 ctl;
248 u32 win_size;
249 u64 xlate_addr;
250 } bar_entry[6];
251 struct {
252 u32 win_size;
253 u32 reserved[3];
254 } bar_ext_entry[6];
255 u32 reserved2[192];
256 u32 req_id_table[512];
257 u32 reserved3[256];
258 u64 lut_entry[512];
259} __packed;
260
261#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
262#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
263
264struct ntb_dbmsg_regs {
265 u32 reserved1[1024];
266 u64 odb;
267 u64 odb_mask;
268 u64 idb;
269 u64 idb_mask;
270 u8 idb_vec_map[64];
271 u32 msg_map;
272 u32 reserved2;
273 struct {
274 u32 msg;
275 u32 status;
276 } omsg[4];
277
278 struct {
279 u32 msg;
280 u8 status;
281 u8 mask;
282 u8 src;
283 u8 reserved;
284 } imsg[4];
285
286 u8 reserved3[3928];
287 u8 msix_table[1024];
288 u8 reserved4[3072];
289 u8 pba[24];
290 u8 reserved5[4072];
291} __packed;
292
293enum {
294 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
295 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
296 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
297 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
298};
299
300struct pff_csr_regs {
301 u16 vendor_id;
302 u16 device_id;
303 u16 pcicmd;
304 u16 pcists;
305 u32 pci_class;
306 u32 pci_opts;
307 union {
308 u32 pci_bar[6];
309 u64 pci_bar64[3];
310 };
311 u32 pci_cardbus;
312 u32 pci_subsystem_id;
313 u32 pci_expansion_rom;
314 u32 pci_cap_ptr;
315 u32 reserved1;
316 u32 pci_irq;
317 u32 pci_cap_region[48];
318 u32 pcie_cap_region[448];
319 u32 indirect_gas_window[128];
320 u32 indirect_gas_window_off;
321 u32 reserved[127];
322 u32 pff_event_summary;
323 u32 reserved2[3];
324 u32 aer_in_p2p_hdr;
325 u32 aer_in_p2p_data[5];
326 u32 aer_in_vep_hdr;
327 u32 aer_in_vep_data[5];
328 u32 dpc_hdr;
329 u32 dpc_data[5];
330 u32 cts_hdr;
331 u32 cts_data[5];
332 u32 reserved3[6];
333 u32 hotplug_hdr;
334 u32 hotplug_data[5];
335 u32 ier_hdr;
336 u32 ier_data[5];
337 u32 threshold_hdr;
338 u32 threshold_data[5];
339 u32 power_mgmt_hdr;
340 u32 power_mgmt_data[5];
341 u32 tlp_throttling_hdr;
342 u32 tlp_throttling_data[5];
343 u32 force_speed_hdr;
344 u32 force_speed_data[5];
345 u32 credit_timeout_hdr;
346 u32 credit_timeout_data[5];
347 u32 link_state_hdr;
348 u32 link_state_data[5];
349 u32 reserved4[174];
350} __packed;
351
352struct switchtec_ntb;
353
354struct dma_mrpc_output {
355 u32 status;
356 u32 cmd_id;
357 u32 rtn_code;
358 u32 output_size;
359 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
360};
361
362struct switchtec_dev {
363 struct pci_dev *pdev;
364 struct device dev;
365 struct cdev cdev;
366
367 int partition;
368 int partition_count;
369 int pff_csr_count;
370 char pff_local[SWITCHTEC_MAX_PFF_CSR];
371
372 void __iomem *mmio;
373 struct mrpc_regs __iomem *mmio_mrpc;
374 struct sw_event_regs __iomem *mmio_sw_event;
375 struct sys_info_regs __iomem *mmio_sys_info;
376 struct flash_info_regs __iomem *mmio_flash_info;
377 struct ntb_info_regs __iomem *mmio_ntb;
378 struct part_cfg_regs __iomem *mmio_part_cfg;
379 struct part_cfg_regs __iomem *mmio_part_cfg_all;
380 struct pff_csr_regs __iomem *mmio_pff_csr;
381
382 /*
383 * The mrpc mutex must be held when accessing the other
384 * mrpc_ fields, alive flag and stuser->state field
385 */
386 struct mutex mrpc_mutex;
387 struct list_head mrpc_queue;
388 int mrpc_busy;
389 struct work_struct mrpc_work;
390 struct delayed_work mrpc_timeout;
391 bool alive;
392
393 wait_queue_head_t event_wq;
394 atomic_t event_cnt;
395
396 struct work_struct link_event_work;
397 void (*link_notifier)(struct switchtec_dev *stdev);
398 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
399
400 struct switchtec_ntb *sndev;
401
402 struct dma_mrpc_output *dma_mrpc;
403 dma_addr_t dma_mrpc_dma_addr;
404};
405
406static inline struct switchtec_dev *to_stdev(struct device *dev)
407{
408 return container_of(dev, struct switchtec_dev, dev);
409}
410
411extern struct class *switchtec_class;
412
413#endif
414