1/**
2 * \file drm.h
3 * Header for the Direct Rendering Manager
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 *
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */
10
11/*
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
34 */
35
36#ifndef _DRM_H_
37#define _DRM_H_
38
39#if defined(__KERNEL__)
40
41#include <linux/types.h>
42#include <asm/ioctl.h>
43typedef unsigned int drm_handle_t;
44
45#elif defined(__linux__)
46
47#include <linux/types.h>
48#include <asm/ioctl.h>
49typedef unsigned int drm_handle_t;
50
51#else /* One of the BSDs */
52
53#include <sys/ioccom.h>
54#include <sys/types.h>
55typedef int8_t __s8;
56typedef uint8_t __u8;
57typedef int16_t __s16;
58typedef uint16_t __u16;
59typedef int32_t __s32;
60typedef uint32_t __u32;
61typedef int64_t __s64;
62typedef uint64_t __u64;
63typedef size_t __kernel_size_t;
64typedef unsigned long drm_handle_t;
65
66#endif
67
68#if defined(__cplusplus)
69extern "C" {
70#endif
71
72#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
73#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
74#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
75#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
76
77#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
78#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
79#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
80#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
81#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
82
83typedef unsigned int drm_context_t;
84typedef unsigned int drm_drawable_t;
85typedef unsigned int drm_magic_t;
86
87/**
88 * Cliprect.
89 *
90 * \warning: If you change this structure, make sure you change
91 * XF86DRIClipRectRec in the server as well
92 *
93 * \note KW: Actually it's illegal to change either for
94 * backwards-compatibility reasons.
95 */
96struct drm_clip_rect {
97 unsigned short x1;
98 unsigned short y1;
99 unsigned short x2;
100 unsigned short y2;
101};
102
103/**
104 * Drawable information.
105 */
106struct drm_drawable_info {
107 unsigned int num_rects;
108 struct drm_clip_rect *rects;
109};
110
111/**
112 * Texture region,
113 */
114struct drm_tex_region {
115 unsigned char next;
116 unsigned char prev;
117 unsigned char in_use;
118 unsigned char padding;
119 unsigned int age;
120};
121
122/**
123 * Hardware lock.
124 *
125 * The lock structure is a simple cache-line aligned integer. To avoid
126 * processor bus contention on a multiprocessor system, there should not be any
127 * other data stored in the same cache line.
128 */
129struct drm_hw_lock {
130 __volatile__ unsigned int lock; /**< lock variable */
131 char padding[60]; /**< Pad to cache line */
132};
133
134/**
135 * DRM_IOCTL_VERSION ioctl argument type.
136 *
137 * \sa drmGetVersion().
138 */
139struct drm_version {
140 int version_major; /**< Major version */
141 int version_minor; /**< Minor version */
142 int version_patchlevel; /**< Patch level */
143 __kernel_size_t name_len; /**< Length of name buffer */
144 char __user *name; /**< Name of driver */
145 __kernel_size_t date_len; /**< Length of date buffer */
146 char __user *date; /**< User-space buffer to hold date */
147 __kernel_size_t desc_len; /**< Length of desc buffer */
148 char __user *desc; /**< User-space buffer to hold desc */
149};
150
151/**
152 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
153 *
154 * \sa drmGetBusid() and drmSetBusId().
155 */
156struct drm_unique {
157 __kernel_size_t unique_len; /**< Length of unique */
158 char __user *unique; /**< Unique name for driver instantiation */
159};
160
161struct drm_list {
162 int count; /**< Length of user-space structures */
163 struct drm_version __user *version;
164};
165
166struct drm_block {
167 int unused;
168};
169
170/**
171 * DRM_IOCTL_CONTROL ioctl argument type.
172 *
173 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
174 */
175struct drm_control {
176 enum {
177 DRM_ADD_COMMAND,
178 DRM_RM_COMMAND,
179 DRM_INST_HANDLER,
180 DRM_UNINST_HANDLER
181 } func;
182 int irq;
183};
184
185/**
186 * Type of memory to map.
187 */
188enum drm_map_type {
189 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
190 _DRM_REGISTERS = 1, /**< no caching, no core dump */
191 _DRM_SHM = 2, /**< shared, cached */
192 _DRM_AGP = 3, /**< AGP/GART */
193 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
194 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
195};
196
197/**
198 * Memory mapping flags.
199 */
200enum drm_map_flags {
201 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
202 _DRM_READ_ONLY = 0x02,
203 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
204 _DRM_KERNEL = 0x08, /**< kernel requires access */
205 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
206 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
207 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
208 _DRM_DRIVER = 0x80 /**< Managed by driver */
209};
210
211struct drm_ctx_priv_map {
212 unsigned int ctx_id; /**< Context requesting private mapping */
213 void *handle; /**< Handle of map */
214};
215
216/**
217 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
218 * argument type.
219 *
220 * \sa drmAddMap().
221 */
222struct drm_map {
223 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
224 unsigned long size; /**< Requested physical size (bytes) */
225 enum drm_map_type type; /**< Type of memory to map */
226 enum drm_map_flags flags; /**< Flags */
227 void *handle; /**< User-space: "Handle" to pass to mmap() */
228 /**< Kernel-space: kernel-virtual address */
229 int mtrr; /**< MTRR slot used */
230 /* Private data */
231};
232
233/**
234 * DRM_IOCTL_GET_CLIENT ioctl argument type.
235 */
236struct drm_client {
237 int idx; /**< Which client desired? */
238 int auth; /**< Is client authenticated? */
239 unsigned long pid; /**< Process ID */
240 unsigned long uid; /**< User ID */
241 unsigned long magic; /**< Magic */
242 unsigned long iocs; /**< Ioctl count */
243};
244
245enum drm_stat_type {
246 _DRM_STAT_LOCK,
247 _DRM_STAT_OPENS,
248 _DRM_STAT_CLOSES,
249 _DRM_STAT_IOCTLS,
250 _DRM_STAT_LOCKS,
251 _DRM_STAT_UNLOCKS,
252 _DRM_STAT_VALUE, /**< Generic value */
253 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
254 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
255
256 _DRM_STAT_IRQ, /**< IRQ */
257 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
258 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
259 _DRM_STAT_DMA, /**< DMA */
260 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
261 _DRM_STAT_MISSED /**< Missed DMA opportunity */
262 /* Add to the *END* of the list */
263};
264
265/**
266 * DRM_IOCTL_GET_STATS ioctl argument type.
267 */
268struct drm_stats {
269 unsigned long count;
270 struct {
271 unsigned long value;
272 enum drm_stat_type type;
273 } data[15];
274};
275
276/**
277 * Hardware locking flags.
278 */
279enum drm_lock_flags {
280 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
281 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
282 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
283 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
284 /* These *HALT* flags aren't supported yet
285 -- they will be used to support the
286 full-screen DGA-like mode. */
287 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
288 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
289};
290
291/**
292 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
293 *
294 * \sa drmGetLock() and drmUnlock().
295 */
296struct drm_lock {
297 int context;
298 enum drm_lock_flags flags;
299};
300
301/**
302 * DMA flags
303 *
304 * \warning
305 * These values \e must match xf86drm.h.
306 *
307 * \sa drm_dma.
308 */
309enum drm_dma_flags {
310 /* Flags for DMA buffer dispatch */
311 _DRM_DMA_BLOCK = 0x01, /**<
312 * Block until buffer dispatched.
313 *
314 * \note The buffer may not yet have
315 * been processed by the hardware --
316 * getting a hardware lock with the
317 * hardware quiescent will ensure
318 * that the buffer has been
319 * processed.
320 */
321 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
322 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
323
324 /* Flags for DMA buffer request */
325 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
326 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
327 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
328};
329
330/**
331 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
332 *
333 * \sa drmAddBufs().
334 */
335struct drm_buf_desc {
336 int count; /**< Number of buffers of this size */
337 int size; /**< Size in bytes */
338 int low_mark; /**< Low water mark */
339 int high_mark; /**< High water mark */
340 enum {
341 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
342 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
343 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
344 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
345 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
346 } flags;
347 unsigned long agp_start; /**<
348 * Start address of where the AGP buffers are
349 * in the AGP aperture
350 */
351};
352
353/**
354 * DRM_IOCTL_INFO_BUFS ioctl argument type.
355 */
356struct drm_buf_info {
357 int count; /**< Entries in list */
358 struct drm_buf_desc __user *list;
359};
360
361/**
362 * DRM_IOCTL_FREE_BUFS ioctl argument type.
363 */
364struct drm_buf_free {
365 int count;
366 int __user *list;
367};
368
369/**
370 * Buffer information
371 *
372 * \sa drm_buf_map.
373 */
374struct drm_buf_pub {
375 int idx; /**< Index into the master buffer list */
376 int total; /**< Buffer size */
377 int used; /**< Amount of buffer in use (for DMA) */
378 void __user *address; /**< Address of buffer */
379};
380
381/**
382 * DRM_IOCTL_MAP_BUFS ioctl argument type.
383 */
384struct drm_buf_map {
385 int count; /**< Length of the buffer list */
386#ifdef __cplusplus
387 void __user *virt;
388#else
389 void __user *virtual; /**< Mmap'd area in user-virtual */
390#endif
391 struct drm_buf_pub __user *list; /**< Buffer information */
392};
393
394/**
395 * DRM_IOCTL_DMA ioctl argument type.
396 *
397 * Indices here refer to the offset into the buffer list in drm_buf_get.
398 *
399 * \sa drmDMA().
400 */
401struct drm_dma {
402 int context; /**< Context handle */
403 int send_count; /**< Number of buffers to send */
404 int __user *send_indices; /**< List of handles to buffers */
405 int __user *send_sizes; /**< Lengths of data to send */
406 enum drm_dma_flags flags; /**< Flags */
407 int request_count; /**< Number of buffers requested */
408 int request_size; /**< Desired size for buffers */
409 int __user *request_indices; /**< Buffer information */
410 int __user *request_sizes;
411 int granted_count; /**< Number of buffers granted */
412};
413
414enum drm_ctx_flags {
415 _DRM_CONTEXT_PRESERVED = 0x01,
416 _DRM_CONTEXT_2DONLY = 0x02
417};
418
419/**
420 * DRM_IOCTL_ADD_CTX ioctl argument type.
421 *
422 * \sa drmCreateContext() and drmDestroyContext().
423 */
424struct drm_ctx {
425 drm_context_t handle;
426 enum drm_ctx_flags flags;
427};
428
429/**
430 * DRM_IOCTL_RES_CTX ioctl argument type.
431 */
432struct drm_ctx_res {
433 int count;
434 struct drm_ctx __user *contexts;
435};
436
437/**
438 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
439 */
440struct drm_draw {
441 drm_drawable_t handle;
442};
443
444/**
445 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
446 */
447typedef enum {
448 DRM_DRAWABLE_CLIPRECTS
449} drm_drawable_info_type_t;
450
451struct drm_update_draw {
452 drm_drawable_t handle;
453 unsigned int type;
454 unsigned int num;
455 unsigned long long data;
456};
457
458/**
459 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
460 */
461struct drm_auth {
462 drm_magic_t magic;
463};
464
465/**
466 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
467 *
468 * \sa drmGetInterruptFromBusID().
469 */
470struct drm_irq_busid {
471 int irq; /**< IRQ number */
472 int busnum; /**< bus number */
473 int devnum; /**< device number */
474 int funcnum; /**< function number */
475};
476
477enum drm_vblank_seq_type {
478 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
479 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
480 /* bits 1-6 are reserved for high crtcs */
481 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
482 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
483 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
484 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
485 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
486 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
487};
488#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
489
490#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
491#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
492 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
493
494struct drm_wait_vblank_request {
495 enum drm_vblank_seq_type type;
496 unsigned int sequence;
497 unsigned long signal;
498};
499
500struct drm_wait_vblank_reply {
501 enum drm_vblank_seq_type type;
502 unsigned int sequence;
503 long tval_sec;
504 long tval_usec;
505};
506
507/**
508 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
509 *
510 * \sa drmWaitVBlank().
511 */
512union drm_wait_vblank {
513 struct drm_wait_vblank_request request;
514 struct drm_wait_vblank_reply reply;
515};
516
517#define _DRM_PRE_MODESET 1
518#define _DRM_POST_MODESET 2
519
520/**
521 * DRM_IOCTL_MODESET_CTL ioctl argument type
522 *
523 * \sa drmModesetCtl().
524 */
525struct drm_modeset_ctl {
526 __u32 crtc;
527 __u32 cmd;
528};
529
530/**
531 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
532 *
533 * \sa drmAgpEnable().
534 */
535struct drm_agp_mode {
536 unsigned long mode; /**< AGP mode */
537};
538
539/**
540 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
541 *
542 * \sa drmAgpAlloc() and drmAgpFree().
543 */
544struct drm_agp_buffer {
545 unsigned long size; /**< In bytes -- will round to page boundary */
546 unsigned long handle; /**< Used for binding / unbinding */
547 unsigned long type; /**< Type of memory to allocate */
548 unsigned long physical; /**< Physical used by i810 */
549};
550
551/**
552 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
553 *
554 * \sa drmAgpBind() and drmAgpUnbind().
555 */
556struct drm_agp_binding {
557 unsigned long handle; /**< From drm_agp_buffer */
558 unsigned long offset; /**< In bytes -- will round to page boundary */
559};
560
561/**
562 * DRM_IOCTL_AGP_INFO ioctl argument type.
563 *
564 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
565 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
566 * drmAgpVendorId() and drmAgpDeviceId().
567 */
568struct drm_agp_info {
569 int agp_version_major;
570 int agp_version_minor;
571 unsigned long mode;
572 unsigned long aperture_base; /* physical address */
573 unsigned long aperture_size; /* bytes */
574 unsigned long memory_allowed; /* bytes */
575 unsigned long memory_used;
576
577 /* PCI information */
578 unsigned short id_vendor;
579 unsigned short id_device;
580};
581
582/**
583 * DRM_IOCTL_SG_ALLOC ioctl argument type.
584 */
585struct drm_scatter_gather {
586 unsigned long size; /**< In bytes -- will round to page boundary */
587 unsigned long handle; /**< Used for mapping / unmapping */
588};
589
590/**
591 * DRM_IOCTL_SET_VERSION ioctl argument type.
592 */
593struct drm_set_version {
594 int drm_di_major;
595 int drm_di_minor;
596 int drm_dd_major;
597 int drm_dd_minor;
598};
599
600/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
601struct drm_gem_close {
602 /** Handle of the object to be closed. */
603 __u32 handle;
604 __u32 pad;
605};
606
607/** DRM_IOCTL_GEM_FLINK ioctl argument type */
608struct drm_gem_flink {
609 /** Handle for the object being named */
610 __u32 handle;
611
612 /** Returned global name */
613 __u32 name;
614};
615
616/** DRM_IOCTL_GEM_OPEN ioctl argument type */
617struct drm_gem_open {
618 /** Name of object being opened */
619 __u32 name;
620
621 /** Returned handle for the object */
622 __u32 handle;
623
624 /** Returned size of the object */
625 __u64 size;
626};
627
628#define DRM_CAP_DUMB_BUFFER 0x1
629#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
630#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
631#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
632#define DRM_CAP_PRIME 0x5
633#define DRM_PRIME_CAP_IMPORT 0x1
634#define DRM_PRIME_CAP_EXPORT 0x2
635#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
636#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
637/*
638 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
639 * combination for the hardware cursor. The intention is that a hardware
640 * agnostic userspace can query a cursor plane size to use.
641 *
642 * Note that the cross-driver contract is to merely return a valid size;
643 * drivers are free to attach another meaning on top, eg. i915 returns the
644 * maximum plane size.
645 */
646#define DRM_CAP_CURSOR_WIDTH 0x8
647#define DRM_CAP_CURSOR_HEIGHT 0x9
648#define DRM_CAP_ADDFB2_MODIFIERS 0x10
649#define DRM_CAP_PAGE_FLIP_TARGET 0x11
650#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
651#define DRM_CAP_SYNCOBJ 0x13
652
653/** DRM_IOCTL_GET_CAP ioctl argument type */
654struct drm_get_cap {
655 __u64 capability;
656 __u64 value;
657};
658
659/**
660 * DRM_CLIENT_CAP_STEREO_3D
661 *
662 * if set to 1, the DRM core will expose the stereo 3D capabilities of the
663 * monitor by advertising the supported 3D layouts in the flags of struct
664 * drm_mode_modeinfo.
665 */
666#define DRM_CLIENT_CAP_STEREO_3D 1
667
668/**
669 * DRM_CLIENT_CAP_UNIVERSAL_PLANES
670 *
671 * If set to 1, the DRM core will expose all planes (overlay, primary, and
672 * cursor) to userspace.
673 */
674#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
675
676/**
677 * DRM_CLIENT_CAP_ATOMIC
678 *
679 * If set to 1, the DRM core will expose atomic properties to userspace
680 */
681#define DRM_CLIENT_CAP_ATOMIC 3
682
683/**
684 * DRM_CLIENT_CAP_ASPECT_RATIO
685 *
686 * If set to 1, the DRM core will provide aspect ratio information in modes.
687 */
688#define DRM_CLIENT_CAP_ASPECT_RATIO 4
689
690/**
691 * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
692 *
693 * If set to 1, the DRM core will expose special connectors to be used for
694 * writing back to memory the scene setup in the commit. Depends on client
695 * also supporting DRM_CLIENT_CAP_ATOMIC
696 */
697#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
698
699/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
700struct drm_set_client_cap {
701 __u64 capability;
702 __u64 value;
703};
704
705#define DRM_RDWR O_RDWR
706#define DRM_CLOEXEC O_CLOEXEC
707struct drm_prime_handle {
708 __u32 handle;
709
710 /** Flags.. only applicable for handle->fd */
711 __u32 flags;
712
713 /** Returned dmabuf file descriptor */
714 __s32 fd;
715};
716
717struct drm_syncobj_create {
718 __u32 handle;
719#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
720 __u32 flags;
721};
722
723struct drm_syncobj_destroy {
724 __u32 handle;
725 __u32 pad;
726};
727
728#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
729#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
730struct drm_syncobj_handle {
731 __u32 handle;
732 __u32 flags;
733
734 __s32 fd;
735 __u32 pad;
736};
737
738#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
739#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
740struct drm_syncobj_wait {
741 __u64 handles;
742 /* absolute timeout */
743 __s64 timeout_nsec;
744 __u32 count_handles;
745 __u32 flags;
746 __u32 first_signaled; /* only valid when not waiting all */
747 __u32 pad;
748};
749
750struct drm_syncobj_array {
751 __u64 handles;
752 __u32 count_handles;
753 __u32 pad;
754};
755
756/* Query current scanout sequence number */
757struct drm_crtc_get_sequence {
758 __u32 crtc_id; /* requested crtc_id */
759 __u32 active; /* return: crtc output is active */
760 __u64 sequence; /* return: most recent vblank sequence */
761 __s64 sequence_ns; /* return: most recent time of first pixel out */
762};
763
764/* Queue event to be delivered at specified sequence. Time stamp marks
765 * when the first pixel of the refresh cycle leaves the display engine
766 * for the display
767 */
768#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */
769#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */
770
771struct drm_crtc_queue_sequence {
772 __u32 crtc_id;
773 __u32 flags;
774 __u64 sequence; /* on input, target sequence. on output, actual sequence */
775 __u64 user_data; /* user data passed to event */
776};
777
778#if defined(__cplusplus)
779}
780#endif
781
782#include "drm_mode.h"
783
784#if defined(__cplusplus)
785extern "C" {
786#endif
787
788#define DRM_IOCTL_BASE 'd'
789#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
790#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
791#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
792#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
793
794#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
795#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
796#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
797#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
798#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
799#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
800#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
801#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
802#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
803#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
804#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
805#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
806#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
807#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
808
809#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
810#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
811#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
812#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
813#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
814#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
815#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
816#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
817#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
818#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
819#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
820
821#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
822
823#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
824#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
825
826#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
827#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
828
829#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
830#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
831#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
832#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
833#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
834#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
835#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
836#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
837#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
838#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
839#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
840#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
841#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
842
843#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
844#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
845
846#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
847#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
848#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
849#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
850#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
851#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
852#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
853#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
854
855#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
856#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
857
858#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
859
860#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
861#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
862
863#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
864
865#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
866#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
867#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
868#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
869#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
870#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
871#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
872#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
873#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
874#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
875
876#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
877#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
878#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
879#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
880#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
881#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
882#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
883#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
884
885#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
886#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
887#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
888#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
889#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
890#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
891#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
892#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
893#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
894#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
895#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
896#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
897#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
898
899#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
900#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
901#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
902#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
903#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
904#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
905#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
906
907#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)
908#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)
909#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
910#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
911
912/**
913 * Device specific ioctls should only be in their respective headers
914 * The device specific ioctl range is from 0x40 to 0x9f.
915 * Generic IOCTLS restart at 0xA0.
916 *
917 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
918 * drmCommandReadWrite().
919 */
920#define DRM_COMMAND_BASE 0x40
921#define DRM_COMMAND_END 0xA0
922
923/**
924 * Header for events written back to userspace on the drm fd. The
925 * type defines the type of event, the length specifies the total
926 * length of the event (including the header), and user_data is
927 * typically a 64 bit value passed with the ioctl that triggered the
928 * event. A read on the drm fd will always only return complete
929 * events, that is, if for example the read buffer is 100 bytes, and
930 * there are two 64 byte events pending, only one will be returned.
931 *
932 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
933 * up are chipset specific.
934 */
935struct drm_event {
936 __u32 type;
937 __u32 length;
938};
939
940#define DRM_EVENT_VBLANK 0x01
941#define DRM_EVENT_FLIP_COMPLETE 0x02
942#define DRM_EVENT_CRTC_SEQUENCE 0x03
943
944struct drm_event_vblank {
945 struct drm_event base;
946 __u64 user_data;
947 __u32 tv_sec;
948 __u32 tv_usec;
949 __u32 sequence;
950 __u32 crtc_id; /* 0 on older kernels that do not support this */
951};
952
953/* Event delivered at sequence. Time stamp marks when the first pixel
954 * of the refresh cycle leaves the display engine for the display
955 */
956struct drm_event_crtc_sequence {
957 struct drm_event base;
958 __u64 user_data;
959 __s64 time_ns;
960 __u64 sequence;
961};
962
963/* typedef area */
964#ifndef __KERNEL__
965typedef struct drm_clip_rect drm_clip_rect_t;
966typedef struct drm_drawable_info drm_drawable_info_t;
967typedef struct drm_tex_region drm_tex_region_t;
968typedef struct drm_hw_lock drm_hw_lock_t;
969typedef struct drm_version drm_version_t;
970typedef struct drm_unique drm_unique_t;
971typedef struct drm_list drm_list_t;
972typedef struct drm_block drm_block_t;
973typedef struct drm_control drm_control_t;
974typedef enum drm_map_type drm_map_type_t;
975typedef enum drm_map_flags drm_map_flags_t;
976typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
977typedef struct drm_map drm_map_t;
978typedef struct drm_client drm_client_t;
979typedef enum drm_stat_type drm_stat_type_t;
980typedef struct drm_stats drm_stats_t;
981typedef enum drm_lock_flags drm_lock_flags_t;
982typedef struct drm_lock drm_lock_t;
983typedef enum drm_dma_flags drm_dma_flags_t;
984typedef struct drm_buf_desc drm_buf_desc_t;
985typedef struct drm_buf_info drm_buf_info_t;
986typedef struct drm_buf_free drm_buf_free_t;
987typedef struct drm_buf_pub drm_buf_pub_t;
988typedef struct drm_buf_map drm_buf_map_t;
989typedef struct drm_dma drm_dma_t;
990typedef union drm_wait_vblank drm_wait_vblank_t;
991typedef struct drm_agp_mode drm_agp_mode_t;
992typedef enum drm_ctx_flags drm_ctx_flags_t;
993typedef struct drm_ctx drm_ctx_t;
994typedef struct drm_ctx_res drm_ctx_res_t;
995typedef struct drm_draw drm_draw_t;
996typedef struct drm_update_draw drm_update_draw_t;
997typedef struct drm_auth drm_auth_t;
998typedef struct drm_irq_busid drm_irq_busid_t;
999typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1000
1001typedef struct drm_agp_buffer drm_agp_buffer_t;
1002typedef struct drm_agp_binding drm_agp_binding_t;
1003typedef struct drm_agp_info drm_agp_info_t;
1004typedef struct drm_scatter_gather drm_scatter_gather_t;
1005typedef struct drm_set_version drm_set_version_t;
1006#endif
1007
1008#if defined(__cplusplus)
1009}
1010#endif
1011
1012#endif
1013