1/* SPDX-License-Identifier: GPL-2.0 */
2/* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $
3 * linux/drivers/video/aty128.h
4 * Register definitions for ATI Rage128 boards
5 *
6 * Anthony Tong <atong@uiuc.edu>, 1999
7 * Brad Douglas <brad@neruo.com>, 2000
8 */
9
10#ifndef REG_RAGE128_H
11#define REG_RAGE128_H
12
13#define CLOCK_CNTL_INDEX 0x0008
14#define CLOCK_CNTL_DATA 0x000c
15#define BIOS_0_SCRATCH 0x0010
16#define BUS_CNTL 0x0030
17#define BUS_CNTL1 0x0034
18#define GEN_INT_CNTL 0x0040
19#define CRTC_GEN_CNTL 0x0050
20#define CRTC_EXT_CNTL 0x0054
21#define DAC_CNTL 0x0058
22#define I2C_CNTL_1 0x0094
23#define PALETTE_INDEX 0x00b0
24#define PALETTE_DATA 0x00b4
25#define CNFG_CNTL 0x00e0
26#define GEN_RESET_CNTL 0x00f0
27#define CNFG_MEMSIZE 0x00f8
28#define MEM_CNTL 0x0140
29#define MEM_POWER_MISC 0x015c
30#define AGP_BASE 0x0170
31#define AGP_CNTL 0x0174
32#define AGP_APER_OFFSET 0x0178
33#define PCI_GART_PAGE 0x017c
34#define PC_NGUI_MODE 0x0180
35#define PC_NGUI_CTLSTAT 0x0184
36#define MPP_TB_CONFIG 0x01C0
37#define MPP_GP_CONFIG 0x01C8
38#define VIPH_CONTROL 0x01D0
39#define CRTC_H_TOTAL_DISP 0x0200
40#define CRTC_H_SYNC_STRT_WID 0x0204
41#define CRTC_V_TOTAL_DISP 0x0208
42#define CRTC_V_SYNC_STRT_WID 0x020c
43#define CRTC_VLINE_CRNT_VLINE 0x0210
44#define CRTC_CRNT_FRAME 0x0214
45#define CRTC_GUI_TRIG_VLINE 0x0218
46#define CRTC_OFFSET 0x0224
47#define CRTC_OFFSET_CNTL 0x0228
48#define CRTC_PITCH 0x022c
49#define OVR_CLR 0x0230
50#define OVR_WID_LEFT_RIGHT 0x0234
51#define OVR_WID_TOP_BOTTOM 0x0238
52#define LVDS_GEN_CNTL 0x02d0
53#define DDA_CONFIG 0x02e0
54#define DDA_ON_OFF 0x02e4
55#define VGA_DDA_CONFIG 0x02e8
56#define VGA_DDA_ON_OFF 0x02ec
57#define CRTC2_H_TOTAL_DISP 0x0300
58#define CRTC2_H_SYNC_STRT_WID 0x0304
59#define CRTC2_V_TOTAL_DISP 0x0308
60#define CRTC2_V_SYNC_STRT_WID 0x030c
61#define CRTC2_VLINE_CRNT_VLINE 0x0310
62#define CRTC2_CRNT_FRAME 0x0314
63#define CRTC2_GUI_TRIG_VLINE 0x0318
64#define CRTC2_OFFSET 0x0324
65#define CRTC2_OFFSET_CNTL 0x0328
66#define CRTC2_PITCH 0x032c
67#define DDA2_CONFIG 0x03e0
68#define DDA2_ON_OFF 0x03e4
69#define CRTC2_GEN_CNTL 0x03f8
70#define CRTC2_STATUS 0x03fc
71#define OV0_SCALE_CNTL 0x0420
72#define SUBPIC_CNTL 0x0540
73#define PM4_BUFFER_OFFSET 0x0700
74#define PM4_BUFFER_CNTL 0x0704
75#define PM4_BUFFER_WM_CNTL 0x0708
76#define PM4_BUFFER_DL_RPTR_ADDR 0x070c
77#define PM4_BUFFER_DL_RPTR 0x0710
78#define PM4_BUFFER_DL_WPTR 0x0714
79#define PM4_VC_FPU_SETUP 0x071c
80#define PM4_FPU_CNTL 0x0720
81#define PM4_VC_FORMAT 0x0724
82#define PM4_VC_CNTL 0x0728
83#define PM4_VC_I01 0x072c
84#define PM4_VC_VLOFF 0x0730
85#define PM4_VC_VLSIZE 0x0734
86#define PM4_IW_INDOFF 0x0738
87#define PM4_IW_INDSIZE 0x073c
88#define PM4_FPU_FPX0 0x0740
89#define PM4_FPU_FPY0 0x0744
90#define PM4_FPU_FPX1 0x0748
91#define PM4_FPU_FPY1 0x074c
92#define PM4_FPU_FPX2 0x0750
93#define PM4_FPU_FPY2 0x0754
94#define PM4_FPU_FPY3 0x0758
95#define PM4_FPU_FPY4 0x075c
96#define PM4_FPU_FPY5 0x0760
97#define PM4_FPU_FPY6 0x0764
98#define PM4_FPU_FPR 0x0768
99#define PM4_FPU_FPG 0x076c
100#define PM4_FPU_FPB 0x0770
101#define PM4_FPU_FPA 0x0774
102#define PM4_FPU_INTXY0 0x0780
103#define PM4_FPU_INTXY1 0x0784
104#define PM4_FPU_INTXY2 0x0788
105#define PM4_FPU_INTARGB 0x078c
106#define PM4_FPU_FPTWICEAREA 0x0790
107#define PM4_FPU_DMAJOR01 0x0794
108#define PM4_FPU_DMAJOR12 0x0798
109#define PM4_FPU_DMAJOR02 0x079c
110#define PM4_FPU_STAT 0x07a0
111#define PM4_STAT 0x07b8
112#define PM4_TEST_CNTL 0x07d0
113#define PM4_MICROCODE_ADDR 0x07d4
114#define PM4_MICROCODE_RADDR 0x07d8
115#define PM4_MICROCODE_DATAH 0x07dc
116#define PM4_MICROCODE_DATAL 0x07e0
117#define PM4_CMDFIFO_ADDR 0x07e4
118#define PM4_CMDFIFO_DATAH 0x07e8
119#define PM4_CMDFIFO_DATAL 0x07ec
120#define PM4_BUFFER_ADDR 0x07f0
121#define PM4_BUFFER_DATAH 0x07f4
122#define PM4_BUFFER_DATAL 0x07f8
123#define PM4_MICRO_CNTL 0x07fc
124#define CAP0_TRIG_CNTL 0x0950
125#define CAP1_TRIG_CNTL 0x09c0
126
127/******************************************************************************
128 * GUI Block Memory Mapped Registers *
129 * These registers are FIFOed. *
130 *****************************************************************************/
131#define PM4_FIFO_DATA_EVEN 0x1000
132#define PM4_FIFO_DATA_ODD 0x1004
133
134#define DST_OFFSET 0x1404
135#define DST_PITCH 0x1408
136#define DST_WIDTH 0x140c
137#define DST_HEIGHT 0x1410
138#define SRC_X 0x1414
139#define SRC_Y 0x1418
140#define DST_X 0x141c
141#define DST_Y 0x1420
142#define SRC_PITCH_OFFSET 0x1428
143#define DST_PITCH_OFFSET 0x142c
144#define SRC_Y_X 0x1434
145#define DST_Y_X 0x1438
146#define DST_HEIGHT_WIDTH 0x143c
147#define DP_GUI_MASTER_CNTL 0x146c
148#define BRUSH_SCALE 0x1470
149#define BRUSH_Y_X 0x1474
150#define DP_BRUSH_BKGD_CLR 0x1478
151#define DP_BRUSH_FRGD_CLR 0x147c
152#define DST_WIDTH_X 0x1588
153#define DST_HEIGHT_WIDTH_8 0x158c
154#define SRC_X_Y 0x1590
155#define DST_X_Y 0x1594
156#define DST_WIDTH_HEIGHT 0x1598
157#define DST_WIDTH_X_INCY 0x159c
158#define DST_HEIGHT_Y 0x15a0
159#define DST_X_SUB 0x15a4
160#define DST_Y_SUB 0x15a8
161#define SRC_OFFSET 0x15ac
162#define SRC_PITCH 0x15b0
163#define DST_HEIGHT_WIDTH_BW 0x15b4
164#define CLR_CMP_CNTL 0x15c0
165#define CLR_CMP_CLR_SRC 0x15c4
166#define CLR_CMP_CLR_DST 0x15c8
167#define CLR_CMP_MASK 0x15cc
168#define DP_SRC_FRGD_CLR 0x15d8
169#define DP_SRC_BKGD_CLR 0x15dc
170#define DST_BRES_ERR 0x1628
171#define DST_BRES_INC 0x162c
172#define DST_BRES_DEC 0x1630
173#define DST_BRES_LNTH 0x1634
174#define DST_BRES_LNTH_SUB 0x1638
175#define SC_LEFT 0x1640
176#define SC_RIGHT 0x1644
177#define SC_TOP 0x1648
178#define SC_BOTTOM 0x164c
179#define SRC_SC_RIGHT 0x1654
180#define SRC_SC_BOTTOM 0x165c
181#define GUI_DEBUG0 0x16a0
182#define GUI_DEBUG1 0x16a4
183#define GUI_TIMEOUT 0x16b0
184#define GUI_TIMEOUT0 0x16b4
185#define GUI_TIMEOUT1 0x16b8
186#define GUI_PROBE 0x16bc
187#define DP_CNTL 0x16c0
188#define DP_DATATYPE 0x16c4
189#define DP_MIX 0x16c8
190#define DP_WRITE_MASK 0x16cc
191#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
192#define DEFAULT_OFFSET 0x16e0
193#define DEFAULT_PITCH 0x16e4
194#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8
195#define SC_TOP_LEFT 0x16ec
196#define SC_BOTTOM_RIGHT 0x16f0
197#define SRC_SC_BOTTOM_RIGHT 0x16f4
198#define WAIT_UNTIL 0x1720
199#define CACHE_CNTL 0x1724
200#define GUI_STAT 0x1740
201#define PC_GUI_MODE 0x1744
202#define PC_GUI_CTLSTAT 0x1748
203#define PC_DEBUG_MODE 0x1760
204#define BRES_DST_ERR_DEC 0x1780
205#define TRAIL_BRES_T12_ERR_DEC 0x1784
206#define TRAIL_BRES_T12_INC 0x1788
207#define DP_T12_CNTL 0x178c
208#define DST_BRES_T1_LNTH 0x1790
209#define DST_BRES_T2_LNTH 0x1794
210#define SCALE_SRC_HEIGHT_WIDTH 0x1994
211#define SCALE_OFFSET_0 0x1998
212#define SCALE_PITCH 0x199c
213#define SCALE_X_INC 0x19a0
214#define SCALE_Y_INC 0x19a4
215#define SCALE_HACC 0x19a8
216#define SCALE_VACC 0x19ac
217#define SCALE_DST_X_Y 0x19b0
218#define SCALE_DST_HEIGHT_WIDTH 0x19b4
219#define SCALE_3D_CNTL 0x1a00
220#define SCALE_3D_DATATYPE 0x1a20
221#define SETUP_CNTL 0x1bc4
222#define SOLID_COLOR 0x1bc8
223#define WINDOW_XY_OFFSET 0x1bcc
224#define DRAW_LINE_POINT 0x1bd0
225#define SETUP_CNTL_PM4 0x1bd4
226#define DST_PITCH_OFFSET_C 0x1c80
227#define DP_GUI_MASTER_CNTL_C 0x1c84
228#define SC_TOP_LEFT_C 0x1c88
229#define SC_BOTTOM_RIGHT_C 0x1c8c
230
231#define CLR_CMP_MASK_3D 0x1A28
232#define MISC_3D_STATE_CNTL_REG 0x1CA0
233#define MC_SRC1_CNTL 0x19D8
234#define TEX_CNTL 0x1800
235
236/* CONSTANTS */
237#define GUI_ACTIVE 0x80000000
238#define ENGINE_IDLE 0x0
239
240#define PLL_WR_EN 0x00000080
241
242#define CLK_PIN_CNTL 0x0001
243#define PPLL_CNTL 0x0002
244#define PPLL_REF_DIV 0x0003
245#define PPLL_DIV_0 0x0004
246#define PPLL_DIV_1 0x0005
247#define PPLL_DIV_2 0x0006
248#define PPLL_DIV_3 0x0007
249#define VCLK_ECP_CNTL 0x0008
250#define HTOTAL_CNTL 0x0009
251#define X_MPLL_REF_FB_DIV 0x000a
252#define XPLL_CNTL 0x000b
253#define XDLL_CNTL 0x000c
254#define XCLK_CNTL 0x000d
255#define MPLL_CNTL 0x000e
256#define MCLK_CNTL 0x000f
257#define AGP_PLL_CNTL 0x0010
258#define FCP_CNTL 0x0012
259#define PLL_TEST_CNTL 0x0013
260#define P2PLL_CNTL 0x002a
261#define P2PLL_REF_DIV 0x002b
262#define P2PLL_DIV_0 0x002b
263#define POWER_MANAGEMENT 0x002f
264
265#define PPLL_RESET 0x01
266#define PPLL_ATOMIC_UPDATE_EN 0x10000
267#define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000
268#define PPLL_REF_DIV_MASK 0x3FF
269#define PPLL_FB3_DIV_MASK 0x7FF
270#define PPLL_POST3_DIV_MASK 0x70000
271#define PPLL_ATOMIC_UPDATE_R 0x8000
272#define PPLL_ATOMIC_UPDATE_W 0x8000
273#define MEM_CFG_TYPE_MASK 0x3
274#define XCLK_SRC_SEL_MASK 0x7
275#define XPLL_FB_DIV_MASK 0xFF00
276#define X_MPLL_REF_DIV_MASK 0xFF
277
278/* CRTC control values (CRTC_GEN_CNTL) */
279#define CRTC_CSYNC_EN 0x00000010
280
281#define CRTC2_DBL_SCAN_EN 0x00000001
282#define CRTC2_DISPLAY_DIS 0x00800000
283#define CRTC2_FIFO_EXTSENSE 0x00200000
284#define CRTC2_ICON_EN 0x00100000
285#define CRTC2_CUR_EN 0x00010000
286#define CRTC2_EN 0x02000000
287#define CRTC2_DISP_REQ_EN_B 0x04000000
288
289#define CRTC_PIX_WIDTH_MASK 0x00000700
290#define CRTC_PIX_WIDTH_4BPP 0x00000100
291#define CRTC_PIX_WIDTH_8BPP 0x00000200
292#define CRTC_PIX_WIDTH_15BPP 0x00000300
293#define CRTC_PIX_WIDTH_16BPP 0x00000400
294#define CRTC_PIX_WIDTH_24BPP 0x00000500
295#define CRTC_PIX_WIDTH_32BPP 0x00000600
296
297/* DAC_CNTL bit constants */
298#define DAC_8BIT_EN 0x00000100
299#define DAC_MASK 0xFF000000
300#define DAC_BLANKING 0x00000004
301#define DAC_RANGE_CNTL 0x00000003
302#define DAC_CLK_SEL 0x00000010
303#define DAC_PALETTE_ACCESS_CNTL 0x00000020
304#define DAC_PALETTE2_SNOOP_EN 0x00000040
305#define DAC_PDWN 0x00008000
306
307/* CRTC_EXT_CNTL */
308#define CRT_CRTC_ON 0x00008000
309
310/* GEN_RESET_CNTL bit constants */
311#define SOFT_RESET_GUI 0x00000001
312#define SOFT_RESET_VCLK 0x00000100
313#define SOFT_RESET_PCLK 0x00000200
314#define SOFT_RESET_ECP 0x00000400
315#define SOFT_RESET_DISPENG_XCLK 0x00000800
316
317/* PC_GUI_CTLSTAT bit constants */
318#define PC_BUSY_INIT 0x10000000
319#define PC_BUSY_GUI 0x20000000
320#define PC_BUSY_NGUI 0x40000000
321#define PC_BUSY 0x80000000
322
323#define BUS_MASTER_DIS 0x00000040
324#define PM4_BUFFER_CNTL_NONPM4 0x00000000
325
326/* DP_DATATYPE bit constants */
327#define DST_8BPP 0x00000002
328#define DST_15BPP 0x00000003
329#define DST_16BPP 0x00000004
330#define DST_24BPP 0x00000005
331#define DST_32BPP 0x00000006
332
333#define BRUSH_SOLIDCOLOR 0x00000d00
334
335/* DP_GUI_MASTER_CNTL bit constants */
336#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
337#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
338#define GMC_SRC_CLIP_DEFAULT 0x00000000
339#define GMC_DST_CLIP_DEFAULT 0x00000000
340#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
341#define GMC_SRC_DSTCOLOR 0x00003000
342#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
343#define GMC_DP_SRC_RECT 0x02000000
344#define GMC_3D_FCN_EN_CLR 0x00000000
345#define GMC_AUX_CLIP_CLEAR 0x20000000
346#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
347#define GMC_WRITE_MASK_SET 0x40000000
348#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
349
350/* DP_GUI_MASTER_CNTL ROP3 named constants */
351#define ROP3_PATCOPY 0x00f00000
352#define ROP3_SRCCOPY 0x00cc0000
353
354#define SRC_DSTCOLOR 0x00030000
355
356/* DP_CNTL bit constants */
357#define DST_X_RIGHT_TO_LEFT 0x00000000
358#define DST_X_LEFT_TO_RIGHT 0x00000001
359#define DST_Y_BOTTOM_TO_TOP 0x00000000
360#define DST_Y_TOP_TO_BOTTOM 0x00000002
361#define DST_X_MAJOR 0x00000000
362#define DST_Y_MAJOR 0x00000004
363#define DST_X_TILE 0x00000008
364#define DST_Y_TILE 0x00000010
365#define DST_LAST_PEL 0x00000020
366#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
367#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
368#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
369#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
370#define DST_BRES_SIGN 0x00000100
371#define DST_HOST_BIG_ENDIAN_EN 0x00000200
372#define DST_POLYLINE_NONLAST 0x00008000
373#define DST_RASTER_STALL 0x00010000
374#define DST_POLY_EDGE 0x00040000
375
376/* DP_MIX bit constants */
377#define DP_SRC_RECT 0x00000200
378#define DP_SRC_HOST 0x00000300
379#define DP_SRC_HOST_BYTEALIGN 0x00000400
380
381/* LVDS_GEN_CNTL constants */
382#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
383#define LVDS_BL_MOD_LEVEL_SHIFT 8
384#define LVDS_BL_MOD_EN 0x00010000
385#define LVDS_DIGION 0x00040000
386#define LVDS_BLON 0x00080000
387#define LVDS_ON 0x00000001
388#define LVDS_DISPLAY_DIS 0x00000002
389#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004
390#define LVDS_PANEL_24BITS_TFT 0x00000008
391#define LVDS_FRAME_MOD_NO 0x00000000
392#define LVDS_FRAME_MOD_2_LEVELS 0x00000010
393#define LVDS_FRAME_MOD_4_LEVELS 0x00000020
394#define LVDS_RST_FM 0x00000040
395#define LVDS_EN 0x00000080
396
397/* CRTC2_GEN_CNTL constants */
398#define CRTC2_EN 0x02000000
399
400/* POWER_MANAGEMENT constants */
401#define PWR_MGT_ON 0x00000001
402#define PWR_MGT_MODE_MASK 0x00000006
403#define PWR_MGT_MODE_PIN 0x00000000
404#define PWR_MGT_MODE_REGISTER 0x00000002
405#define PWR_MGT_MODE_TIMER 0x00000004
406#define PWR_MGT_MODE_PCI 0x00000006
407#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008
408#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010
409#define PWR_MGT_STANDBY_POL 0x00000020
410#define PWR_MGT_SUSPEND_POL 0x00000040
411#define PWR_MGT_SELF_REFRESH 0x00000080
412#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100
413#define PWR_MGT_KEYBD_SNOOP 0x00000200
414#define PWR_MGT_TRISTATE_MEM_EN 0x00000800
415#define PWR_MGT_SELW4MS 0x00001000
416#define PWR_MGT_SLOWDOWN_MCLK 0x00002000
417
418#define PMI_PMSCR_REG 0x60
419
420/* used by ATI bug fix for hardware ROM */
421#define RAGE128_MPP_TB_CONFIG 0x01c0
422
423#endif /* REG_RAGE128_H */
424