1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (C) 2016 Texas Instruments, Inc. |
4 | */ |
5 | |
6 | #ifndef __OMAPFB_DSS_H |
7 | #define __OMAPFB_DSS_H |
8 | |
9 | #include <linux/list.h> |
10 | #include <linux/kobject.h> |
11 | #include <linux/device.h> |
12 | #include <linux/interrupt.h> |
13 | #include <linux/platform_data/omapdss.h> |
14 | |
15 | #include <video/videomode.h> |
16 | |
17 | #define DISPC_IRQ_FRAMEDONE (1 << 0) |
18 | #define DISPC_IRQ_VSYNC (1 << 1) |
19 | #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) |
20 | #define DISPC_IRQ_EVSYNC_ODD (1 << 3) |
21 | #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) |
22 | #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) |
23 | #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) |
24 | #define DISPC_IRQ_GFX_END_WIN (1 << 7) |
25 | #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) |
26 | #define DISPC_IRQ_OCP_ERR (1 << 9) |
27 | #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) |
28 | #define DISPC_IRQ_VID1_END_WIN (1 << 11) |
29 | #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) |
30 | #define DISPC_IRQ_VID2_END_WIN (1 << 13) |
31 | #define DISPC_IRQ_SYNC_LOST (1 << 14) |
32 | #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) |
33 | #define DISPC_IRQ_WAKEUP (1 << 16) |
34 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) |
35 | #define DISPC_IRQ_VSYNC2 (1 << 18) |
36 | #define DISPC_IRQ_VID3_END_WIN (1 << 19) |
37 | #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) |
38 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) |
39 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) |
40 | #define DISPC_IRQ_FRAMEDONEWB (1 << 23) |
41 | #define DISPC_IRQ_FRAMEDONETV (1 << 24) |
42 | #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) |
43 | #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26) |
44 | #define DISPC_IRQ_SYNC_LOST3 (1 << 27) |
45 | #define DISPC_IRQ_VSYNC3 (1 << 28) |
46 | #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) |
47 | #define DISPC_IRQ_FRAMEDONE3 (1 << 30) |
48 | |
49 | struct omap_dss_device; |
50 | struct omap_overlay_manager; |
51 | struct dss_lcd_mgr_config; |
52 | struct snd_aes_iec958; |
53 | struct snd_cea_861_aud_if; |
54 | struct hdmi_avi_infoframe; |
55 | |
56 | enum omap_display_type { |
57 | OMAP_DISPLAY_TYPE_NONE = 0, |
58 | OMAP_DISPLAY_TYPE_DPI = 1 << 0, |
59 | OMAP_DISPLAY_TYPE_DBI = 1 << 1, |
60 | OMAP_DISPLAY_TYPE_SDI = 1 << 2, |
61 | OMAP_DISPLAY_TYPE_DSI = 1 << 3, |
62 | OMAP_DISPLAY_TYPE_VENC = 1 << 4, |
63 | OMAP_DISPLAY_TYPE_HDMI = 1 << 5, |
64 | OMAP_DISPLAY_TYPE_DVI = 1 << 6, |
65 | }; |
66 | |
67 | enum omap_plane { |
68 | OMAP_DSS_GFX = 0, |
69 | OMAP_DSS_VIDEO1 = 1, |
70 | OMAP_DSS_VIDEO2 = 2, |
71 | OMAP_DSS_VIDEO3 = 3, |
72 | OMAP_DSS_WB = 4, |
73 | }; |
74 | |
75 | enum omap_channel { |
76 | OMAP_DSS_CHANNEL_LCD = 0, |
77 | OMAP_DSS_CHANNEL_DIGIT = 1, |
78 | OMAP_DSS_CHANNEL_LCD2 = 2, |
79 | OMAP_DSS_CHANNEL_LCD3 = 3, |
80 | OMAP_DSS_CHANNEL_WB = 4, |
81 | }; |
82 | |
83 | enum omap_color_mode { |
84 | OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ |
85 | OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ |
86 | OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ |
87 | OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ |
88 | OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ |
89 | OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ |
90 | OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ |
91 | OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ |
92 | OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ |
93 | OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ |
94 | OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ |
95 | OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ |
96 | OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ |
97 | OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ |
98 | OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ |
99 | OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ |
100 | OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ |
101 | OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ |
102 | OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ |
103 | }; |
104 | |
105 | enum omap_dss_load_mode { |
106 | OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, |
107 | OMAP_DSS_LOAD_CLUT_ONLY = 1, |
108 | OMAP_DSS_LOAD_FRAME_ONLY = 2, |
109 | OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, |
110 | }; |
111 | |
112 | enum omap_dss_trans_key_type { |
113 | OMAP_DSS_COLOR_KEY_GFX_DST = 0, |
114 | OMAP_DSS_COLOR_KEY_VID_SRC = 1, |
115 | }; |
116 | |
117 | enum omap_dss_signal_level { |
118 | OMAPDSS_SIG_ACTIVE_LOW, |
119 | OMAPDSS_SIG_ACTIVE_HIGH, |
120 | }; |
121 | |
122 | enum omap_dss_signal_edge { |
123 | OMAPDSS_DRIVE_SIG_FALLING_EDGE, |
124 | OMAPDSS_DRIVE_SIG_RISING_EDGE, |
125 | }; |
126 | |
127 | enum omap_dss_venc_type { |
128 | OMAP_DSS_VENC_TYPE_COMPOSITE, |
129 | OMAP_DSS_VENC_TYPE_SVIDEO, |
130 | }; |
131 | |
132 | enum omap_dss_dsi_pixel_format { |
133 | OMAP_DSS_DSI_FMT_RGB888, |
134 | OMAP_DSS_DSI_FMT_RGB666, |
135 | OMAP_DSS_DSI_FMT_RGB666_PACKED, |
136 | OMAP_DSS_DSI_FMT_RGB565, |
137 | }; |
138 | |
139 | enum omap_dss_dsi_mode { |
140 | OMAP_DSS_DSI_CMD_MODE = 0, |
141 | OMAP_DSS_DSI_VIDEO_MODE, |
142 | }; |
143 | |
144 | enum omap_display_caps { |
145 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, |
146 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, |
147 | }; |
148 | |
149 | enum omap_dss_display_state { |
150 | OMAP_DSS_DISPLAY_DISABLED = 0, |
151 | OMAP_DSS_DISPLAY_ACTIVE, |
152 | }; |
153 | |
154 | enum omap_dss_rotation_type { |
155 | OMAP_DSS_ROT_DMA = 1 << 0, |
156 | OMAP_DSS_ROT_VRFB = 1 << 1, |
157 | OMAP_DSS_ROT_TILER = 1 << 2, |
158 | }; |
159 | |
160 | /* clockwise rotation angle */ |
161 | enum omap_dss_rotation_angle { |
162 | OMAP_DSS_ROT_0 = 0, |
163 | OMAP_DSS_ROT_90 = 1, |
164 | OMAP_DSS_ROT_180 = 2, |
165 | OMAP_DSS_ROT_270 = 3, |
166 | }; |
167 | |
168 | enum omap_overlay_caps { |
169 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, |
170 | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, |
171 | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, |
172 | OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, |
173 | OMAP_DSS_OVL_CAP_POS = 1 << 4, |
174 | OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, |
175 | }; |
176 | |
177 | enum omap_dss_output_id { |
178 | OMAP_DSS_OUTPUT_DPI = 1 << 0, |
179 | OMAP_DSS_OUTPUT_DBI = 1 << 1, |
180 | OMAP_DSS_OUTPUT_SDI = 1 << 2, |
181 | OMAP_DSS_OUTPUT_DSI1 = 1 << 3, |
182 | OMAP_DSS_OUTPUT_DSI2 = 1 << 4, |
183 | OMAP_DSS_OUTPUT_VENC = 1 << 5, |
184 | OMAP_DSS_OUTPUT_HDMI = 1 << 6, |
185 | }; |
186 | |
187 | /* DSI */ |
188 | |
189 | enum omap_dss_dsi_trans_mode { |
190 | /* Sync Pulses: both sync start and end packets sent */ |
191 | OMAP_DSS_DSI_PULSE_MODE, |
192 | /* Sync Events: only sync start packets sent */ |
193 | OMAP_DSS_DSI_EVENT_MODE, |
194 | /* Burst: only sync start packets sent, pixels are time compressed */ |
195 | OMAP_DSS_DSI_BURST_MODE, |
196 | }; |
197 | |
198 | struct omap_dss_dsi_videomode_timings { |
199 | unsigned long hsclk; |
200 | |
201 | unsigned ndl; |
202 | unsigned bitspp; |
203 | |
204 | /* pixels */ |
205 | u16 hact; |
206 | /* lines */ |
207 | u16 vact; |
208 | |
209 | /* DSI video mode blanking data */ |
210 | /* Unit: byte clock cycles */ |
211 | u16 hss; |
212 | u16 hsa; |
213 | u16 hse; |
214 | u16 hfp; |
215 | u16 hbp; |
216 | /* Unit: line clocks */ |
217 | u16 vsa; |
218 | u16 vfp; |
219 | u16 vbp; |
220 | |
221 | /* DSI blanking modes */ |
222 | int blanking_mode; |
223 | int hsa_blanking_mode; |
224 | int hbp_blanking_mode; |
225 | int hfp_blanking_mode; |
226 | |
227 | enum omap_dss_dsi_trans_mode trans_mode; |
228 | |
229 | bool ddr_clk_always_on; |
230 | int window_sync; |
231 | }; |
232 | |
233 | struct omap_dss_dsi_config { |
234 | enum omap_dss_dsi_mode mode; |
235 | enum omap_dss_dsi_pixel_format pixel_format; |
236 | const struct omap_video_timings *timings; |
237 | |
238 | unsigned long hs_clk_min, hs_clk_max; |
239 | unsigned long lp_clk_min, lp_clk_max; |
240 | |
241 | bool ddr_clk_always_on; |
242 | enum omap_dss_dsi_trans_mode trans_mode; |
243 | }; |
244 | |
245 | struct omap_video_timings { |
246 | /* Unit: pixels */ |
247 | u16 x_res; |
248 | /* Unit: pixels */ |
249 | u16 y_res; |
250 | /* Unit: Hz */ |
251 | u32 pixelclock; |
252 | /* Unit: pixel clocks */ |
253 | u16 hsw; /* Horizontal synchronization pulse width */ |
254 | /* Unit: pixel clocks */ |
255 | u16 hfp; /* Horizontal front porch */ |
256 | /* Unit: pixel clocks */ |
257 | u16 hbp; /* Horizontal back porch */ |
258 | /* Unit: line clocks */ |
259 | u16 vsw; /* Vertical synchronization pulse width */ |
260 | /* Unit: line clocks */ |
261 | u16 vfp; /* Vertical front porch */ |
262 | /* Unit: line clocks */ |
263 | u16 vbp; /* Vertical back porch */ |
264 | |
265 | /* Vsync logic level */ |
266 | enum omap_dss_signal_level vsync_level; |
267 | /* Hsync logic level */ |
268 | enum omap_dss_signal_level hsync_level; |
269 | /* Interlaced or Progressive timings */ |
270 | bool interlace; |
271 | /* Pixel clock edge to drive LCD data */ |
272 | enum omap_dss_signal_edge data_pclk_edge; |
273 | /* Data enable logic level */ |
274 | enum omap_dss_signal_level de_level; |
275 | /* Pixel clock edges to drive HSYNC and VSYNC signals */ |
276 | enum omap_dss_signal_edge sync_pclk_edge; |
277 | |
278 | bool double_pixel; |
279 | }; |
280 | |
281 | /* Hardcoded timings for tv modes. Venc only uses these to |
282 | * identify the mode, and does not actually use the configs |
283 | * itself. However, the configs should be something that |
284 | * a normal monitor can also show */ |
285 | extern const struct omap_video_timings omap_dss_pal_timings; |
286 | extern const struct omap_video_timings omap_dss_ntsc_timings; |
287 | |
288 | struct omap_dss_cpr_coefs { |
289 | s16 rr, rg, rb; |
290 | s16 gr, gg, gb; |
291 | s16 br, bg, bb; |
292 | }; |
293 | |
294 | struct omap_overlay_info { |
295 | dma_addr_t paddr; |
296 | dma_addr_t p_uv_addr; /* for NV12 format */ |
297 | u16 screen_width; |
298 | u16 width; |
299 | u16 height; |
300 | enum omap_color_mode color_mode; |
301 | u8 rotation; |
302 | enum omap_dss_rotation_type rotation_type; |
303 | bool mirror; |
304 | |
305 | u16 pos_x; |
306 | u16 pos_y; |
307 | u16 out_width; /* if 0, out_width == width */ |
308 | u16 out_height; /* if 0, out_height == height */ |
309 | u8 global_alpha; |
310 | u8 pre_mult_alpha; |
311 | u8 zorder; |
312 | }; |
313 | |
314 | struct omap_overlay { |
315 | struct kobject kobj; |
316 | struct list_head list; |
317 | |
318 | /* static fields */ |
319 | const char *name; |
320 | enum omap_plane id; |
321 | enum omap_color_mode supported_modes; |
322 | enum omap_overlay_caps caps; |
323 | |
324 | /* dynamic fields */ |
325 | struct omap_overlay_manager *manager; |
326 | |
327 | /* |
328 | * The following functions do not block: |
329 | * |
330 | * is_enabled |
331 | * set_overlay_info |
332 | * get_overlay_info |
333 | * |
334 | * The rest of the functions may block and cannot be called from |
335 | * interrupt context |
336 | */ |
337 | |
338 | int (*enable)(struct omap_overlay *ovl); |
339 | int (*disable)(struct omap_overlay *ovl); |
340 | bool (*is_enabled)(struct omap_overlay *ovl); |
341 | |
342 | int (*set_manager)(struct omap_overlay *ovl, |
343 | struct omap_overlay_manager *mgr); |
344 | int (*unset_manager)(struct omap_overlay *ovl); |
345 | |
346 | int (*set_overlay_info)(struct omap_overlay *ovl, |
347 | struct omap_overlay_info *info); |
348 | void (*get_overlay_info)(struct omap_overlay *ovl, |
349 | struct omap_overlay_info *info); |
350 | |
351 | int (*wait_for_go)(struct omap_overlay *ovl); |
352 | |
353 | struct omap_dss_device *(*get_device)(struct omap_overlay *ovl); |
354 | }; |
355 | |
356 | struct omap_overlay_manager_info { |
357 | u32 default_color; |
358 | |
359 | enum omap_dss_trans_key_type trans_key_type; |
360 | u32 trans_key; |
361 | bool trans_enabled; |
362 | |
363 | bool partial_alpha_enabled; |
364 | |
365 | bool cpr_enable; |
366 | struct omap_dss_cpr_coefs cpr_coefs; |
367 | }; |
368 | |
369 | struct omap_overlay_manager { |
370 | struct kobject kobj; |
371 | |
372 | /* static fields */ |
373 | const char *name; |
374 | enum omap_channel id; |
375 | struct list_head overlays; |
376 | enum omap_display_type supported_displays; |
377 | enum omap_dss_output_id supported_outputs; |
378 | |
379 | /* dynamic fields */ |
380 | struct omap_dss_device *output; |
381 | |
382 | /* |
383 | * The following functions do not block: |
384 | * |
385 | * set_manager_info |
386 | * get_manager_info |
387 | * apply |
388 | * |
389 | * The rest of the functions may block and cannot be called from |
390 | * interrupt context |
391 | */ |
392 | |
393 | int (*set_output)(struct omap_overlay_manager *mgr, |
394 | struct omap_dss_device *output); |
395 | int (*unset_output)(struct omap_overlay_manager *mgr); |
396 | |
397 | int (*set_manager_info)(struct omap_overlay_manager *mgr, |
398 | struct omap_overlay_manager_info *info); |
399 | void (*get_manager_info)(struct omap_overlay_manager *mgr, |
400 | struct omap_overlay_manager_info *info); |
401 | |
402 | int (*apply)(struct omap_overlay_manager *mgr); |
403 | int (*wait_for_go)(struct omap_overlay_manager *mgr); |
404 | int (*wait_for_vsync)(struct omap_overlay_manager *mgr); |
405 | |
406 | struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); |
407 | }; |
408 | |
409 | /* 22 pins means 1 clk lane and 10 data lanes */ |
410 | #define OMAP_DSS_MAX_DSI_PINS 22 |
411 | |
412 | struct omap_dsi_pin_config { |
413 | int num_pins; |
414 | /* |
415 | * pin numbers in the following order: |
416 | * clk+, clk- |
417 | * data1+, data1- |
418 | * data2+, data2- |
419 | * ... |
420 | */ |
421 | int pins[OMAP_DSS_MAX_DSI_PINS]; |
422 | }; |
423 | |
424 | struct omap_dss_writeback_info { |
425 | u32 paddr; |
426 | u32 p_uv_addr; |
427 | u16 buf_width; |
428 | u16 width; |
429 | u16 height; |
430 | enum omap_color_mode color_mode; |
431 | u8 rotation; |
432 | enum omap_dss_rotation_type rotation_type; |
433 | bool mirror; |
434 | u8 pre_mult_alpha; |
435 | }; |
436 | |
437 | struct omapdss_dpi_ops { |
438 | int (*connect)(struct omap_dss_device *dssdev, |
439 | struct omap_dss_device *dst); |
440 | void (*disconnect)(struct omap_dss_device *dssdev, |
441 | struct omap_dss_device *dst); |
442 | |
443 | int (*enable)(struct omap_dss_device *dssdev); |
444 | void (*disable)(struct omap_dss_device *dssdev); |
445 | |
446 | int (*check_timings)(struct omap_dss_device *dssdev, |
447 | struct omap_video_timings *timings); |
448 | void (*set_timings)(struct omap_dss_device *dssdev, |
449 | struct omap_video_timings *timings); |
450 | void (*get_timings)(struct omap_dss_device *dssdev, |
451 | struct omap_video_timings *timings); |
452 | |
453 | void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines); |
454 | }; |
455 | |
456 | struct omapdss_sdi_ops { |
457 | int (*connect)(struct omap_dss_device *dssdev, |
458 | struct omap_dss_device *dst); |
459 | void (*disconnect)(struct omap_dss_device *dssdev, |
460 | struct omap_dss_device *dst); |
461 | |
462 | int (*enable)(struct omap_dss_device *dssdev); |
463 | void (*disable)(struct omap_dss_device *dssdev); |
464 | |
465 | int (*check_timings)(struct omap_dss_device *dssdev, |
466 | struct omap_video_timings *timings); |
467 | void (*set_timings)(struct omap_dss_device *dssdev, |
468 | struct omap_video_timings *timings); |
469 | void (*get_timings)(struct omap_dss_device *dssdev, |
470 | struct omap_video_timings *timings); |
471 | |
472 | void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs); |
473 | }; |
474 | |
475 | struct omapdss_dvi_ops { |
476 | int (*connect)(struct omap_dss_device *dssdev, |
477 | struct omap_dss_device *dst); |
478 | void (*disconnect)(struct omap_dss_device *dssdev, |
479 | struct omap_dss_device *dst); |
480 | |
481 | int (*enable)(struct omap_dss_device *dssdev); |
482 | void (*disable)(struct omap_dss_device *dssdev); |
483 | |
484 | int (*check_timings)(struct omap_dss_device *dssdev, |
485 | struct omap_video_timings *timings); |
486 | void (*set_timings)(struct omap_dss_device *dssdev, |
487 | struct omap_video_timings *timings); |
488 | void (*get_timings)(struct omap_dss_device *dssdev, |
489 | struct omap_video_timings *timings); |
490 | }; |
491 | |
492 | struct omapdss_atv_ops { |
493 | int (*connect)(struct omap_dss_device *dssdev, |
494 | struct omap_dss_device *dst); |
495 | void (*disconnect)(struct omap_dss_device *dssdev, |
496 | struct omap_dss_device *dst); |
497 | |
498 | int (*enable)(struct omap_dss_device *dssdev); |
499 | void (*disable)(struct omap_dss_device *dssdev); |
500 | |
501 | int (*check_timings)(struct omap_dss_device *dssdev, |
502 | struct omap_video_timings *timings); |
503 | void (*set_timings)(struct omap_dss_device *dssdev, |
504 | struct omap_video_timings *timings); |
505 | void (*get_timings)(struct omap_dss_device *dssdev, |
506 | struct omap_video_timings *timings); |
507 | |
508 | void (*set_type)(struct omap_dss_device *dssdev, |
509 | enum omap_dss_venc_type type); |
510 | void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev, |
511 | bool invert_polarity); |
512 | |
513 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
514 | u32 (*get_wss)(struct omap_dss_device *dssdev); |
515 | }; |
516 | |
517 | struct omapdss_hdmi_ops { |
518 | int (*connect)(struct omap_dss_device *dssdev, |
519 | struct omap_dss_device *dst); |
520 | void (*disconnect)(struct omap_dss_device *dssdev, |
521 | struct omap_dss_device *dst); |
522 | |
523 | int (*enable)(struct omap_dss_device *dssdev); |
524 | void (*disable)(struct omap_dss_device *dssdev); |
525 | |
526 | int (*check_timings)(struct omap_dss_device *dssdev, |
527 | struct omap_video_timings *timings); |
528 | void (*set_timings)(struct omap_dss_device *dssdev, |
529 | struct omap_video_timings *timings); |
530 | void (*get_timings)(struct omap_dss_device *dssdev, |
531 | struct omap_video_timings *timings); |
532 | |
533 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); |
534 | bool (*detect)(struct omap_dss_device *dssdev); |
535 | |
536 | int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); |
537 | int (*set_infoframe)(struct omap_dss_device *dssdev, |
538 | const struct hdmi_avi_infoframe *avi); |
539 | }; |
540 | |
541 | struct omapdss_dsi_ops { |
542 | int (*connect)(struct omap_dss_device *dssdev, |
543 | struct omap_dss_device *dst); |
544 | void (*disconnect)(struct omap_dss_device *dssdev, |
545 | struct omap_dss_device *dst); |
546 | |
547 | int (*enable)(struct omap_dss_device *dssdev); |
548 | void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes, |
549 | bool enter_ulps); |
550 | |
551 | /* bus configuration */ |
552 | int (*set_config)(struct omap_dss_device *dssdev, |
553 | const struct omap_dss_dsi_config *cfg); |
554 | int (*configure_pins)(struct omap_dss_device *dssdev, |
555 | const struct omap_dsi_pin_config *pin_cfg); |
556 | |
557 | void (*enable_hs)(struct omap_dss_device *dssdev, int channel, |
558 | bool enable); |
559 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); |
560 | |
561 | int (*update)(struct omap_dss_device *dssdev, int channel, |
562 | void (*callback)(int, void *), void *data); |
563 | |
564 | void (*bus_lock)(struct omap_dss_device *dssdev); |
565 | void (*bus_unlock)(struct omap_dss_device *dssdev); |
566 | |
567 | int (*enable_video_output)(struct omap_dss_device *dssdev, int channel); |
568 | void (*disable_video_output)(struct omap_dss_device *dssdev, |
569 | int channel); |
570 | |
571 | int (*request_vc)(struct omap_dss_device *dssdev, int *channel); |
572 | int (*set_vc_id)(struct omap_dss_device *dssdev, int channel, |
573 | int vc_id); |
574 | void (*release_vc)(struct omap_dss_device *dssdev, int channel); |
575 | |
576 | /* data transfer */ |
577 | int (*dcs_write)(struct omap_dss_device *dssdev, int channel, |
578 | u8 *data, int len); |
579 | int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel, |
580 | u8 *data, int len); |
581 | int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
582 | u8 *data, int len); |
583 | |
584 | int (*gen_write)(struct omap_dss_device *dssdev, int channel, |
585 | u8 *data, int len); |
586 | int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel, |
587 | u8 *data, int len); |
588 | int (*gen_read)(struct omap_dss_device *dssdev, int channel, |
589 | u8 *reqdata, int reqlen, |
590 | u8 *data, int len); |
591 | |
592 | int (*bta_sync)(struct omap_dss_device *dssdev, int channel); |
593 | |
594 | int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev, |
595 | int channel, u16 plen); |
596 | }; |
597 | |
598 | struct omap_dss_device { |
599 | struct kobject kobj; |
600 | struct device *dev; |
601 | |
602 | struct module *owner; |
603 | |
604 | struct list_head panel_list; |
605 | |
606 | /* alias in the form of "display%d" */ |
607 | char alias[16]; |
608 | |
609 | enum omap_display_type type; |
610 | enum omap_display_type output_type; |
611 | |
612 | union { |
613 | struct { |
614 | u8 data_lines; |
615 | } dpi; |
616 | |
617 | struct { |
618 | u8 datapairs; |
619 | } sdi; |
620 | |
621 | struct { |
622 | int module; |
623 | } dsi; |
624 | |
625 | struct { |
626 | enum omap_dss_venc_type type; |
627 | bool invert_polarity; |
628 | } venc; |
629 | } phy; |
630 | |
631 | struct { |
632 | struct omap_video_timings timings; |
633 | |
634 | enum omap_dss_dsi_pixel_format dsi_pix_fmt; |
635 | enum omap_dss_dsi_mode dsi_mode; |
636 | } panel; |
637 | |
638 | struct { |
639 | u8 pixel_size; |
640 | } ctrl; |
641 | |
642 | const char *name; |
643 | |
644 | /* used to match device to driver */ |
645 | const char *driver_name; |
646 | |
647 | void *data; |
648 | |
649 | struct omap_dss_driver *driver; |
650 | |
651 | union { |
652 | const struct omapdss_dpi_ops *dpi; |
653 | const struct omapdss_sdi_ops *sdi; |
654 | const struct omapdss_dvi_ops *dvi; |
655 | const struct omapdss_hdmi_ops *hdmi; |
656 | const struct omapdss_atv_ops *atv; |
657 | const struct omapdss_dsi_ops *dsi; |
658 | } ops; |
659 | |
660 | /* helper variable for driver suspend/resume */ |
661 | bool activate_after_resume; |
662 | |
663 | enum omap_display_caps caps; |
664 | |
665 | struct omap_dss_device *src; |
666 | |
667 | enum omap_dss_display_state state; |
668 | |
669 | /* OMAP DSS output specific fields */ |
670 | |
671 | struct list_head list; |
672 | |
673 | /* DISPC channel for this output */ |
674 | enum omap_channel dispc_channel; |
675 | bool dispc_channel_connected; |
676 | |
677 | /* output instance */ |
678 | enum omap_dss_output_id id; |
679 | |
680 | /* the port number in the DT node */ |
681 | int port_num; |
682 | |
683 | /* dynamic fields */ |
684 | struct omap_overlay_manager *manager; |
685 | |
686 | struct omap_dss_device *dst; |
687 | }; |
688 | |
689 | struct omap_dss_driver { |
690 | int (*probe)(struct omap_dss_device *); |
691 | void (*remove)(struct omap_dss_device *); |
692 | |
693 | int (*connect)(struct omap_dss_device *dssdev); |
694 | void (*disconnect)(struct omap_dss_device *dssdev); |
695 | |
696 | int (*enable)(struct omap_dss_device *display); |
697 | void (*disable)(struct omap_dss_device *display); |
698 | int (*run_test)(struct omap_dss_device *display, int test); |
699 | |
700 | int (*update)(struct omap_dss_device *dssdev, |
701 | u16 x, u16 y, u16 w, u16 h); |
702 | int (*sync)(struct omap_dss_device *dssdev); |
703 | |
704 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); |
705 | int (*get_te)(struct omap_dss_device *dssdev); |
706 | |
707 | u8 (*get_rotate)(struct omap_dss_device *dssdev); |
708 | int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); |
709 | |
710 | bool (*get_mirror)(struct omap_dss_device *dssdev); |
711 | int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); |
712 | |
713 | int (*memory_read)(struct omap_dss_device *dssdev, |
714 | void *buf, size_t size, |
715 | u16 x, u16 y, u16 w, u16 h); |
716 | |
717 | void (*get_resolution)(struct omap_dss_device *dssdev, |
718 | u16 *xres, u16 *yres); |
719 | void (*get_dimensions)(struct omap_dss_device *dssdev, |
720 | u32 *width, u32 *height); |
721 | int (*get_recommended_bpp)(struct omap_dss_device *dssdev); |
722 | |
723 | int (*check_timings)(struct omap_dss_device *dssdev, |
724 | struct omap_video_timings *timings); |
725 | void (*set_timings)(struct omap_dss_device *dssdev, |
726 | struct omap_video_timings *timings); |
727 | void (*get_timings)(struct omap_dss_device *dssdev, |
728 | struct omap_video_timings *timings); |
729 | |
730 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
731 | u32 (*get_wss)(struct omap_dss_device *dssdev); |
732 | |
733 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); |
734 | bool (*detect)(struct omap_dss_device *dssdev); |
735 | |
736 | int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); |
737 | int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev, |
738 | const struct hdmi_avi_infoframe *avi); |
739 | }; |
740 | |
741 | #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) |
742 | |
743 | typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); |
744 | |
745 | #if IS_ENABLED(CONFIG_FB_OMAP2) |
746 | |
747 | enum omapdss_version omapdss_get_version(void); |
748 | bool omapdss_is_initialized(void); |
749 | |
750 | int omap_dss_register_driver(struct omap_dss_driver *); |
751 | void omap_dss_unregister_driver(struct omap_dss_driver *); |
752 | |
753 | int omapdss_register_display(struct omap_dss_device *dssdev); |
754 | void omapdss_unregister_display(struct omap_dss_device *dssdev); |
755 | |
756 | struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev); |
757 | void omap_dss_put_device(struct omap_dss_device *dssdev); |
758 | struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); |
759 | struct omap_dss_device *omap_dss_find_device(void *data, |
760 | int (*match)(struct omap_dss_device *dssdev, void *data)); |
761 | const char *omapdss_get_default_display_name(void); |
762 | |
763 | void videomode_to_omap_video_timings(const struct videomode *vm, |
764 | struct omap_video_timings *ovt); |
765 | void omap_video_timings_to_videomode(const struct omap_video_timings *ovt, |
766 | struct videomode *vm); |
767 | |
768 | int dss_feat_get_num_mgrs(void); |
769 | int dss_feat_get_num_ovls(void); |
770 | enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); |
771 | |
772 | |
773 | |
774 | int omap_dss_get_num_overlay_managers(void); |
775 | struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); |
776 | |
777 | int omap_dss_get_num_overlays(void); |
778 | struct omap_overlay *omap_dss_get_overlay(int num); |
779 | |
780 | int omapdss_register_output(struct omap_dss_device *output); |
781 | void omapdss_unregister_output(struct omap_dss_device *output); |
782 | struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id); |
783 | struct omap_dss_device *omap_dss_find_output(const char *name); |
784 | struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port); |
785 | int omapdss_output_set_device(struct omap_dss_device *out, |
786 | struct omap_dss_device *dssdev); |
787 | int omapdss_output_unset_device(struct omap_dss_device *out); |
788 | |
789 | struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); |
790 | struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev); |
791 | |
792 | void omapdss_default_get_resolution(struct omap_dss_device *dssdev, |
793 | u16 *xres, u16 *yres); |
794 | int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); |
795 | void omapdss_default_get_timings(struct omap_dss_device *dssdev, |
796 | struct omap_video_timings *timings); |
797 | |
798 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); |
799 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); |
800 | |
801 | int omapdss_compat_init(void); |
802 | void omapdss_compat_uninit(void); |
803 | |
804 | static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev) |
805 | { |
806 | return dssdev->src; |
807 | } |
808 | |
809 | static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) |
810 | { |
811 | return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; |
812 | } |
813 | |
814 | struct device_node * |
815 | omapdss_of_get_next_port(const struct device_node *parent, |
816 | struct device_node *prev); |
817 | |
818 | struct device_node * |
819 | omapdss_of_get_next_endpoint(const struct device_node *parent, |
820 | struct device_node *prev); |
821 | |
822 | struct device_node * |
823 | omapdss_of_get_first_endpoint(const struct device_node *parent); |
824 | |
825 | struct omap_dss_device * |
826 | omapdss_of_find_source_for_first_ep(struct device_node *node); |
827 | #else |
828 | |
829 | static inline enum omapdss_version omapdss_get_version(void) |
830 | { return OMAPDSS_VER_UNKNOWN; }; |
831 | |
832 | static inline bool omapdss_is_initialized(void) |
833 | { return false; }; |
834 | |
835 | static inline int omap_dispc_register_isr(omap_dispc_isr_t isr, |
836 | void *arg, u32 mask) |
837 | { return 0; }; |
838 | |
839 | static inline int omap_dispc_unregister_isr(omap_dispc_isr_t isr, |
840 | void *arg, u32 mask) |
841 | { return 0; }; |
842 | |
843 | static inline struct omap_dss_device |
844 | *omap_dss_get_device(struct omap_dss_device *dssdev) |
845 | { return NULL; }; |
846 | |
847 | static inline struct omap_dss_device |
848 | *omap_dss_get_next_device(struct omap_dss_device *from) |
849 | {return NULL; }; |
850 | |
851 | static inline void omap_dss_put_device(struct omap_dss_device *dssdev) {}; |
852 | |
853 | static inline int omapdss_compat_init(void) |
854 | { return 0; }; |
855 | |
856 | static inline void omapdss_compat_uninit(void) {}; |
857 | |
858 | static inline int omap_dss_get_num_overlay_managers(void) |
859 | { return 0; }; |
860 | |
861 | static inline struct omap_overlay_manager *omap_dss_get_overlay_manager(int num) |
862 | { return NULL; }; |
863 | |
864 | static inline int omap_dss_get_num_overlays(void) |
865 | { return 0; }; |
866 | |
867 | static inline struct omap_overlay *omap_dss_get_overlay(int num) |
868 | { return NULL; }; |
869 | |
870 | |
871 | #endif /* FB_OMAP2 */ |
872 | |
873 | |
874 | #endif /* __OMAPFB_DSS_H */ |
875 | |