1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Driver for ESS Maestro3/Allegro (ES1988) soundcards. |
4 | * Copyright (c) 2000 by Zach Brown <zab@zabbo.net> |
5 | * Takashi Iwai <tiwai@suse.de> |
6 | * |
7 | * Most of the hardware init stuffs are based on maestro3 driver for |
8 | * OSS/Free by Zach Brown. Many thanks to Zach! |
9 | * |
10 | * ChangeLog: |
11 | * Aug. 27, 2001 |
12 | * - Fixed deadlock on capture |
13 | * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org> |
14 | */ |
15 | |
16 | #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2" |
17 | #define DRIVER_NAME "Maestro3" |
18 | |
19 | #include <linux/io.h> |
20 | #include <linux/delay.h> |
21 | #include <linux/interrupt.h> |
22 | #include <linux/init.h> |
23 | #include <linux/pci.h> |
24 | #include <linux/dma-mapping.h> |
25 | #include <linux/slab.h> |
26 | #include <linux/vmalloc.h> |
27 | #include <linux/module.h> |
28 | #include <linux/firmware.h> |
29 | #include <linux/input.h> |
30 | #include <sound/core.h> |
31 | #include <sound/info.h> |
32 | #include <sound/control.h> |
33 | #include <sound/pcm.h> |
34 | #include <sound/mpu401.h> |
35 | #include <sound/ac97_codec.h> |
36 | #include <sound/initval.h> |
37 | #include <asm/byteorder.h> |
38 | |
39 | MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>" ); |
40 | MODULE_DESCRIPTION("ESS Maestro3 PCI" ); |
41 | MODULE_LICENSE("GPL" ); |
42 | MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw" ); |
43 | MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw" ); |
44 | |
45 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
46 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
47 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */ |
48 | static bool external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; |
49 | static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; |
50 | |
51 | module_param_array(index, int, NULL, 0444); |
52 | MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard." ); |
53 | module_param_array(id, charp, NULL, 0444); |
54 | MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard." ); |
55 | module_param_array(enable, bool, NULL, 0444); |
56 | MODULE_PARM_DESC(enable, "Enable this soundcard." ); |
57 | module_param_array(external_amp, bool, NULL, 0444); |
58 | MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard." ); |
59 | module_param_array(amp_gpio, int, NULL, 0444); |
60 | MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)" ); |
61 | |
62 | #define MAX_PLAYBACKS 2 |
63 | #define MAX_CAPTURES 1 |
64 | #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES) |
65 | |
66 | |
67 | /* |
68 | * maestro3 registers |
69 | */ |
70 | |
71 | /* Allegro PCI configuration registers */ |
72 | #define PCI_LEGACY_AUDIO_CTRL 0x40 |
73 | #define SOUND_BLASTER_ENABLE 0x00000001 |
74 | #define FM_SYNTHESIS_ENABLE 0x00000002 |
75 | #define GAME_PORT_ENABLE 0x00000004 |
76 | #define MPU401_IO_ENABLE 0x00000008 |
77 | #define MPU401_IRQ_ENABLE 0x00000010 |
78 | #define ALIAS_10BIT_IO 0x00000020 |
79 | #define SB_DMA_MASK 0x000000C0 |
80 | #define SB_DMA_0 0x00000040 |
81 | #define SB_DMA_1 0x00000040 |
82 | #define SB_DMA_R 0x00000080 |
83 | #define SB_DMA_3 0x000000C0 |
84 | #define SB_IRQ_MASK 0x00000700 |
85 | #define SB_IRQ_5 0x00000000 |
86 | #define SB_IRQ_7 0x00000100 |
87 | #define SB_IRQ_9 0x00000200 |
88 | #define SB_IRQ_10 0x00000300 |
89 | #define MIDI_IRQ_MASK 0x00003800 |
90 | #define SERIAL_IRQ_ENABLE 0x00004000 |
91 | #define DISABLE_LEGACY 0x00008000 |
92 | |
93 | #define PCI_ALLEGRO_CONFIG 0x50 |
94 | #define SB_ADDR_240 0x00000004 |
95 | #define MPU_ADDR_MASK 0x00000018 |
96 | #define MPU_ADDR_330 0x00000000 |
97 | #define MPU_ADDR_300 0x00000008 |
98 | #define MPU_ADDR_320 0x00000010 |
99 | #define MPU_ADDR_340 0x00000018 |
100 | #define USE_PCI_TIMING 0x00000040 |
101 | #define POSTED_WRITE_ENABLE 0x00000080 |
102 | #define DMA_POLICY_MASK 0x00000700 |
103 | #define DMA_DDMA 0x00000000 |
104 | #define DMA_TDMA 0x00000100 |
105 | #define DMA_PCPCI 0x00000200 |
106 | #define DMA_WBDMA16 0x00000400 |
107 | #define DMA_WBDMA4 0x00000500 |
108 | #define DMA_WBDMA2 0x00000600 |
109 | #define DMA_WBDMA1 0x00000700 |
110 | #define DMA_SAFE_GUARD 0x00000800 |
111 | #define HI_PERF_GP_ENABLE 0x00001000 |
112 | #define PIC_SNOOP_MODE_0 0x00002000 |
113 | #define PIC_SNOOP_MODE_1 0x00004000 |
114 | #define SOUNDBLASTER_IRQ_MASK 0x00008000 |
115 | #define RING_IN_ENABLE 0x00010000 |
116 | #define SPDIF_TEST_MODE 0x00020000 |
117 | #define CLK_MULT_MODE_SELECT_2 0x00040000 |
118 | #define EEPROM_WRITE_ENABLE 0x00080000 |
119 | #define CODEC_DIR_IN 0x00100000 |
120 | #define HV_BUTTON_FROM_GD 0x00200000 |
121 | #define REDUCED_DEBOUNCE 0x00400000 |
122 | #define HV_CTRL_ENABLE 0x00800000 |
123 | #define SPDIF_ENABLE 0x01000000 |
124 | #define CLK_DIV_SELECT 0x06000000 |
125 | #define CLK_DIV_BY_48 0x00000000 |
126 | #define CLK_DIV_BY_49 0x02000000 |
127 | #define CLK_DIV_BY_50 0x04000000 |
128 | #define CLK_DIV_RESERVED 0x06000000 |
129 | #define PM_CTRL_ENABLE 0x08000000 |
130 | #define CLK_MULT_MODE_SELECT 0x30000000 |
131 | #define CLK_MULT_MODE_SHIFT 28 |
132 | #define CLK_MULT_MODE_0 0x00000000 |
133 | #define CLK_MULT_MODE_1 0x10000000 |
134 | #define CLK_MULT_MODE_2 0x20000000 |
135 | #define CLK_MULT_MODE_3 0x30000000 |
136 | #define INT_CLK_SELECT 0x40000000 |
137 | #define INT_CLK_MULT_RESET 0x80000000 |
138 | |
139 | /* M3 */ |
140 | #define INT_CLK_SRC_NOT_PCI 0x00100000 |
141 | #define INT_CLK_MULT_ENABLE 0x80000000 |
142 | |
143 | #define PCI_ACPI_CONTROL 0x54 |
144 | #define PCI_ACPI_D0 0x00000000 |
145 | #define PCI_ACPI_D1 0xB4F70000 |
146 | #define PCI_ACPI_D2 0xB4F7B4F7 |
147 | |
148 | #define PCI_USER_CONFIG 0x58 |
149 | #define EXT_PCI_MASTER_ENABLE 0x00000001 |
150 | #define SPDIF_OUT_SELECT 0x00000002 |
151 | #define TEST_PIN_DIR_CTRL 0x00000004 |
152 | #define AC97_CODEC_TEST 0x00000020 |
153 | #define TRI_STATE_BUFFER 0x00000080 |
154 | #define IN_CLK_12MHZ_SELECT 0x00000100 |
155 | #define MULTI_FUNC_DISABLE 0x00000200 |
156 | #define EXT_MASTER_PAIR_SEL 0x00000400 |
157 | #define PCI_MASTER_SUPPORT 0x00000800 |
158 | #define STOP_CLOCK_ENABLE 0x00001000 |
159 | #define EAPD_DRIVE_ENABLE 0x00002000 |
160 | #define REQ_TRI_STATE_ENABLE 0x00004000 |
161 | #define REQ_LOW_ENABLE 0x00008000 |
162 | #define MIDI_1_ENABLE 0x00010000 |
163 | #define MIDI_2_ENABLE 0x00020000 |
164 | #define SB_AUDIO_SYNC 0x00040000 |
165 | #define HV_CTRL_TEST 0x00100000 |
166 | #define SOUNDBLASTER_TEST 0x00400000 |
167 | |
168 | #define PCI_USER_CONFIG_C 0x5C |
169 | |
170 | #define PCI_DDMA_CTRL 0x60 |
171 | #define DDMA_ENABLE 0x00000001 |
172 | |
173 | |
174 | /* Allegro registers */ |
175 | #define HOST_INT_CTRL 0x18 |
176 | #define SB_INT_ENABLE 0x0001 |
177 | #define MPU401_INT_ENABLE 0x0002 |
178 | #define ASSP_INT_ENABLE 0x0010 |
179 | #define RING_INT_ENABLE 0x0020 |
180 | #define HV_INT_ENABLE 0x0040 |
181 | #define CLKRUN_GEN_ENABLE 0x0100 |
182 | #define HV_CTRL_TO_PME 0x0400 |
183 | #define SOFTWARE_RESET_ENABLE 0x8000 |
184 | |
185 | /* |
186 | * should be using the above defines, probably. |
187 | */ |
188 | #define REGB_ENABLE_RESET 0x01 |
189 | #define REGB_STOP_CLOCK 0x10 |
190 | |
191 | #define HOST_INT_STATUS 0x1A |
192 | #define SB_INT_PENDING 0x01 |
193 | #define MPU401_INT_PENDING 0x02 |
194 | #define ASSP_INT_PENDING 0x10 |
195 | #define RING_INT_PENDING 0x20 |
196 | #define HV_INT_PENDING 0x40 |
197 | |
198 | #define HARDWARE_VOL_CTRL 0x1B |
199 | #define SHADOW_MIX_REG_VOICE 0x1C |
200 | #define HW_VOL_COUNTER_VOICE 0x1D |
201 | #define SHADOW_MIX_REG_MASTER 0x1E |
202 | #define HW_VOL_COUNTER_MASTER 0x1F |
203 | |
204 | #define CODEC_COMMAND 0x30 |
205 | #define CODEC_READ_B 0x80 |
206 | |
207 | #define CODEC_STATUS 0x30 |
208 | #define CODEC_BUSY_B 0x01 |
209 | |
210 | #define CODEC_DATA 0x32 |
211 | |
212 | #define RING_BUS_CTRL_A 0x36 |
213 | #define RAC_PME_ENABLE 0x0100 |
214 | #define RAC_SDFS_ENABLE 0x0200 |
215 | #define LAC_PME_ENABLE 0x0400 |
216 | #define LAC_SDFS_ENABLE 0x0800 |
217 | #define SERIAL_AC_LINK_ENABLE 0x1000 |
218 | #define IO_SRAM_ENABLE 0x2000 |
219 | #define IIS_INPUT_ENABLE 0x8000 |
220 | |
221 | #define RING_BUS_CTRL_B 0x38 |
222 | #define SECOND_CODEC_ID_MASK 0x0003 |
223 | #define SPDIF_FUNC_ENABLE 0x0010 |
224 | #define SECOND_AC_ENABLE 0x0020 |
225 | #define SB_MODULE_INTF_ENABLE 0x0040 |
226 | #define SSPE_ENABLE 0x0040 |
227 | #define M3I_DOCK_ENABLE 0x0080 |
228 | |
229 | #define SDO_OUT_DEST_CTRL 0x3A |
230 | #define COMMAND_ADDR_OUT 0x0003 |
231 | #define PCM_LR_OUT_LOCAL 0x0000 |
232 | #define PCM_LR_OUT_REMOTE 0x0004 |
233 | #define PCM_LR_OUT_MUTE 0x0008 |
234 | #define PCM_LR_OUT_BOTH 0x000C |
235 | #define LINE1_DAC_OUT_LOCAL 0x0000 |
236 | #define LINE1_DAC_OUT_REMOTE 0x0010 |
237 | #define LINE1_DAC_OUT_MUTE 0x0020 |
238 | #define LINE1_DAC_OUT_BOTH 0x0030 |
239 | #define PCM_CLS_OUT_LOCAL 0x0000 |
240 | #define PCM_CLS_OUT_REMOTE 0x0040 |
241 | #define PCM_CLS_OUT_MUTE 0x0080 |
242 | #define PCM_CLS_OUT_BOTH 0x00C0 |
243 | #define PCM_RLF_OUT_LOCAL 0x0000 |
244 | #define PCM_RLF_OUT_REMOTE 0x0100 |
245 | #define PCM_RLF_OUT_MUTE 0x0200 |
246 | #define PCM_RLF_OUT_BOTH 0x0300 |
247 | #define LINE2_DAC_OUT_LOCAL 0x0000 |
248 | #define LINE2_DAC_OUT_REMOTE 0x0400 |
249 | #define LINE2_DAC_OUT_MUTE 0x0800 |
250 | #define LINE2_DAC_OUT_BOTH 0x0C00 |
251 | #define HANDSET_OUT_LOCAL 0x0000 |
252 | #define HANDSET_OUT_REMOTE 0x1000 |
253 | #define HANDSET_OUT_MUTE 0x2000 |
254 | #define HANDSET_OUT_BOTH 0x3000 |
255 | #define IO_CTRL_OUT_LOCAL 0x0000 |
256 | #define IO_CTRL_OUT_REMOTE 0x4000 |
257 | #define IO_CTRL_OUT_MUTE 0x8000 |
258 | #define IO_CTRL_OUT_BOTH 0xC000 |
259 | |
260 | #define SDO_IN_DEST_CTRL 0x3C |
261 | #define STATUS_ADDR_IN 0x0003 |
262 | #define PCM_LR_IN_LOCAL 0x0000 |
263 | #define PCM_LR_IN_REMOTE 0x0004 |
264 | #define PCM_LR_RESERVED 0x0008 |
265 | #define PCM_LR_IN_BOTH 0x000C |
266 | #define LINE1_ADC_IN_LOCAL 0x0000 |
267 | #define LINE1_ADC_IN_REMOTE 0x0010 |
268 | #define LINE1_ADC_IN_MUTE 0x0020 |
269 | #define MIC_ADC_IN_LOCAL 0x0000 |
270 | #define MIC_ADC_IN_REMOTE 0x0040 |
271 | #define MIC_ADC_IN_MUTE 0x0080 |
272 | #define LINE2_DAC_IN_LOCAL 0x0000 |
273 | #define LINE2_DAC_IN_REMOTE 0x0400 |
274 | #define LINE2_DAC_IN_MUTE 0x0800 |
275 | #define HANDSET_IN_LOCAL 0x0000 |
276 | #define HANDSET_IN_REMOTE 0x1000 |
277 | #define HANDSET_IN_MUTE 0x2000 |
278 | #define IO_STATUS_IN_LOCAL 0x0000 |
279 | #define IO_STATUS_IN_REMOTE 0x4000 |
280 | |
281 | #define SPDIF_IN_CTRL 0x3E |
282 | #define SPDIF_IN_ENABLE 0x0001 |
283 | |
284 | #define GPIO_DATA 0x60 |
285 | #define GPIO_DATA_MASK 0x0FFF |
286 | #define GPIO_HV_STATUS 0x3000 |
287 | #define GPIO_PME_STATUS 0x4000 |
288 | |
289 | #define GPIO_MASK 0x64 |
290 | #define GPIO_DIRECTION 0x68 |
291 | #define GPO_PRIMARY_AC97 0x0001 |
292 | #define GPI_LINEOUT_SENSE 0x0004 |
293 | #define GPO_SECONDARY_AC97 0x0008 |
294 | #define GPI_VOL_DOWN 0x0010 |
295 | #define GPI_VOL_UP 0x0020 |
296 | #define GPI_IIS_CLK 0x0040 |
297 | #define GPI_IIS_LRCLK 0x0080 |
298 | #define GPI_IIS_DATA 0x0100 |
299 | #define GPI_DOCKING_STATUS 0x0100 |
300 | #define GPI_HEADPHONE_SENSE 0x0200 |
301 | #define GPO_EXT_AMP_SHUTDOWN 0x1000 |
302 | |
303 | #define GPO_EXT_AMP_M3 1 /* default m3 amp */ |
304 | #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */ |
305 | |
306 | /* M3 */ |
307 | #define GPO_M3_EXT_AMP_SHUTDN 0x0002 |
308 | |
309 | #define ASSP_INDEX_PORT 0x80 |
310 | #define ASSP_MEMORY_PORT 0x82 |
311 | #define ASSP_DATA_PORT 0x84 |
312 | |
313 | #define MPU401_DATA_PORT 0x98 |
314 | #define MPU401_STATUS_PORT 0x99 |
315 | |
316 | #define CLK_MULT_DATA_PORT 0x9C |
317 | |
318 | #define ASSP_CONTROL_A 0xA2 |
319 | #define ASSP_0_WS_ENABLE 0x01 |
320 | #define ASSP_CTRL_A_RESERVED1 0x02 |
321 | #define ASSP_CTRL_A_RESERVED2 0x04 |
322 | #define ASSP_CLK_49MHZ_SELECT 0x08 |
323 | #define FAST_PLU_ENABLE 0x10 |
324 | #define ASSP_CTRL_A_RESERVED3 0x20 |
325 | #define DSP_CLK_36MHZ_SELECT 0x40 |
326 | |
327 | #define ASSP_CONTROL_B 0xA4 |
328 | #define RESET_ASSP 0x00 |
329 | #define RUN_ASSP 0x01 |
330 | #define ENABLE_ASSP_CLOCK 0x00 |
331 | #define STOP_ASSP_CLOCK 0x10 |
332 | #define RESET_TOGGLE 0x40 |
333 | |
334 | #define ASSP_CONTROL_C 0xA6 |
335 | #define ASSP_HOST_INT_ENABLE 0x01 |
336 | #define FM_ADDR_REMAP_DISABLE 0x02 |
337 | #define HOST_WRITE_PORT_ENABLE 0x08 |
338 | |
339 | #define ASSP_HOST_INT_STATUS 0xAC |
340 | #define DSP2HOST_REQ_PIORECORD 0x01 |
341 | #define DSP2HOST_REQ_I2SRATE 0x02 |
342 | #define DSP2HOST_REQ_TIMER 0x04 |
343 | |
344 | /* |
345 | * ASSP control regs |
346 | */ |
347 | #define DSP_PORT_TIMER_COUNT 0x06 |
348 | |
349 | #define DSP_PORT_MEMORY_INDEX 0x80 |
350 | |
351 | #define DSP_PORT_MEMORY_TYPE 0x82 |
352 | #define MEMTYPE_INTERNAL_CODE 0x0002 |
353 | #define MEMTYPE_INTERNAL_DATA 0x0003 |
354 | #define MEMTYPE_MASK 0x0003 |
355 | |
356 | #define DSP_PORT_MEMORY_DATA 0x84 |
357 | |
358 | #define DSP_PORT_CONTROL_REG_A 0xA2 |
359 | #define DSP_PORT_CONTROL_REG_B 0xA4 |
360 | #define DSP_PORT_CONTROL_REG_C 0xA6 |
361 | |
362 | #define REV_A_CODE_MEMORY_BEGIN 0x0000 |
363 | #define REV_A_CODE_MEMORY_END 0x0FFF |
364 | #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 |
365 | #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) |
366 | |
367 | #define REV_B_CODE_MEMORY_BEGIN 0x0000 |
368 | #define REV_B_CODE_MEMORY_END 0x0BFF |
369 | #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 |
370 | #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) |
371 | |
372 | #define REV_A_DATA_MEMORY_BEGIN 0x1000 |
373 | #define REV_A_DATA_MEMORY_END 0x2FFF |
374 | #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 |
375 | #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) |
376 | |
377 | #define REV_B_DATA_MEMORY_BEGIN 0x1000 |
378 | #define REV_B_DATA_MEMORY_END 0x2BFF |
379 | #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 |
380 | #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) |
381 | |
382 | |
383 | #define NUM_UNITS_KERNEL_CODE 16 |
384 | #define NUM_UNITS_KERNEL_DATA 2 |
385 | |
386 | #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 |
387 | #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 |
388 | |
389 | /* |
390 | * Kernel data layout |
391 | */ |
392 | |
393 | #define DP_SHIFT_COUNT 7 |
394 | |
395 | #define KDATA_BASE_ADDR 0x1000 |
396 | #define KDATA_BASE_ADDR2 0x1080 |
397 | |
398 | #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) |
399 | #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) |
400 | #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) |
401 | #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) |
402 | #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) |
403 | #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) |
404 | #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) |
405 | #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) |
406 | #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) |
407 | |
408 | #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) |
409 | #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) |
410 | |
411 | #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) |
412 | #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) |
413 | #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) |
414 | #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) |
415 | #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) |
416 | #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) |
417 | #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) |
418 | #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) |
419 | #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) |
420 | #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) |
421 | |
422 | #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) |
423 | #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) |
424 | |
425 | #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) |
426 | #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) |
427 | |
428 | #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) |
429 | #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) |
430 | |
431 | #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) |
432 | #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) |
433 | #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) |
434 | |
435 | #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) |
436 | #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) |
437 | #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) |
438 | #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) |
439 | #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) |
440 | |
441 | #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) |
442 | #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) |
443 | #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) |
444 | |
445 | #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) |
446 | #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) |
447 | #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) |
448 | |
449 | #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) |
450 | #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) |
451 | #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) |
452 | #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) |
453 | #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) |
454 | #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) |
455 | #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) |
456 | #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) |
457 | #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) |
458 | #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) |
459 | |
460 | #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) |
461 | #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) |
462 | #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) |
463 | |
464 | #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) |
465 | #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) |
466 | |
467 | #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) |
468 | #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) |
469 | #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) |
470 | |
471 | #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) |
472 | #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) |
473 | #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) |
474 | #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) |
475 | #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) |
476 | #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) |
477 | |
478 | #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) |
479 | #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) |
480 | #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) |
481 | #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) |
482 | #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) |
483 | #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) |
484 | |
485 | #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) |
486 | #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) |
487 | #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) |
488 | #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) |
489 | #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) |
490 | #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) |
491 | |
492 | #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) |
493 | #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) |
494 | #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) |
495 | #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) |
496 | |
497 | #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) |
498 | #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) |
499 | |
500 | #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) |
501 | #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) |
502 | |
503 | #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) |
504 | #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) |
505 | #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) |
506 | #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) |
507 | #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) |
508 | |
509 | #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) |
510 | #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) |
511 | |
512 | #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) |
513 | #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) |
514 | #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) |
515 | |
516 | #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) |
517 | #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) |
518 | |
519 | #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) |
520 | |
521 | #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) |
522 | #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) |
523 | #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) |
524 | #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) |
525 | #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) |
526 | #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) |
527 | #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) |
528 | #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) |
529 | #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) |
530 | #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) |
531 | #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) |
532 | #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) |
533 | |
534 | #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) |
535 | #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) |
536 | #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) |
537 | #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) |
538 | |
539 | #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) |
540 | #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) |
541 | |
542 | #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) |
543 | #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) |
544 | #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) |
545 | #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) |
546 | |
547 | #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) |
548 | #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) |
549 | #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) |
550 | #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) |
551 | #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) |
552 | |
553 | /* |
554 | * second 'segment' (?) reserved for mixer |
555 | * buffers.. |
556 | */ |
557 | |
558 | #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) |
559 | #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) |
560 | #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) |
561 | #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) |
562 | #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) |
563 | #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) |
564 | #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) |
565 | #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) |
566 | #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) |
567 | #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) |
568 | #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) |
569 | #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) |
570 | #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) |
571 | #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) |
572 | #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) |
573 | #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) |
574 | |
575 | #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) |
576 | #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) |
577 | #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) |
578 | #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) |
579 | #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) |
580 | #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) |
581 | #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) |
582 | #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) |
583 | #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) |
584 | #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) |
585 | #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) |
586 | |
587 | #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) |
588 | #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) |
589 | #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) |
590 | #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) |
591 | #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) |
592 | #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) |
593 | |
594 | #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) |
595 | #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) |
596 | #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) |
597 | #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) |
598 | |
599 | /* |
600 | * client data area offsets |
601 | */ |
602 | #define CDATA_INSTANCE_READY 0x00 |
603 | |
604 | #define CDATA_HOST_SRC_ADDRL 0x01 |
605 | #define CDATA_HOST_SRC_ADDRH 0x02 |
606 | #define CDATA_HOST_SRC_END_PLUS_1L 0x03 |
607 | #define CDATA_HOST_SRC_END_PLUS_1H 0x04 |
608 | #define CDATA_HOST_SRC_CURRENTL 0x05 |
609 | #define CDATA_HOST_SRC_CURRENTH 0x06 |
610 | |
611 | #define CDATA_IN_BUF_CONNECT 0x07 |
612 | #define CDATA_OUT_BUF_CONNECT 0x08 |
613 | |
614 | #define CDATA_IN_BUF_BEGIN 0x09 |
615 | #define CDATA_IN_BUF_END_PLUS_1 0x0A |
616 | #define CDATA_IN_BUF_HEAD 0x0B |
617 | #define CDATA_IN_BUF_TAIL 0x0C |
618 | #define CDATA_OUT_BUF_BEGIN 0x0D |
619 | #define CDATA_OUT_BUF_END_PLUS_1 0x0E |
620 | #define CDATA_OUT_BUF_HEAD 0x0F |
621 | #define CDATA_OUT_BUF_TAIL 0x10 |
622 | |
623 | #define CDATA_DMA_CONTROL 0x11 |
624 | #define CDATA_RESERVED 0x12 |
625 | |
626 | #define CDATA_FREQUENCY 0x13 |
627 | #define CDATA_LEFT_VOLUME 0x14 |
628 | #define CDATA_RIGHT_VOLUME 0x15 |
629 | #define CDATA_LEFT_SUR_VOL 0x16 |
630 | #define CDATA_RIGHT_SUR_VOL 0x17 |
631 | |
632 | #define 0x18 |
633 | |
634 | #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN |
635 | #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) |
636 | #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) |
637 | #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) |
638 | #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) |
639 | #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) |
640 | #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) |
641 | #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) |
642 | |
643 | #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) |
644 | #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) |
645 | #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) |
646 | #define MINISRC_BIQUAD_STAGE 2 |
647 | #define MINISRC_COEF_LOC 0x175 |
648 | |
649 | #define DMACONTROL_BLOCK_MASK 0x000F |
650 | #define DMAC_BLOCK0_SELECTOR 0x0000 |
651 | #define DMAC_BLOCK1_SELECTOR 0x0001 |
652 | #define DMAC_BLOCK2_SELECTOR 0x0002 |
653 | #define DMAC_BLOCK3_SELECTOR 0x0003 |
654 | #define DMAC_BLOCK4_SELECTOR 0x0004 |
655 | #define DMAC_BLOCK5_SELECTOR 0x0005 |
656 | #define DMAC_BLOCK6_SELECTOR 0x0006 |
657 | #define DMAC_BLOCK7_SELECTOR 0x0007 |
658 | #define DMAC_BLOCK8_SELECTOR 0x0008 |
659 | #define DMAC_BLOCK9_SELECTOR 0x0009 |
660 | #define DMAC_BLOCKA_SELECTOR 0x000A |
661 | #define DMAC_BLOCKB_SELECTOR 0x000B |
662 | #define DMAC_BLOCKC_SELECTOR 0x000C |
663 | #define DMAC_BLOCKD_SELECTOR 0x000D |
664 | #define DMAC_BLOCKE_SELECTOR 0x000E |
665 | #define DMAC_BLOCKF_SELECTOR 0x000F |
666 | #define DMACONTROL_PAGE_MASK 0x00F0 |
667 | #define DMAC_PAGE0_SELECTOR 0x0030 |
668 | #define DMAC_PAGE1_SELECTOR 0x0020 |
669 | #define DMAC_PAGE2_SELECTOR 0x0010 |
670 | #define DMAC_PAGE3_SELECTOR 0x0000 |
671 | #define DMACONTROL_AUTOREPEAT 0x1000 |
672 | #define DMACONTROL_STOPPED 0x2000 |
673 | #define DMACONTROL_DIRECTION 0x0100 |
674 | |
675 | /* |
676 | * an arbitrary volume we set the internal |
677 | * volume settings to so that the ac97 volume |
678 | * range is a little less insane. 0x7fff is |
679 | * max. |
680 | */ |
681 | #define ARB_VOLUME ( 0x6800 ) |
682 | |
683 | /* |
684 | */ |
685 | |
686 | struct m3_list { |
687 | int curlen; |
688 | int mem_addr; |
689 | int max; |
690 | }; |
691 | |
692 | struct m3_dma { |
693 | |
694 | int number; |
695 | struct snd_pcm_substream *substream; |
696 | |
697 | struct assp_instance { |
698 | unsigned short code, data; |
699 | } inst; |
700 | |
701 | int running; |
702 | int opened; |
703 | |
704 | unsigned long buffer_addr; |
705 | int dma_size; |
706 | int period_size; |
707 | unsigned int hwptr; |
708 | int count; |
709 | |
710 | int index[3]; |
711 | struct m3_list *index_list[3]; |
712 | |
713 | int in_lists; |
714 | |
715 | struct list_head list; |
716 | |
717 | }; |
718 | |
719 | struct snd_m3 { |
720 | |
721 | struct snd_card *card; |
722 | |
723 | unsigned long iobase; |
724 | |
725 | int irq; |
726 | unsigned int allegro_flag : 1; |
727 | |
728 | struct snd_ac97 *ac97; |
729 | |
730 | struct snd_pcm *pcm; |
731 | |
732 | struct pci_dev *pci; |
733 | |
734 | int dacs_active; |
735 | int timer_users; |
736 | |
737 | struct m3_list msrc_list; |
738 | struct m3_list mixer_list; |
739 | struct m3_list adc1_list; |
740 | struct m3_list dma_list; |
741 | |
742 | /* for storing reset state..*/ |
743 | u8 reset_state; |
744 | |
745 | int external_amp; |
746 | int amp_gpio; /* gpio pin # for external amp, -1 = default */ |
747 | unsigned int hv_config; /* hardware-volume config bits */ |
748 | unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION |
749 | (e.g. for IrDA on Dell Inspirons) */ |
750 | unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */ |
751 | |
752 | /* midi */ |
753 | struct snd_rawmidi *rmidi; |
754 | |
755 | /* pcm streams */ |
756 | int num_substreams; |
757 | struct m3_dma *substreams; |
758 | |
759 | spinlock_t reg_lock; |
760 | |
761 | #ifdef CONFIG_SND_MAESTRO3_INPUT |
762 | struct input_dev *input_dev; |
763 | char phys[64]; /* physical device path */ |
764 | #else |
765 | struct snd_kcontrol *master_switch; |
766 | struct snd_kcontrol *master_volume; |
767 | #endif |
768 | struct work_struct hwvol_work; |
769 | |
770 | unsigned int in_suspend; |
771 | |
772 | #ifdef CONFIG_PM_SLEEP |
773 | u16 *suspend_mem; |
774 | #endif |
775 | |
776 | const struct firmware *assp_kernel_image; |
777 | const struct firmware *assp_minisrc_image; |
778 | }; |
779 | |
780 | /* |
781 | * pci ids |
782 | */ |
783 | static const struct pci_device_id snd_m3_ids[] = { |
784 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID, |
785 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
786 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID, |
787 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
788 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID, |
789 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
790 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID, |
791 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
792 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID, |
793 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
794 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID, |
795 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
796 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID, |
797 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
798 | {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID, |
799 | PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, |
800 | {0,}, |
801 | }; |
802 | |
803 | MODULE_DEVICE_TABLE(pci, snd_m3_ids); |
804 | |
805 | static const struct snd_pci_quirk m3_amp_quirk_list[] = { |
806 | SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c" , 0x0c), |
807 | SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28" , 0x0d), |
808 | SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72" , 0x0d), |
809 | SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7" , 0x03), |
810 | SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF" , 0x03), |
811 | { } /* END */ |
812 | }; |
813 | |
814 | static const struct snd_pci_quirk m3_irda_quirk_list[] = { |
815 | SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000" , 1), |
816 | SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000" , 1), |
817 | SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100" , 1), |
818 | { } /* END */ |
819 | }; |
820 | |
821 | /* hardware volume quirks */ |
822 | static const struct snd_pci_quirk m3_hv_quirk_list[] = { |
823 | /* Allegro chips */ |
824 | SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
825 | SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
826 | SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
827 | SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
828 | SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
829 | SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
830 | SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
831 | SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
832 | SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
833 | SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
834 | SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
835 | SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
836 | SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
837 | SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
838 | SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
839 | SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
840 | SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
841 | SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
842 | SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
843 | SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
844 | SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
845 | SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
846 | SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
847 | SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
848 | SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD), |
849 | SND_PCI_QUIRK(0x1033, 0x80F1, NULL, |
850 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
851 | SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */ |
852 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
853 | SND_PCI_QUIRK(0x107B, 0x340A, NULL, |
854 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
855 | SND_PCI_QUIRK(0x107B, 0x3450, NULL, |
856 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
857 | SND_PCI_QUIRK(0x109F, 0x3134, NULL, |
858 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
859 | SND_PCI_QUIRK(0x109F, 0x3161, NULL, |
860 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
861 | SND_PCI_QUIRK(0x144D, 0x3280, NULL, |
862 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
863 | SND_PCI_QUIRK(0x144D, 0x3281, NULL, |
864 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
865 | SND_PCI_QUIRK(0x144D, 0xC002, NULL, |
866 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
867 | SND_PCI_QUIRK(0x144D, 0xC003, NULL, |
868 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
869 | SND_PCI_QUIRK(0x1509, 0x1740, NULL, |
870 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
871 | SND_PCI_QUIRK(0x1610, 0x0010, NULL, |
872 | HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE), |
873 | SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE), |
874 | SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE), |
875 | SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE), |
876 | SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE), |
877 | SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE), |
878 | /* Maestro3 chips */ |
879 | SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE), |
880 | SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE), |
881 | SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE), |
882 | SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE), |
883 | SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE), |
884 | SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE), |
885 | SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE), |
886 | SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE), |
887 | SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE), |
888 | SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE), |
889 | SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE), |
890 | SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE), |
891 | SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE), |
892 | SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), |
893 | SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), |
894 | SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), |
895 | SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE), |
896 | { } /* END */ |
897 | }; |
898 | |
899 | /* HP Omnibook quirks */ |
900 | static const struct snd_pci_quirk m3_omnibook_quirk_list[] = { |
901 | SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */ |
902 | SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */ |
903 | { } /* END */ |
904 | }; |
905 | |
906 | /* |
907 | * lowlevel functions |
908 | */ |
909 | |
910 | static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg) |
911 | { |
912 | outw(value, port: chip->iobase + reg); |
913 | } |
914 | |
915 | static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg) |
916 | { |
917 | return inw(port: chip->iobase + reg); |
918 | } |
919 | |
920 | static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg) |
921 | { |
922 | outb(value, port: chip->iobase + reg); |
923 | } |
924 | |
925 | static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg) |
926 | { |
927 | return inb(port: chip->iobase + reg); |
928 | } |
929 | |
930 | /* |
931 | * access 16bit words to the code or data regions of the dsp's memory. |
932 | * index addresses 16bit words. |
933 | */ |
934 | static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index) |
935 | { |
936 | snd_m3_outw(chip, value: region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); |
937 | snd_m3_outw(chip, value: index, DSP_PORT_MEMORY_INDEX); |
938 | return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA); |
939 | } |
940 | |
941 | static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data) |
942 | { |
943 | snd_m3_outw(chip, value: region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); |
944 | snd_m3_outw(chip, value: index, DSP_PORT_MEMORY_INDEX); |
945 | snd_m3_outw(chip, value: data, DSP_PORT_MEMORY_DATA); |
946 | } |
947 | |
948 | static void snd_m3_assp_halt(struct snd_m3 *chip) |
949 | { |
950 | chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; |
951 | msleep(msecs: 10); |
952 | snd_m3_outb(chip, value: chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); |
953 | } |
954 | |
955 | static void snd_m3_assp_continue(struct snd_m3 *chip) |
956 | { |
957 | snd_m3_outb(chip, value: chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); |
958 | } |
959 | |
960 | |
961 | /* |
962 | * This makes me sad. the maestro3 has lists |
963 | * internally that must be packed.. 0 terminates, |
964 | * apparently, or maybe all unused entries have |
965 | * to be 0, the lists have static lengths set |
966 | * by the binary code images. |
967 | */ |
968 | |
969 | static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val) |
970 | { |
971 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
972 | index: list->mem_addr + list->curlen, |
973 | data: val); |
974 | return list->curlen++; |
975 | } |
976 | |
977 | static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index) |
978 | { |
979 | u16 val; |
980 | int lastindex = list->curlen - 1; |
981 | |
982 | if (index != lastindex) { |
983 | val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
984 | index: list->mem_addr + lastindex); |
985 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
986 | index: list->mem_addr + index, |
987 | data: val); |
988 | } |
989 | |
990 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
991 | index: list->mem_addr + lastindex, |
992 | data: 0); |
993 | |
994 | list->curlen--; |
995 | } |
996 | |
997 | static void snd_m3_inc_timer_users(struct snd_m3 *chip) |
998 | { |
999 | chip->timer_users++; |
1000 | if (chip->timer_users != 1) |
1001 | return; |
1002 | |
1003 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1004 | KDATA_TIMER_COUNT_RELOAD, |
1005 | data: 240); |
1006 | |
1007 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1008 | KDATA_TIMER_COUNT_CURRENT, |
1009 | data: 240); |
1010 | |
1011 | snd_m3_outw(chip, |
1012 | value: snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE, |
1013 | HOST_INT_CTRL); |
1014 | } |
1015 | |
1016 | static void snd_m3_dec_timer_users(struct snd_m3 *chip) |
1017 | { |
1018 | chip->timer_users--; |
1019 | if (chip->timer_users > 0) |
1020 | return; |
1021 | |
1022 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1023 | KDATA_TIMER_COUNT_RELOAD, |
1024 | data: 0); |
1025 | |
1026 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1027 | KDATA_TIMER_COUNT_CURRENT, |
1028 | data: 0); |
1029 | |
1030 | snd_m3_outw(chip, |
1031 | value: snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE, |
1032 | HOST_INT_CTRL); |
1033 | } |
1034 | |
1035 | /* |
1036 | * start/stop |
1037 | */ |
1038 | |
1039 | /* spinlock held! */ |
1040 | static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s, |
1041 | struct snd_pcm_substream *subs) |
1042 | { |
1043 | if (! s || ! subs) |
1044 | return -EINVAL; |
1045 | |
1046 | snd_m3_inc_timer_users(chip); |
1047 | switch (subs->stream) { |
1048 | case SNDRV_PCM_STREAM_PLAYBACK: |
1049 | chip->dacs_active++; |
1050 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1051 | index: s->inst.data + CDATA_INSTANCE_READY, data: 1); |
1052 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1053 | KDATA_MIXER_TASK_NUMBER, |
1054 | data: chip->dacs_active); |
1055 | break; |
1056 | case SNDRV_PCM_STREAM_CAPTURE: |
1057 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1058 | KDATA_ADC1_REQUEST, data: 1); |
1059 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1060 | index: s->inst.data + CDATA_INSTANCE_READY, data: 1); |
1061 | break; |
1062 | } |
1063 | return 0; |
1064 | } |
1065 | |
1066 | /* spinlock held! */ |
1067 | static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s, |
1068 | struct snd_pcm_substream *subs) |
1069 | { |
1070 | if (! s || ! subs) |
1071 | return -EINVAL; |
1072 | |
1073 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1074 | index: s->inst.data + CDATA_INSTANCE_READY, data: 0); |
1075 | snd_m3_dec_timer_users(chip); |
1076 | switch (subs->stream) { |
1077 | case SNDRV_PCM_STREAM_PLAYBACK: |
1078 | chip->dacs_active--; |
1079 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1080 | KDATA_MIXER_TASK_NUMBER, |
1081 | data: chip->dacs_active); |
1082 | break; |
1083 | case SNDRV_PCM_STREAM_CAPTURE: |
1084 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1085 | KDATA_ADC1_REQUEST, data: 0); |
1086 | break; |
1087 | } |
1088 | return 0; |
1089 | } |
1090 | |
1091 | static int |
1092 | snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd) |
1093 | { |
1094 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1095 | struct m3_dma *s = subs->runtime->private_data; |
1096 | int err = -EINVAL; |
1097 | |
1098 | if (snd_BUG_ON(!s)) |
1099 | return -ENXIO; |
1100 | |
1101 | spin_lock(lock: &chip->reg_lock); |
1102 | switch (cmd) { |
1103 | case SNDRV_PCM_TRIGGER_START: |
1104 | case SNDRV_PCM_TRIGGER_RESUME: |
1105 | if (s->running) |
1106 | err = -EBUSY; |
1107 | else { |
1108 | s->running = 1; |
1109 | err = snd_m3_pcm_start(chip, s, subs); |
1110 | } |
1111 | break; |
1112 | case SNDRV_PCM_TRIGGER_STOP: |
1113 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1114 | if (! s->running) |
1115 | err = 0; /* should return error? */ |
1116 | else { |
1117 | s->running = 0; |
1118 | err = snd_m3_pcm_stop(chip, s, subs); |
1119 | } |
1120 | break; |
1121 | } |
1122 | spin_unlock(lock: &chip->reg_lock); |
1123 | return err; |
1124 | } |
1125 | |
1126 | /* |
1127 | * setup |
1128 | */ |
1129 | static void |
1130 | snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) |
1131 | { |
1132 | int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer; |
1133 | struct snd_pcm_runtime *runtime = subs->runtime; |
1134 | |
1135 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
1136 | dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); |
1137 | dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); |
1138 | } else { |
1139 | dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); |
1140 | dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); |
1141 | } |
1142 | dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2); |
1143 | dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1; |
1144 | |
1145 | s->dma_size = frames_to_bytes(runtime, size: runtime->buffer_size); |
1146 | s->period_size = frames_to_bytes(runtime, size: runtime->period_size); |
1147 | s->hwptr = 0; |
1148 | s->count = 0; |
1149 | |
1150 | #define LO(x) ((x) & 0xffff) |
1151 | #define HI(x) LO((x) >> 16) |
1152 | |
1153 | /* host dma buffer pointers */ |
1154 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1155 | index: s->inst.data + CDATA_HOST_SRC_ADDRL, |
1156 | LO(s->buffer_addr)); |
1157 | |
1158 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1159 | index: s->inst.data + CDATA_HOST_SRC_ADDRH, |
1160 | HI(s->buffer_addr)); |
1161 | |
1162 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1163 | index: s->inst.data + CDATA_HOST_SRC_END_PLUS_1L, |
1164 | LO(s->buffer_addr + s->dma_size)); |
1165 | |
1166 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1167 | index: s->inst.data + CDATA_HOST_SRC_END_PLUS_1H, |
1168 | HI(s->buffer_addr + s->dma_size)); |
1169 | |
1170 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1171 | index: s->inst.data + CDATA_HOST_SRC_CURRENTL, |
1172 | LO(s->buffer_addr)); |
1173 | |
1174 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1175 | index: s->inst.data + CDATA_HOST_SRC_CURRENTH, |
1176 | HI(s->buffer_addr)); |
1177 | #undef LO |
1178 | #undef HI |
1179 | |
1180 | /* dsp buffers */ |
1181 | |
1182 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1183 | index: s->inst.data + CDATA_IN_BUF_BEGIN, |
1184 | data: dsp_in_buffer); |
1185 | |
1186 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1187 | index: s->inst.data + CDATA_IN_BUF_END_PLUS_1, |
1188 | data: dsp_in_buffer + (dsp_in_size / 2)); |
1189 | |
1190 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1191 | index: s->inst.data + CDATA_IN_BUF_HEAD, |
1192 | data: dsp_in_buffer); |
1193 | |
1194 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1195 | index: s->inst.data + CDATA_IN_BUF_TAIL, |
1196 | data: dsp_in_buffer); |
1197 | |
1198 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1199 | index: s->inst.data + CDATA_OUT_BUF_BEGIN, |
1200 | data: dsp_out_buffer); |
1201 | |
1202 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1203 | index: s->inst.data + CDATA_OUT_BUF_END_PLUS_1, |
1204 | data: dsp_out_buffer + (dsp_out_size / 2)); |
1205 | |
1206 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1207 | index: s->inst.data + CDATA_OUT_BUF_HEAD, |
1208 | data: dsp_out_buffer); |
1209 | |
1210 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1211 | index: s->inst.data + CDATA_OUT_BUF_TAIL, |
1212 | data: dsp_out_buffer); |
1213 | } |
1214 | |
1215 | static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s, |
1216 | struct snd_pcm_runtime *runtime) |
1217 | { |
1218 | u32 freq; |
1219 | |
1220 | /* |
1221 | * put us in the lists if we're not already there |
1222 | */ |
1223 | if (! s->in_lists) { |
1224 | s->index[0] = snd_m3_add_list(chip, list: s->index_list[0], |
1225 | val: s->inst.data >> DP_SHIFT_COUNT); |
1226 | s->index[1] = snd_m3_add_list(chip, list: s->index_list[1], |
1227 | val: s->inst.data >> DP_SHIFT_COUNT); |
1228 | s->index[2] = snd_m3_add_list(chip, list: s->index_list[2], |
1229 | val: s->inst.data >> DP_SHIFT_COUNT); |
1230 | s->in_lists = 1; |
1231 | } |
1232 | |
1233 | /* write to 'mono' word */ |
1234 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1235 | index: s->inst.data + SRC3_DIRECTION_OFFSET + 1, |
1236 | data: runtime->channels == 2 ? 0 : 1); |
1237 | /* write to '8bit' word */ |
1238 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1239 | index: s->inst.data + SRC3_DIRECTION_OFFSET + 2, |
1240 | data: snd_pcm_format_width(format: runtime->format) == 16 ? 0 : 1); |
1241 | |
1242 | /* set up dac/adc rate */ |
1243 | freq = DIV_ROUND_CLOSEST(runtime->rate << 15, 48000); |
1244 | if (freq) |
1245 | freq--; |
1246 | |
1247 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1248 | index: s->inst.data + CDATA_FREQUENCY, |
1249 | data: freq); |
1250 | } |
1251 | |
1252 | |
1253 | static const struct play_vals { |
1254 | u16 addr, val; |
1255 | } pv[] = { |
1256 | {CDATA_LEFT_VOLUME, ARB_VOLUME}, |
1257 | {CDATA_RIGHT_VOLUME, ARB_VOLUME}, |
1258 | {SRC3_DIRECTION_OFFSET, 0} , |
1259 | /* +1, +2 are stereo/16 bit */ |
1260 | {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ |
1261 | {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ |
1262 | {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ |
1263 | {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ |
1264 | {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ |
1265 | {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ |
1266 | {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ |
1267 | {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ |
1268 | {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ |
1269 | {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ |
1270 | {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ |
1271 | {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ |
1272 | {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ |
1273 | {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ |
1274 | {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ |
1275 | {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ |
1276 | {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ |
1277 | }; |
1278 | |
1279 | |
1280 | /* the mode passed should be already shifted and masked */ |
1281 | static void |
1282 | snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s, |
1283 | struct snd_pcm_substream *subs) |
1284 | { |
1285 | unsigned int i; |
1286 | |
1287 | /* |
1288 | * some per client initializers |
1289 | */ |
1290 | |
1291 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1292 | index: s->inst.data + SRC3_DIRECTION_OFFSET + 12, |
1293 | data: s->inst.data + 40 + 8); |
1294 | |
1295 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1296 | index: s->inst.data + SRC3_DIRECTION_OFFSET + 19, |
1297 | data: s->inst.code + MINISRC_COEF_LOC); |
1298 | |
1299 | /* enable or disable low pass filter? */ |
1300 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1301 | index: s->inst.data + SRC3_DIRECTION_OFFSET + 22, |
1302 | data: subs->runtime->rate > 45000 ? 0xff : 0); |
1303 | |
1304 | /* tell it which way dma is going? */ |
1305 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1306 | index: s->inst.data + CDATA_DMA_CONTROL, |
1307 | DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); |
1308 | |
1309 | /* |
1310 | * set an armload of static initializers |
1311 | */ |
1312 | for (i = 0; i < ARRAY_SIZE(pv); i++) |
1313 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1314 | index: s->inst.data + pv[i].addr, data: pv[i].val); |
1315 | } |
1316 | |
1317 | /* |
1318 | * Native record driver |
1319 | */ |
1320 | static const struct rec_vals { |
1321 | u16 addr, val; |
1322 | } rv[] = { |
1323 | {CDATA_LEFT_VOLUME, ARB_VOLUME}, |
1324 | {CDATA_RIGHT_VOLUME, ARB_VOLUME}, |
1325 | {SRC3_DIRECTION_OFFSET, 1} , |
1326 | /* +1, +2 are stereo/16 bit */ |
1327 | {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ |
1328 | {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ |
1329 | {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ |
1330 | {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ |
1331 | {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ |
1332 | {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ |
1333 | {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ |
1334 | {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ |
1335 | {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ |
1336 | {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ |
1337 | {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ |
1338 | {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ |
1339 | {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ |
1340 | {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ |
1341 | {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ |
1342 | {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ |
1343 | {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ |
1344 | {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ |
1345 | {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ |
1346 | }; |
1347 | |
1348 | static void |
1349 | snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) |
1350 | { |
1351 | unsigned int i; |
1352 | |
1353 | /* |
1354 | * some per client initializers |
1355 | */ |
1356 | |
1357 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1358 | index: s->inst.data + SRC3_DIRECTION_OFFSET + 12, |
1359 | data: s->inst.data + 40 + 8); |
1360 | |
1361 | /* tell it which way dma is going? */ |
1362 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1363 | index: s->inst.data + CDATA_DMA_CONTROL, |
1364 | DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + |
1365 | DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); |
1366 | |
1367 | /* |
1368 | * set an armload of static initializers |
1369 | */ |
1370 | for (i = 0; i < ARRAY_SIZE(rv); i++) |
1371 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
1372 | index: s->inst.data + rv[i].addr, data: rv[i].val); |
1373 | } |
1374 | |
1375 | static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream, |
1376 | struct snd_pcm_hw_params *hw_params) |
1377 | { |
1378 | struct m3_dma *s = substream->runtime->private_data; |
1379 | |
1380 | /* set buffer address */ |
1381 | s->buffer_addr = substream->runtime->dma_addr; |
1382 | if (s->buffer_addr & 0x3) { |
1383 | dev_err(substream->pcm->card->dev, "oh my, not aligned\n" ); |
1384 | s->buffer_addr = s->buffer_addr & ~0x3; |
1385 | } |
1386 | return 0; |
1387 | } |
1388 | |
1389 | static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream) |
1390 | { |
1391 | struct m3_dma *s; |
1392 | |
1393 | if (substream->runtime->private_data == NULL) |
1394 | return 0; |
1395 | s = substream->runtime->private_data; |
1396 | s->buffer_addr = 0; |
1397 | return 0; |
1398 | } |
1399 | |
1400 | static int |
1401 | snd_m3_pcm_prepare(struct snd_pcm_substream *subs) |
1402 | { |
1403 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1404 | struct snd_pcm_runtime *runtime = subs->runtime; |
1405 | struct m3_dma *s = runtime->private_data; |
1406 | |
1407 | if (snd_BUG_ON(!s)) |
1408 | return -ENXIO; |
1409 | |
1410 | if (runtime->format != SNDRV_PCM_FORMAT_U8 && |
1411 | runtime->format != SNDRV_PCM_FORMAT_S16_LE) |
1412 | return -EINVAL; |
1413 | if (runtime->rate > 48000 || |
1414 | runtime->rate < 8000) |
1415 | return -EINVAL; |
1416 | |
1417 | spin_lock_irq(lock: &chip->reg_lock); |
1418 | |
1419 | snd_m3_pcm_setup1(chip, s, subs); |
1420 | |
1421 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) |
1422 | snd_m3_playback_setup(chip, s, subs); |
1423 | else |
1424 | snd_m3_capture_setup(chip, s, subs); |
1425 | |
1426 | snd_m3_pcm_setup2(chip, s, runtime); |
1427 | |
1428 | spin_unlock_irq(lock: &chip->reg_lock); |
1429 | |
1430 | return 0; |
1431 | } |
1432 | |
1433 | /* |
1434 | * get current pointer |
1435 | */ |
1436 | static unsigned int |
1437 | snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs) |
1438 | { |
1439 | u16 hi = 0, lo = 0; |
1440 | int retry = 10; |
1441 | u32 addr; |
1442 | |
1443 | /* |
1444 | * try and get a valid answer |
1445 | */ |
1446 | while (retry--) { |
1447 | hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
1448 | index: s->inst.data + CDATA_HOST_SRC_CURRENTH); |
1449 | |
1450 | lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
1451 | index: s->inst.data + CDATA_HOST_SRC_CURRENTL); |
1452 | |
1453 | if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, |
1454 | index: s->inst.data + CDATA_HOST_SRC_CURRENTH)) |
1455 | break; |
1456 | } |
1457 | addr = lo | ((u32)hi<<16); |
1458 | return (unsigned int)(addr - s->buffer_addr); |
1459 | } |
1460 | |
1461 | static snd_pcm_uframes_t |
1462 | snd_m3_pcm_pointer(struct snd_pcm_substream *subs) |
1463 | { |
1464 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1465 | unsigned int ptr; |
1466 | struct m3_dma *s = subs->runtime->private_data; |
1467 | |
1468 | if (snd_BUG_ON(!s)) |
1469 | return 0; |
1470 | |
1471 | spin_lock(lock: &chip->reg_lock); |
1472 | ptr = snd_m3_get_pointer(chip, s, subs); |
1473 | spin_unlock(lock: &chip->reg_lock); |
1474 | return bytes_to_frames(runtime: subs->runtime, size: ptr); |
1475 | } |
1476 | |
1477 | |
1478 | /* update pointer */ |
1479 | /* spinlock held! */ |
1480 | static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s) |
1481 | { |
1482 | struct snd_pcm_substream *subs = s->substream; |
1483 | unsigned int hwptr; |
1484 | int diff; |
1485 | |
1486 | if (! s->running) |
1487 | return; |
1488 | |
1489 | hwptr = snd_m3_get_pointer(chip, s, subs); |
1490 | |
1491 | /* try to avoid expensive modulo divisions */ |
1492 | if (hwptr >= s->dma_size) |
1493 | hwptr %= s->dma_size; |
1494 | |
1495 | diff = s->dma_size + hwptr - s->hwptr; |
1496 | if (diff >= s->dma_size) |
1497 | diff %= s->dma_size; |
1498 | |
1499 | s->hwptr = hwptr; |
1500 | s->count += diff; |
1501 | |
1502 | if (s->count >= (signed)s->period_size) { |
1503 | |
1504 | if (s->count < 2 * (signed)s->period_size) |
1505 | s->count -= (signed)s->period_size; |
1506 | else |
1507 | s->count %= s->period_size; |
1508 | |
1509 | spin_unlock(lock: &chip->reg_lock); |
1510 | snd_pcm_period_elapsed(substream: subs); |
1511 | spin_lock(lock: &chip->reg_lock); |
1512 | } |
1513 | } |
1514 | |
1515 | /* The m3's hardware volume works by incrementing / decrementing 2 counters |
1516 | (without wrap around) in response to volume button presses and then |
1517 | generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7 |
1518 | of a byte wide register. The meaning of bits 0 and 4 is unknown. */ |
1519 | static void snd_m3_update_hw_volume(struct work_struct *work) |
1520 | { |
1521 | struct snd_m3 *chip = container_of(work, struct snd_m3, hwvol_work); |
1522 | int x, val; |
1523 | |
1524 | /* Figure out which volume control button was pushed, |
1525 | based on differences from the default register |
1526 | values. */ |
1527 | x = inb(port: chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee; |
1528 | |
1529 | /* Reset the volume counters to 4. Tests on the allegro integrated |
1530 | into a Compaq N600C laptop, have revealed that: |
1531 | 1) Writing any value will result in the 2 counters being reset to |
1532 | 4 so writing 0x88 is not strictly necessary |
1533 | 2) Writing to any of the 4 involved registers will reset all 4 |
1534 | of them (and reading them always returns the same value for all |
1535 | of them) |
1536 | It could be that a maestro deviates from this, so leave the code |
1537 | as is. */ |
1538 | outb(value: 0x88, port: chip->iobase + SHADOW_MIX_REG_VOICE); |
1539 | outb(value: 0x88, port: chip->iobase + HW_VOL_COUNTER_VOICE); |
1540 | outb(value: 0x88, port: chip->iobase + SHADOW_MIX_REG_MASTER); |
1541 | outb(value: 0x88, port: chip->iobase + HW_VOL_COUNTER_MASTER); |
1542 | |
1543 | /* Ignore spurious HV interrupts during suspend / resume, this avoids |
1544 | mistaking them for a mute button press. */ |
1545 | if (chip->in_suspend) |
1546 | return; |
1547 | |
1548 | #ifndef CONFIG_SND_MAESTRO3_INPUT |
1549 | if (!chip->master_switch || !chip->master_volume) |
1550 | return; |
1551 | |
1552 | val = snd_ac97_read(chip->ac97, AC97_MASTER); |
1553 | switch (x) { |
1554 | case 0x88: |
1555 | /* The counters have not changed, yet we've received a HV |
1556 | interrupt. According to tests run by various people this |
1557 | happens when pressing the mute button. */ |
1558 | val ^= 0x8000; |
1559 | break; |
1560 | case 0xaa: |
1561 | /* counters increased by 1 -> volume up */ |
1562 | if ((val & 0x7f) > 0) |
1563 | val--; |
1564 | if ((val & 0x7f00) > 0) |
1565 | val -= 0x0100; |
1566 | break; |
1567 | case 0x66: |
1568 | /* counters decreased by 1 -> volume down */ |
1569 | if ((val & 0x7f) < 0x1f) |
1570 | val++; |
1571 | if ((val & 0x7f00) < 0x1f00) |
1572 | val += 0x0100; |
1573 | break; |
1574 | } |
1575 | if (snd_ac97_update(chip->ac97, AC97_MASTER, val)) |
1576 | snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, |
1577 | &chip->master_switch->id); |
1578 | #else |
1579 | if (!chip->input_dev) |
1580 | return; |
1581 | |
1582 | val = 0; |
1583 | switch (x) { |
1584 | case 0x88: |
1585 | /* The counters have not changed, yet we've received a HV |
1586 | interrupt. According to tests run by various people this |
1587 | happens when pressing the mute button. */ |
1588 | val = KEY_MUTE; |
1589 | break; |
1590 | case 0xaa: |
1591 | /* counters increased by 1 -> volume up */ |
1592 | val = KEY_VOLUMEUP; |
1593 | break; |
1594 | case 0x66: |
1595 | /* counters decreased by 1 -> volume down */ |
1596 | val = KEY_VOLUMEDOWN; |
1597 | break; |
1598 | } |
1599 | |
1600 | if (val) { |
1601 | input_report_key(dev: chip->input_dev, code: val, value: 1); |
1602 | input_sync(dev: chip->input_dev); |
1603 | input_report_key(dev: chip->input_dev, code: val, value: 0); |
1604 | input_sync(dev: chip->input_dev); |
1605 | } |
1606 | #endif |
1607 | } |
1608 | |
1609 | static irqreturn_t snd_m3_interrupt(int irq, void *dev_id) |
1610 | { |
1611 | struct snd_m3 *chip = dev_id; |
1612 | u8 status; |
1613 | int i; |
1614 | |
1615 | status = inb(port: chip->iobase + HOST_INT_STATUS); |
1616 | |
1617 | if (status == 0xff) |
1618 | return IRQ_NONE; |
1619 | |
1620 | if (status & HV_INT_PENDING) |
1621 | schedule_work(work: &chip->hwvol_work); |
1622 | |
1623 | /* |
1624 | * ack an assp int if its running |
1625 | * and has an int pending |
1626 | */ |
1627 | if (status & ASSP_INT_PENDING) { |
1628 | u8 ctl = inb(port: chip->iobase + ASSP_CONTROL_B); |
1629 | if (!(ctl & STOP_ASSP_CLOCK)) { |
1630 | ctl = inb(port: chip->iobase + ASSP_HOST_INT_STATUS); |
1631 | if (ctl & DSP2HOST_REQ_TIMER) { |
1632 | outb(DSP2HOST_REQ_TIMER, port: chip->iobase + ASSP_HOST_INT_STATUS); |
1633 | /* update adc/dac info if it was a timer int */ |
1634 | spin_lock(lock: &chip->reg_lock); |
1635 | for (i = 0; i < chip->num_substreams; i++) { |
1636 | struct m3_dma *s = &chip->substreams[i]; |
1637 | if (s->running) |
1638 | snd_m3_update_ptr(chip, s); |
1639 | } |
1640 | spin_unlock(lock: &chip->reg_lock); |
1641 | } |
1642 | } |
1643 | } |
1644 | |
1645 | #if 0 /* TODO: not supported yet */ |
1646 | if ((status & MPU401_INT_PENDING) && chip->rmidi) |
1647 | snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); |
1648 | #endif |
1649 | |
1650 | /* ack ints */ |
1651 | outb(value: status, port: chip->iobase + HOST_INT_STATUS); |
1652 | |
1653 | return IRQ_HANDLED; |
1654 | } |
1655 | |
1656 | |
1657 | /* |
1658 | */ |
1659 | |
1660 | static const struct snd_pcm_hardware snd_m3_playback = |
1661 | { |
1662 | .info = (SNDRV_PCM_INFO_MMAP | |
1663 | SNDRV_PCM_INFO_INTERLEAVED | |
1664 | SNDRV_PCM_INFO_MMAP_VALID | |
1665 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
1666 | /*SNDRV_PCM_INFO_PAUSE |*/ |
1667 | SNDRV_PCM_INFO_RESUME), |
1668 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1669 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, |
1670 | .rate_min = 8000, |
1671 | .rate_max = 48000, |
1672 | .channels_min = 1, |
1673 | .channels_max = 2, |
1674 | .buffer_bytes_max = (512*1024), |
1675 | .period_bytes_min = 64, |
1676 | .period_bytes_max = (512*1024), |
1677 | .periods_min = 1, |
1678 | .periods_max = 1024, |
1679 | }; |
1680 | |
1681 | static const struct snd_pcm_hardware snd_m3_capture = |
1682 | { |
1683 | .info = (SNDRV_PCM_INFO_MMAP | |
1684 | SNDRV_PCM_INFO_INTERLEAVED | |
1685 | SNDRV_PCM_INFO_MMAP_VALID | |
1686 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
1687 | /*SNDRV_PCM_INFO_PAUSE |*/ |
1688 | SNDRV_PCM_INFO_RESUME), |
1689 | .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, |
1690 | .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, |
1691 | .rate_min = 8000, |
1692 | .rate_max = 48000, |
1693 | .channels_min = 1, |
1694 | .channels_max = 2, |
1695 | .buffer_bytes_max = (512*1024), |
1696 | .period_bytes_min = 64, |
1697 | .period_bytes_max = (512*1024), |
1698 | .periods_min = 1, |
1699 | .periods_max = 1024, |
1700 | }; |
1701 | |
1702 | |
1703 | /* |
1704 | */ |
1705 | |
1706 | static int |
1707 | snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs) |
1708 | { |
1709 | int i; |
1710 | struct m3_dma *s; |
1711 | |
1712 | spin_lock_irq(lock: &chip->reg_lock); |
1713 | for (i = 0; i < chip->num_substreams; i++) { |
1714 | s = &chip->substreams[i]; |
1715 | if (! s->opened) |
1716 | goto __found; |
1717 | } |
1718 | spin_unlock_irq(lock: &chip->reg_lock); |
1719 | return -ENOMEM; |
1720 | __found: |
1721 | s->opened = 1; |
1722 | s->running = 0; |
1723 | spin_unlock_irq(lock: &chip->reg_lock); |
1724 | |
1725 | subs->runtime->private_data = s; |
1726 | s->substream = subs; |
1727 | |
1728 | /* set list owners */ |
1729 | if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
1730 | s->index_list[0] = &chip->mixer_list; |
1731 | } else |
1732 | s->index_list[0] = &chip->adc1_list; |
1733 | s->index_list[1] = &chip->msrc_list; |
1734 | s->index_list[2] = &chip->dma_list; |
1735 | |
1736 | return 0; |
1737 | } |
1738 | |
1739 | static void |
1740 | snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs) |
1741 | { |
1742 | struct m3_dma *s = subs->runtime->private_data; |
1743 | |
1744 | if (s == NULL) |
1745 | return; /* not opened properly */ |
1746 | |
1747 | spin_lock_irq(lock: &chip->reg_lock); |
1748 | if (s->substream && s->running) |
1749 | snd_m3_pcm_stop(chip, s, subs: s->substream); /* does this happen? */ |
1750 | if (s->in_lists) { |
1751 | snd_m3_remove_list(chip, list: s->index_list[0], index: s->index[0]); |
1752 | snd_m3_remove_list(chip, list: s->index_list[1], index: s->index[1]); |
1753 | snd_m3_remove_list(chip, list: s->index_list[2], index: s->index[2]); |
1754 | s->in_lists = 0; |
1755 | } |
1756 | s->running = 0; |
1757 | s->opened = 0; |
1758 | spin_unlock_irq(lock: &chip->reg_lock); |
1759 | } |
1760 | |
1761 | static int |
1762 | snd_m3_playback_open(struct snd_pcm_substream *subs) |
1763 | { |
1764 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1765 | struct snd_pcm_runtime *runtime = subs->runtime; |
1766 | int err; |
1767 | |
1768 | err = snd_m3_substream_open(chip, subs); |
1769 | if (err < 0) |
1770 | return err; |
1771 | |
1772 | runtime->hw = snd_m3_playback; |
1773 | |
1774 | return 0; |
1775 | } |
1776 | |
1777 | static int |
1778 | snd_m3_playback_close(struct snd_pcm_substream *subs) |
1779 | { |
1780 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1781 | |
1782 | snd_m3_substream_close(chip, subs); |
1783 | return 0; |
1784 | } |
1785 | |
1786 | static int |
1787 | snd_m3_capture_open(struct snd_pcm_substream *subs) |
1788 | { |
1789 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1790 | struct snd_pcm_runtime *runtime = subs->runtime; |
1791 | int err; |
1792 | |
1793 | err = snd_m3_substream_open(chip, subs); |
1794 | if (err < 0) |
1795 | return err; |
1796 | |
1797 | runtime->hw = snd_m3_capture; |
1798 | |
1799 | return 0; |
1800 | } |
1801 | |
1802 | static int |
1803 | snd_m3_capture_close(struct snd_pcm_substream *subs) |
1804 | { |
1805 | struct snd_m3 *chip = snd_pcm_substream_chip(subs); |
1806 | |
1807 | snd_m3_substream_close(chip, subs); |
1808 | return 0; |
1809 | } |
1810 | |
1811 | /* |
1812 | * create pcm instance |
1813 | */ |
1814 | |
1815 | static const struct snd_pcm_ops snd_m3_playback_ops = { |
1816 | .open = snd_m3_playback_open, |
1817 | .close = snd_m3_playback_close, |
1818 | .hw_params = snd_m3_pcm_hw_params, |
1819 | .hw_free = snd_m3_pcm_hw_free, |
1820 | .prepare = snd_m3_pcm_prepare, |
1821 | .trigger = snd_m3_pcm_trigger, |
1822 | .pointer = snd_m3_pcm_pointer, |
1823 | }; |
1824 | |
1825 | static const struct snd_pcm_ops snd_m3_capture_ops = { |
1826 | .open = snd_m3_capture_open, |
1827 | .close = snd_m3_capture_close, |
1828 | .hw_params = snd_m3_pcm_hw_params, |
1829 | .hw_free = snd_m3_pcm_hw_free, |
1830 | .prepare = snd_m3_pcm_prepare, |
1831 | .trigger = snd_m3_pcm_trigger, |
1832 | .pointer = snd_m3_pcm_pointer, |
1833 | }; |
1834 | |
1835 | static int |
1836 | snd_m3_pcm(struct snd_m3 * chip, int device) |
1837 | { |
1838 | struct snd_pcm *pcm; |
1839 | int err; |
1840 | |
1841 | err = snd_pcm_new(card: chip->card, id: chip->card->driver, device, |
1842 | MAX_PLAYBACKS, MAX_CAPTURES, rpcm: &pcm); |
1843 | if (err < 0) |
1844 | return err; |
1845 | |
1846 | snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_m3_playback_ops); |
1847 | snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &snd_m3_capture_ops); |
1848 | |
1849 | pcm->private_data = chip; |
1850 | pcm->info_flags = 0; |
1851 | strcpy(p: pcm->name, q: chip->card->driver); |
1852 | chip->pcm = pcm; |
1853 | |
1854 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
1855 | data: &chip->pci->dev, size: 64*1024, max: 64*1024); |
1856 | |
1857 | return 0; |
1858 | } |
1859 | |
1860 | |
1861 | /* |
1862 | * ac97 interface |
1863 | */ |
1864 | |
1865 | /* |
1866 | * Wait for the ac97 serial bus to be free. |
1867 | * return nonzero if the bus is still busy. |
1868 | */ |
1869 | static int snd_m3_ac97_wait(struct snd_m3 *chip) |
1870 | { |
1871 | int i = 10000; |
1872 | |
1873 | do { |
1874 | if (! (snd_m3_inb(chip, reg: 0x30) & 1)) |
1875 | return 0; |
1876 | cpu_relax(); |
1877 | } while (i-- > 0); |
1878 | |
1879 | dev_err(chip->card->dev, "ac97 serial bus busy\n" ); |
1880 | return 1; |
1881 | } |
1882 | |
1883 | static unsigned short |
1884 | snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
1885 | { |
1886 | struct snd_m3 *chip = ac97->private_data; |
1887 | unsigned short data = 0xffff; |
1888 | |
1889 | if (snd_m3_ac97_wait(chip)) |
1890 | goto fail; |
1891 | snd_m3_outb(chip, value: 0x80 | (reg & 0x7f), CODEC_COMMAND); |
1892 | if (snd_m3_ac97_wait(chip)) |
1893 | goto fail; |
1894 | data = snd_m3_inw(chip, CODEC_DATA); |
1895 | fail: |
1896 | return data; |
1897 | } |
1898 | |
1899 | static void |
1900 | snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) |
1901 | { |
1902 | struct snd_m3 *chip = ac97->private_data; |
1903 | |
1904 | if (snd_m3_ac97_wait(chip)) |
1905 | return; |
1906 | snd_m3_outw(chip, value: val, CODEC_DATA); |
1907 | snd_m3_outb(chip, value: reg & 0x7f, CODEC_COMMAND); |
1908 | /* |
1909 | * Workaround for buggy ES1988 integrated AC'97 codec. It remains silent |
1910 | * until the MASTER volume or mute is touched (alsactl restore does not |
1911 | * work). |
1912 | */ |
1913 | if (ac97->id == 0x45838308 && reg == AC97_MASTER) { |
1914 | snd_m3_ac97_wait(chip); |
1915 | snd_m3_outw(chip, value: val, CODEC_DATA); |
1916 | snd_m3_outb(chip, value: reg & 0x7f, CODEC_COMMAND); |
1917 | } |
1918 | } |
1919 | |
1920 | |
1921 | static void snd_m3_remote_codec_config(struct snd_m3 *chip, int isremote) |
1922 | { |
1923 | int io = chip->iobase; |
1924 | u16 tmp; |
1925 | |
1926 | isremote = isremote ? 1 : 0; |
1927 | |
1928 | tmp = inw(port: io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK; |
1929 | /* enable dock on Dell Latitude C810 */ |
1930 | if (chip->pci->subsystem_vendor == 0x1028 && |
1931 | chip->pci->subsystem_device == 0x00e5) |
1932 | tmp |= M3I_DOCK_ENABLE; |
1933 | outw(value: tmp | isremote, port: io + RING_BUS_CTRL_B); |
1934 | outw(value: (inw(port: io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote, |
1935 | port: io + SDO_OUT_DEST_CTRL); |
1936 | outw(value: (inw(port: io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote, |
1937 | port: io + SDO_IN_DEST_CTRL); |
1938 | } |
1939 | |
1940 | /* |
1941 | * hack, returns non zero on err |
1942 | */ |
1943 | static int snd_m3_try_read_vendor(struct snd_m3 *chip) |
1944 | { |
1945 | u16 ret; |
1946 | |
1947 | if (snd_m3_ac97_wait(chip)) |
1948 | return 1; |
1949 | |
1950 | snd_m3_outb(chip, value: 0x80 | (AC97_VENDOR_ID1 & 0x7f), reg: 0x30); |
1951 | |
1952 | if (snd_m3_ac97_wait(chip)) |
1953 | return 1; |
1954 | |
1955 | ret = snd_m3_inw(chip, reg: 0x32); |
1956 | |
1957 | return (ret == 0) || (ret == 0xffff); |
1958 | } |
1959 | |
1960 | static void snd_m3_ac97_reset(struct snd_m3 *chip) |
1961 | { |
1962 | u16 dir; |
1963 | int delay1 = 0, delay2 = 0, i; |
1964 | int io = chip->iobase; |
1965 | |
1966 | if (chip->allegro_flag) { |
1967 | /* |
1968 | * the onboard codec on the allegro seems |
1969 | * to want to wait a very long time before |
1970 | * coming back to life |
1971 | */ |
1972 | delay1 = 50; |
1973 | delay2 = 800; |
1974 | } else { |
1975 | /* maestro3 */ |
1976 | delay1 = 20; |
1977 | delay2 = 500; |
1978 | } |
1979 | |
1980 | for (i = 0; i < 5; i++) { |
1981 | dir = inw(port: io + GPIO_DIRECTION); |
1982 | if (!chip->irda_workaround) |
1983 | dir |= 0x10; /* assuming pci bus master? */ |
1984 | |
1985 | snd_m3_remote_codec_config(chip, isremote: 0); |
1986 | |
1987 | outw(IO_SRAM_ENABLE, port: io + RING_BUS_CTRL_A); |
1988 | udelay(20); |
1989 | |
1990 | outw(value: dir & ~GPO_PRIMARY_AC97 , port: io + GPIO_DIRECTION); |
1991 | outw(value: ~GPO_PRIMARY_AC97 , port: io + GPIO_MASK); |
1992 | outw(value: 0, port: io + GPIO_DATA); |
1993 | outw(value: dir | GPO_PRIMARY_AC97, port: io + GPIO_DIRECTION); |
1994 | |
1995 | schedule_timeout_uninterruptible(timeout: msecs_to_jiffies(m: delay1)); |
1996 | |
1997 | outw(GPO_PRIMARY_AC97, port: io + GPIO_DATA); |
1998 | udelay(5); |
1999 | /* ok, bring back the ac-link */ |
2000 | outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, port: io + RING_BUS_CTRL_A); |
2001 | outw(value: ~0, port: io + GPIO_MASK); |
2002 | |
2003 | schedule_timeout_uninterruptible(timeout: msecs_to_jiffies(m: delay2)); |
2004 | |
2005 | if (! snd_m3_try_read_vendor(chip)) |
2006 | break; |
2007 | |
2008 | delay1 += 10; |
2009 | delay2 += 100; |
2010 | |
2011 | dev_dbg(chip->card->dev, |
2012 | "retrying codec reset with delays of %d and %d ms\n" , |
2013 | delay1, delay2); |
2014 | } |
2015 | |
2016 | #if 0 |
2017 | /* more gung-ho reset that doesn't |
2018 | * seem to work anywhere :) |
2019 | */ |
2020 | tmp = inw(io + RING_BUS_CTRL_A); |
2021 | outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A); |
2022 | msleep(20); |
2023 | outw(tmp, io + RING_BUS_CTRL_A); |
2024 | msleep(50); |
2025 | #endif |
2026 | } |
2027 | |
2028 | static int snd_m3_mixer(struct snd_m3 *chip) |
2029 | { |
2030 | struct snd_ac97_bus *pbus; |
2031 | struct snd_ac97_template ac97; |
2032 | int err; |
2033 | static const struct snd_ac97_bus_ops ops = { |
2034 | .write = snd_m3_ac97_write, |
2035 | .read = snd_m3_ac97_read, |
2036 | }; |
2037 | |
2038 | err = snd_ac97_bus(card: chip->card, num: 0, ops: &ops, NULL, rbus: &pbus); |
2039 | if (err < 0) |
2040 | return err; |
2041 | |
2042 | memset(&ac97, 0, sizeof(ac97)); |
2043 | ac97.private_data = chip; |
2044 | err = snd_ac97_mixer(bus: pbus, template: &ac97, rac97: &chip->ac97); |
2045 | if (err < 0) |
2046 | return err; |
2047 | |
2048 | /* seems ac97 PCM needs initialization.. hack hack.. */ |
2049 | snd_ac97_write(ac97: chip->ac97, AC97_PCM, value: 0x8000 | (15 << 8) | 15); |
2050 | schedule_timeout_uninterruptible(timeout: msecs_to_jiffies(m: 100)); |
2051 | snd_ac97_write(ac97: chip->ac97, AC97_PCM, value: 0); |
2052 | |
2053 | #ifndef CONFIG_SND_MAESTRO3_INPUT |
2054 | chip->master_switch = snd_ctl_find_id_mixer(chip->card, |
2055 | "Master Playback Switch" ); |
2056 | chip->master_volume = snd_ctl_find_id_mixer(chip->card, |
2057 | "Master Playback Volume" ); |
2058 | #endif |
2059 | |
2060 | return 0; |
2061 | } |
2062 | |
2063 | |
2064 | /* |
2065 | * initialize ASSP |
2066 | */ |
2067 | |
2068 | #define MINISRC_LPF_LEN 10 |
2069 | static const u16 minisrc_lpf[MINISRC_LPF_LEN] = { |
2070 | 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, |
2071 | 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F |
2072 | }; |
2073 | |
2074 | static void snd_m3_assp_init(struct snd_m3 *chip) |
2075 | { |
2076 | unsigned int i; |
2077 | const __le16 *data; |
2078 | |
2079 | /* zero kernel data */ |
2080 | for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) |
2081 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2082 | KDATA_BASE_ADDR + i, data: 0); |
2083 | |
2084 | /* zero mixer data? */ |
2085 | for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) |
2086 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2087 | KDATA_BASE_ADDR2 + i, data: 0); |
2088 | |
2089 | /* init dma pointer */ |
2090 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2091 | KDATA_CURRENT_DMA, |
2092 | KDATA_DMA_XFER0); |
2093 | |
2094 | /* write kernel into code memory.. */ |
2095 | data = (const __le16 *)chip->assp_kernel_image->data; |
2096 | for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) { |
2097 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
2098 | REV_B_CODE_MEMORY_BEGIN + i, |
2099 | le16_to_cpu(data[i])); |
2100 | } |
2101 | |
2102 | /* |
2103 | * We only have this one client and we know that 0x400 |
2104 | * is free in our kernel's mem map, so lets just |
2105 | * drop it there. It seems that the minisrc doesn't |
2106 | * need vectors, so we won't bother with them.. |
2107 | */ |
2108 | data = (const __le16 *)chip->assp_minisrc_image->data; |
2109 | for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) { |
2110 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
2111 | index: 0x400 + i, le16_to_cpu(data[i])); |
2112 | } |
2113 | |
2114 | /* |
2115 | * write the coefficients for the low pass filter? |
2116 | */ |
2117 | for (i = 0; i < MINISRC_LPF_LEN ; i++) { |
2118 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
2119 | index: 0x400 + MINISRC_COEF_LOC + i, |
2120 | data: minisrc_lpf[i]); |
2121 | } |
2122 | |
2123 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, |
2124 | index: 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, |
2125 | data: 0x8000); |
2126 | |
2127 | /* |
2128 | * the minisrc is the only thing on |
2129 | * our task list.. |
2130 | */ |
2131 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2132 | KDATA_TASK0, |
2133 | data: 0x400); |
2134 | |
2135 | /* |
2136 | * init the mixer number.. |
2137 | */ |
2138 | |
2139 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2140 | KDATA_MIXER_TASK_NUMBER,data: 0); |
2141 | |
2142 | /* |
2143 | * EXTREME KERNEL MASTER VOLUME |
2144 | */ |
2145 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2146 | KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); |
2147 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2148 | KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); |
2149 | |
2150 | chip->mixer_list.curlen = 0; |
2151 | chip->mixer_list.mem_addr = KDATA_MIXER_XFER0; |
2152 | chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS; |
2153 | chip->adc1_list.curlen = 0; |
2154 | chip->adc1_list.mem_addr = KDATA_ADC1_XFER0; |
2155 | chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS; |
2156 | chip->dma_list.curlen = 0; |
2157 | chip->dma_list.mem_addr = KDATA_DMA_XFER0; |
2158 | chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS; |
2159 | chip->msrc_list.curlen = 0; |
2160 | chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC; |
2161 | chip->msrc_list.max = MAX_INSTANCE_MINISRC; |
2162 | } |
2163 | |
2164 | |
2165 | static int snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index) |
2166 | { |
2167 | int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + |
2168 | MINISRC_IN_BUFFER_SIZE / 2 + |
2169 | 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 ); |
2170 | int address, i; |
2171 | |
2172 | /* |
2173 | * the revb memory map has 0x1100 through 0x1c00 |
2174 | * free. |
2175 | */ |
2176 | |
2177 | /* |
2178 | * align instance address to 256 bytes so that its |
2179 | * shifted list address is aligned. |
2180 | * list address = (mem address >> 1) >> 7; |
2181 | */ |
2182 | data_bytes = ALIGN(data_bytes, 256); |
2183 | address = 0x1100 + ((data_bytes/2) * index); |
2184 | |
2185 | if ((address + (data_bytes/2)) >= 0x1c00) { |
2186 | dev_err(chip->card->dev, |
2187 | "no memory for %d bytes at ind %d (addr 0x%x)\n" , |
2188 | data_bytes, index, address); |
2189 | return -ENOMEM; |
2190 | } |
2191 | |
2192 | s->number = index; |
2193 | s->inst.code = 0x400; |
2194 | s->inst.data = address; |
2195 | |
2196 | for (i = data_bytes / 2; i > 0; address++, i--) { |
2197 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2198 | index: address, data: 0); |
2199 | } |
2200 | |
2201 | return 0; |
2202 | } |
2203 | |
2204 | |
2205 | /* |
2206 | * this works for the reference board, have to find |
2207 | * out about others |
2208 | * |
2209 | * this needs more magic for 4 speaker, but.. |
2210 | */ |
2211 | static void |
2212 | snd_m3_amp_enable(struct snd_m3 *chip, int enable) |
2213 | { |
2214 | int io = chip->iobase; |
2215 | u16 gpo, polarity; |
2216 | |
2217 | if (! chip->external_amp) |
2218 | return; |
2219 | |
2220 | polarity = enable ? 0 : 1; |
2221 | polarity = polarity << chip->amp_gpio; |
2222 | gpo = 1 << chip->amp_gpio; |
2223 | |
2224 | outw(value: ~gpo, port: io + GPIO_MASK); |
2225 | |
2226 | outw(inw(port: io + GPIO_DIRECTION) | gpo, |
2227 | port: io + GPIO_DIRECTION); |
2228 | |
2229 | outw(value: (GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity), |
2230 | port: io + GPIO_DATA); |
2231 | |
2232 | outw(value: 0xffff, port: io + GPIO_MASK); |
2233 | } |
2234 | |
2235 | static void |
2236 | snd_m3_hv_init(struct snd_m3 *chip) |
2237 | { |
2238 | unsigned long io = chip->iobase; |
2239 | u16 val = GPI_VOL_DOWN | GPI_VOL_UP; |
2240 | |
2241 | if (!chip->is_omnibook) |
2242 | return; |
2243 | |
2244 | /* |
2245 | * Volume buttons on some HP OmniBook laptops |
2246 | * require some GPIO magic to work correctly. |
2247 | */ |
2248 | outw(value: 0xffff, port: io + GPIO_MASK); |
2249 | outw(value: 0x0000, port: io + GPIO_DATA); |
2250 | |
2251 | outw(value: ~val, port: io + GPIO_MASK); |
2252 | outw(inw(port: io + GPIO_DIRECTION) & ~val, port: io + GPIO_DIRECTION); |
2253 | outw(value: val, port: io + GPIO_MASK); |
2254 | |
2255 | outw(value: 0xffff, port: io + GPIO_MASK); |
2256 | } |
2257 | |
2258 | static int |
2259 | snd_m3_chip_init(struct snd_m3 *chip) |
2260 | { |
2261 | struct pci_dev *pcidev = chip->pci; |
2262 | unsigned long io = chip->iobase; |
2263 | u32 n; |
2264 | u16 w; |
2265 | u8 t; /* makes as much sense as 'n', no? */ |
2266 | |
2267 | pci_read_config_word(dev: pcidev, PCI_LEGACY_AUDIO_CTRL, val: &w); |
2268 | w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE| |
2269 | MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO| |
2270 | DISABLE_LEGACY); |
2271 | pci_write_config_word(dev: pcidev, PCI_LEGACY_AUDIO_CTRL, val: w); |
2272 | |
2273 | pci_read_config_dword(dev: pcidev, PCI_ALLEGRO_CONFIG, val: &n); |
2274 | n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD); |
2275 | n |= chip->hv_config; |
2276 | /* For some reason we must always use reduced debounce. */ |
2277 | n |= REDUCED_DEBOUNCE; |
2278 | n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; |
2279 | pci_write_config_dword(dev: pcidev, PCI_ALLEGRO_CONFIG, val: n); |
2280 | |
2281 | outb(RESET_ASSP, port: chip->iobase + ASSP_CONTROL_B); |
2282 | pci_read_config_dword(dev: pcidev, PCI_ALLEGRO_CONFIG, val: &n); |
2283 | n &= ~INT_CLK_SELECT; |
2284 | if (!chip->allegro_flag) { |
2285 | n &= ~INT_CLK_MULT_ENABLE; |
2286 | n |= INT_CLK_SRC_NOT_PCI; |
2287 | } |
2288 | n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 ); |
2289 | pci_write_config_dword(dev: pcidev, PCI_ALLEGRO_CONFIG, val: n); |
2290 | |
2291 | if (chip->allegro_flag) { |
2292 | pci_read_config_dword(dev: pcidev, PCI_USER_CONFIG, val: &n); |
2293 | n |= IN_CLK_12MHZ_SELECT; |
2294 | pci_write_config_dword(dev: pcidev, PCI_USER_CONFIG, val: n); |
2295 | } |
2296 | |
2297 | t = inb(port: chip->iobase + ASSP_CONTROL_A); |
2298 | t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); |
2299 | t |= ASSP_CLK_49MHZ_SELECT; |
2300 | t |= ASSP_0_WS_ENABLE; |
2301 | outb(value: t, port: chip->iobase + ASSP_CONTROL_A); |
2302 | |
2303 | snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */ |
2304 | outb(RUN_ASSP, port: chip->iobase + ASSP_CONTROL_B); |
2305 | |
2306 | outb(value: 0x00, port: io + HARDWARE_VOL_CTRL); |
2307 | outb(value: 0x88, port: io + SHADOW_MIX_REG_VOICE); |
2308 | outb(value: 0x88, port: io + HW_VOL_COUNTER_VOICE); |
2309 | outb(value: 0x88, port: io + SHADOW_MIX_REG_MASTER); |
2310 | outb(value: 0x88, port: io + HW_VOL_COUNTER_MASTER); |
2311 | |
2312 | return 0; |
2313 | } |
2314 | |
2315 | static void |
2316 | snd_m3_enable_ints(struct snd_m3 *chip) |
2317 | { |
2318 | unsigned long io = chip->iobase; |
2319 | unsigned short val; |
2320 | |
2321 | /* TODO: MPU401 not supported yet */ |
2322 | val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/; |
2323 | if (chip->hv_config & HV_CTRL_ENABLE) |
2324 | val |= HV_INT_ENABLE; |
2325 | outb(value: val, port: chip->iobase + HOST_INT_STATUS); |
2326 | outw(value: val, port: io + HOST_INT_CTRL); |
2327 | outb(inb(port: io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, |
2328 | port: io + ASSP_CONTROL_C); |
2329 | } |
2330 | |
2331 | |
2332 | /* |
2333 | */ |
2334 | |
2335 | static void snd_m3_free(struct snd_card *card) |
2336 | { |
2337 | struct snd_m3 *chip = card->private_data; |
2338 | struct m3_dma *s; |
2339 | int i; |
2340 | |
2341 | cancel_work_sync(work: &chip->hwvol_work); |
2342 | |
2343 | if (chip->substreams) { |
2344 | spin_lock_irq(lock: &chip->reg_lock); |
2345 | for (i = 0; i < chip->num_substreams; i++) { |
2346 | s = &chip->substreams[i]; |
2347 | /* check surviving pcms; this should not happen though.. */ |
2348 | if (s->substream && s->running) |
2349 | snd_m3_pcm_stop(chip, s, subs: s->substream); |
2350 | } |
2351 | spin_unlock_irq(lock: &chip->reg_lock); |
2352 | } |
2353 | if (chip->iobase) { |
2354 | outw(value: 0, port: chip->iobase + HOST_INT_CTRL); /* disable ints */ |
2355 | } |
2356 | |
2357 | #ifdef CONFIG_PM_SLEEP |
2358 | vfree(addr: chip->suspend_mem); |
2359 | #endif |
2360 | release_firmware(fw: chip->assp_kernel_image); |
2361 | release_firmware(fw: chip->assp_minisrc_image); |
2362 | } |
2363 | |
2364 | |
2365 | /* |
2366 | * APM support |
2367 | */ |
2368 | #ifdef CONFIG_PM_SLEEP |
2369 | static int m3_suspend(struct device *dev) |
2370 | { |
2371 | struct snd_card *card = dev_get_drvdata(dev); |
2372 | struct snd_m3 *chip = card->private_data; |
2373 | int i, dsp_index; |
2374 | |
2375 | if (chip->suspend_mem == NULL) |
2376 | return 0; |
2377 | |
2378 | chip->in_suspend = 1; |
2379 | cancel_work_sync(work: &chip->hwvol_work); |
2380 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
2381 | snd_ac97_suspend(ac97: chip->ac97); |
2382 | |
2383 | msleep(msecs: 10); /* give the assp a chance to idle.. */ |
2384 | |
2385 | snd_m3_assp_halt(chip); |
2386 | |
2387 | /* save dsp image */ |
2388 | dsp_index = 0; |
2389 | for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) |
2390 | chip->suspend_mem[dsp_index++] = |
2391 | snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, index: i); |
2392 | for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) |
2393 | chip->suspend_mem[dsp_index++] = |
2394 | snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, index: i); |
2395 | return 0; |
2396 | } |
2397 | |
2398 | static int m3_resume(struct device *dev) |
2399 | { |
2400 | struct snd_card *card = dev_get_drvdata(dev); |
2401 | struct snd_m3 *chip = card->private_data; |
2402 | int i, dsp_index; |
2403 | |
2404 | if (chip->suspend_mem == NULL) |
2405 | return 0; |
2406 | |
2407 | /* first lets just bring everything back. .*/ |
2408 | snd_m3_outw(chip, value: 0, reg: 0x54); |
2409 | snd_m3_outw(chip, value: 0, reg: 0x56); |
2410 | |
2411 | snd_m3_chip_init(chip); |
2412 | snd_m3_assp_halt(chip); |
2413 | snd_m3_ac97_reset(chip); |
2414 | |
2415 | /* restore dsp image */ |
2416 | dsp_index = 0; |
2417 | for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) |
2418 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, index: i, |
2419 | data: chip->suspend_mem[dsp_index++]); |
2420 | for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) |
2421 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, index: i, |
2422 | data: chip->suspend_mem[dsp_index++]); |
2423 | |
2424 | /* tell the dma engine to restart itself */ |
2425 | snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, |
2426 | KDATA_DMA_ACTIVE, data: 0); |
2427 | |
2428 | /* restore ac97 registers */ |
2429 | snd_ac97_resume(ac97: chip->ac97); |
2430 | |
2431 | snd_m3_assp_continue(chip); |
2432 | snd_m3_enable_ints(chip); |
2433 | snd_m3_amp_enable(chip, enable: 1); |
2434 | |
2435 | snd_m3_hv_init(chip); |
2436 | |
2437 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
2438 | chip->in_suspend = 0; |
2439 | return 0; |
2440 | } |
2441 | |
2442 | static SIMPLE_DEV_PM_OPS(m3_pm, m3_suspend, m3_resume); |
2443 | #define M3_PM_OPS &m3_pm |
2444 | #else |
2445 | #define M3_PM_OPS NULL |
2446 | #endif /* CONFIG_PM_SLEEP */ |
2447 | |
2448 | #ifdef CONFIG_SND_MAESTRO3_INPUT |
2449 | static int snd_m3_input_register(struct snd_m3 *chip) |
2450 | { |
2451 | struct input_dev *input_dev; |
2452 | int err; |
2453 | |
2454 | input_dev = devm_input_allocate_device(&chip->pci->dev); |
2455 | if (!input_dev) |
2456 | return -ENOMEM; |
2457 | |
2458 | snprintf(buf: chip->phys, size: sizeof(chip->phys), fmt: "pci-%s/input0" , |
2459 | pci_name(pdev: chip->pci)); |
2460 | |
2461 | input_dev->name = chip->card->driver; |
2462 | input_dev->phys = chip->phys; |
2463 | input_dev->id.bustype = BUS_PCI; |
2464 | input_dev->id.vendor = chip->pci->vendor; |
2465 | input_dev->id.product = chip->pci->device; |
2466 | input_dev->dev.parent = &chip->pci->dev; |
2467 | |
2468 | __set_bit(EV_KEY, input_dev->evbit); |
2469 | __set_bit(KEY_MUTE, input_dev->keybit); |
2470 | __set_bit(KEY_VOLUMEDOWN, input_dev->keybit); |
2471 | __set_bit(KEY_VOLUMEUP, input_dev->keybit); |
2472 | |
2473 | err = input_register_device(input_dev); |
2474 | if (err) |
2475 | return err; |
2476 | |
2477 | chip->input_dev = input_dev; |
2478 | return 0; |
2479 | } |
2480 | #endif /* CONFIG_INPUT */ |
2481 | |
2482 | /* |
2483 | */ |
2484 | |
2485 | static int |
2486 | snd_m3_create(struct snd_card *card, struct pci_dev *pci, |
2487 | int enable_amp, |
2488 | int amp_gpio) |
2489 | { |
2490 | struct snd_m3 *chip = card->private_data; |
2491 | int i, err; |
2492 | const struct snd_pci_quirk *quirk; |
2493 | |
2494 | if (pcim_enable_device(pdev: pci)) |
2495 | return -EIO; |
2496 | |
2497 | /* check, if we can restrict PCI DMA transfers to 28 bits */ |
2498 | if (dma_set_mask_and_coherent(dev: &pci->dev, DMA_BIT_MASK(28))) { |
2499 | dev_err(card->dev, |
2500 | "architecture does not support 28bit PCI busmaster DMA\n" ); |
2501 | return -ENXIO; |
2502 | } |
2503 | |
2504 | spin_lock_init(&chip->reg_lock); |
2505 | |
2506 | switch (pci->device) { |
2507 | case PCI_DEVICE_ID_ESS_ALLEGRO: |
2508 | case PCI_DEVICE_ID_ESS_ALLEGRO_1: |
2509 | case PCI_DEVICE_ID_ESS_CANYON3D_2LE: |
2510 | case PCI_DEVICE_ID_ESS_CANYON3D_2: |
2511 | chip->allegro_flag = 1; |
2512 | break; |
2513 | } |
2514 | |
2515 | chip->card = card; |
2516 | chip->pci = pci; |
2517 | chip->irq = -1; |
2518 | INIT_WORK(&chip->hwvol_work, snd_m3_update_hw_volume); |
2519 | card->private_free = snd_m3_free; |
2520 | |
2521 | chip->external_amp = enable_amp; |
2522 | if (amp_gpio >= 0 && amp_gpio <= 0x0f) |
2523 | chip->amp_gpio = amp_gpio; |
2524 | else { |
2525 | quirk = snd_pci_quirk_lookup(pci, list: m3_amp_quirk_list); |
2526 | if (quirk) { |
2527 | dev_info(card->dev, "set amp-gpio for '%s'\n" , |
2528 | snd_pci_quirk_name(quirk)); |
2529 | chip->amp_gpio = quirk->value; |
2530 | } else if (chip->allegro_flag) |
2531 | chip->amp_gpio = GPO_EXT_AMP_ALLEGRO; |
2532 | else /* presumably this is for all 'maestro3's.. */ |
2533 | chip->amp_gpio = GPO_EXT_AMP_M3; |
2534 | } |
2535 | |
2536 | quirk = snd_pci_quirk_lookup(pci, list: m3_irda_quirk_list); |
2537 | if (quirk) { |
2538 | dev_info(card->dev, "enabled irda workaround for '%s'\n" , |
2539 | snd_pci_quirk_name(quirk)); |
2540 | chip->irda_workaround = 1; |
2541 | } |
2542 | quirk = snd_pci_quirk_lookup(pci, list: m3_hv_quirk_list); |
2543 | if (quirk) |
2544 | chip->hv_config = quirk->value; |
2545 | if (snd_pci_quirk_lookup(pci, list: m3_omnibook_quirk_list)) |
2546 | chip->is_omnibook = 1; |
2547 | |
2548 | chip->num_substreams = NR_DSPS; |
2549 | chip->substreams = devm_kcalloc(dev: &pci->dev, n: chip->num_substreams, |
2550 | size: sizeof(struct m3_dma), GFP_KERNEL); |
2551 | if (!chip->substreams) |
2552 | return -ENOMEM; |
2553 | |
2554 | err = request_firmware(fw: &chip->assp_kernel_image, |
2555 | name: "ess/maestro3_assp_kernel.fw" , device: &pci->dev); |
2556 | if (err < 0) |
2557 | return err; |
2558 | |
2559 | err = request_firmware(fw: &chip->assp_minisrc_image, |
2560 | name: "ess/maestro3_assp_minisrc.fw" , device: &pci->dev); |
2561 | if (err < 0) |
2562 | return err; |
2563 | |
2564 | err = pci_request_regions(pci, card->driver); |
2565 | if (err < 0) |
2566 | return err; |
2567 | |
2568 | chip->iobase = pci_resource_start(pci, 0); |
2569 | |
2570 | /* just to be sure */ |
2571 | pci_set_master(dev: pci); |
2572 | |
2573 | snd_m3_chip_init(chip); |
2574 | snd_m3_assp_halt(chip); |
2575 | |
2576 | snd_m3_ac97_reset(chip); |
2577 | |
2578 | snd_m3_amp_enable(chip, enable: 1); |
2579 | |
2580 | snd_m3_hv_init(chip); |
2581 | |
2582 | if (devm_request_irq(dev: &pci->dev, irq: pci->irq, handler: snd_m3_interrupt, IRQF_SHARED, |
2583 | KBUILD_MODNAME, dev_id: chip)) { |
2584 | dev_err(card->dev, "unable to grab IRQ %d\n" , pci->irq); |
2585 | return -ENOMEM; |
2586 | } |
2587 | chip->irq = pci->irq; |
2588 | card->sync_irq = chip->irq; |
2589 | |
2590 | #ifdef CONFIG_PM_SLEEP |
2591 | chip->suspend_mem = |
2592 | vmalloc(array_size(sizeof(u16), |
2593 | REV_B_CODE_MEMORY_LENGTH + |
2594 | REV_B_DATA_MEMORY_LENGTH)); |
2595 | if (chip->suspend_mem == NULL) |
2596 | dev_warn(card->dev, "can't allocate apm buffer\n" ); |
2597 | #endif |
2598 | |
2599 | err = snd_m3_mixer(chip); |
2600 | if (err < 0) |
2601 | return err; |
2602 | |
2603 | for (i = 0; i < chip->num_substreams; i++) { |
2604 | struct m3_dma *s = &chip->substreams[i]; |
2605 | err = snd_m3_assp_client_init(chip, s, index: i); |
2606 | if (err < 0) |
2607 | return err; |
2608 | } |
2609 | |
2610 | err = snd_m3_pcm(chip, device: 0); |
2611 | if (err < 0) |
2612 | return err; |
2613 | |
2614 | #ifdef CONFIG_SND_MAESTRO3_INPUT |
2615 | if (chip->hv_config & HV_CTRL_ENABLE) { |
2616 | err = snd_m3_input_register(chip); |
2617 | if (err) |
2618 | dev_warn(card->dev, |
2619 | "Input device registration failed with error %i" , |
2620 | err); |
2621 | } |
2622 | #endif |
2623 | |
2624 | snd_m3_enable_ints(chip); |
2625 | snd_m3_assp_continue(chip); |
2626 | |
2627 | return 0; |
2628 | } |
2629 | |
2630 | /* |
2631 | */ |
2632 | static int |
2633 | __snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) |
2634 | { |
2635 | static int dev; |
2636 | struct snd_card *card; |
2637 | struct snd_m3 *chip; |
2638 | int err; |
2639 | |
2640 | /* don't pick up modems */ |
2641 | if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) |
2642 | return -ENODEV; |
2643 | |
2644 | if (dev >= SNDRV_CARDS) |
2645 | return -ENODEV; |
2646 | if (!enable[dev]) { |
2647 | dev++; |
2648 | return -ENOENT; |
2649 | } |
2650 | |
2651 | err = snd_devm_card_new(parent: &pci->dev, idx: index[dev], xid: id[dev], THIS_MODULE, |
2652 | extra_size: sizeof(*chip), card_ret: &card); |
2653 | if (err < 0) |
2654 | return err; |
2655 | chip = card->private_data; |
2656 | |
2657 | switch (pci->device) { |
2658 | case PCI_DEVICE_ID_ESS_ALLEGRO: |
2659 | case PCI_DEVICE_ID_ESS_ALLEGRO_1: |
2660 | strcpy(p: card->driver, q: "Allegro" ); |
2661 | break; |
2662 | case PCI_DEVICE_ID_ESS_CANYON3D_2LE: |
2663 | case PCI_DEVICE_ID_ESS_CANYON3D_2: |
2664 | strcpy(p: card->driver, q: "Canyon3D-2" ); |
2665 | break; |
2666 | default: |
2667 | strcpy(p: card->driver, q: "Maestro3" ); |
2668 | break; |
2669 | } |
2670 | |
2671 | err = snd_m3_create(card, pci, enable_amp: external_amp[dev], amp_gpio: amp_gpio[dev]); |
2672 | if (err < 0) |
2673 | return err; |
2674 | |
2675 | sprintf(buf: card->shortname, fmt: "ESS %s PCI" , card->driver); |
2676 | sprintf(buf: card->longname, fmt: "%s at 0x%lx, irq %d" , |
2677 | card->shortname, chip->iobase, chip->irq); |
2678 | |
2679 | err = snd_card_register(card); |
2680 | if (err < 0) |
2681 | return err; |
2682 | |
2683 | #if 0 /* TODO: not supported yet */ |
2684 | /* TODO enable MIDI IRQ and I/O */ |
2685 | err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401, |
2686 | chip->iobase + MPU401_DATA_PORT, |
2687 | MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, |
2688 | -1, &chip->rmidi); |
2689 | if (err < 0) |
2690 | dev_warn(card->dev, "no MIDI support.\n" ); |
2691 | #endif |
2692 | |
2693 | pci_set_drvdata(pdev: pci, data: card); |
2694 | dev++; |
2695 | return 0; |
2696 | } |
2697 | |
2698 | static int |
2699 | snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) |
2700 | { |
2701 | return snd_card_free_on_error(dev: &pci->dev, ret: __snd_m3_probe(pci, pci_id)); |
2702 | } |
2703 | |
2704 | static struct pci_driver m3_driver = { |
2705 | .name = KBUILD_MODNAME, |
2706 | .id_table = snd_m3_ids, |
2707 | .probe = snd_m3_probe, |
2708 | .driver = { |
2709 | .pm = M3_PM_OPS, |
2710 | }, |
2711 | }; |
2712 | |
2713 | module_pci_driver(m3_driver); |
2714 | |