1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio |
4 | * interfaces |
5 | * |
6 | * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> |
7 | * |
8 | * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control |
9 | * code. |
10 | */ |
11 | |
12 | #include <linux/delay.h> |
13 | #include <linux/init.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/pci.h> |
16 | #include <linux/module.h> |
17 | #include <linux/vmalloc.h> |
18 | #include <linux/io.h> |
19 | |
20 | #include <sound/core.h> |
21 | #include <sound/info.h> |
22 | #include <sound/control.h> |
23 | #include <sound/pcm.h> |
24 | #include <sound/pcm_params.h> |
25 | #include <sound/asoundef.h> |
26 | #include <sound/initval.h> |
27 | |
28 | /* note, two last pcis should be equal, it is not a bug */ |
29 | |
30 | MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>" ); |
31 | MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " |
32 | "Digi96/8 PAD" ); |
33 | MODULE_LICENSE("GPL" ); |
34 | |
35 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
36 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
37 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ |
38 | |
39 | module_param_array(index, int, NULL, 0444); |
40 | MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard." ); |
41 | module_param_array(id, charp, NULL, 0444); |
42 | MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard." ); |
43 | module_param_array(enable, bool, NULL, 0444); |
44 | MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard." ); |
45 | |
46 | /* |
47 | * Defines for RME Digi96 series, from internal RME reference documents |
48 | * dated 12.01.00 |
49 | */ |
50 | |
51 | #define RME96_SPDIF_NCHANNELS 2 |
52 | |
53 | /* Playback and capture buffer size */ |
54 | #define RME96_BUFFER_SIZE 0x10000 |
55 | |
56 | /* IO area size */ |
57 | #define RME96_IO_SIZE 0x60000 |
58 | |
59 | /* IO area offsets */ |
60 | #define RME96_IO_PLAY_BUFFER 0x0 |
61 | #define RME96_IO_REC_BUFFER 0x10000 |
62 | #define RME96_IO_CONTROL_REGISTER 0x20000 |
63 | #define RME96_IO_ADDITIONAL_REG 0x20004 |
64 | #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 |
65 | #define RME96_IO_CONFIRM_REC_IRQ 0x2000C |
66 | #define RME96_IO_SET_PLAY_POS 0x40000 |
67 | #define RME96_IO_RESET_PLAY_POS 0x4FFFC |
68 | #define RME96_IO_SET_REC_POS 0x50000 |
69 | #define RME96_IO_RESET_REC_POS 0x5FFFC |
70 | #define RME96_IO_GET_PLAY_POS 0x20000 |
71 | #define RME96_IO_GET_REC_POS 0x30000 |
72 | |
73 | /* Write control register bits */ |
74 | #define RME96_WCR_START (1 << 0) |
75 | #define RME96_WCR_START_2 (1 << 1) |
76 | #define RME96_WCR_GAIN_0 (1 << 2) |
77 | #define RME96_WCR_GAIN_1 (1 << 3) |
78 | #define RME96_WCR_MODE24 (1 << 4) |
79 | #define RME96_WCR_MODE24_2 (1 << 5) |
80 | #define RME96_WCR_BM (1 << 6) |
81 | #define RME96_WCR_BM_2 (1 << 7) |
82 | #define RME96_WCR_ADAT (1 << 8) |
83 | #define RME96_WCR_FREQ_0 (1 << 9) |
84 | #define RME96_WCR_FREQ_1 (1 << 10) |
85 | #define RME96_WCR_DS (1 << 11) |
86 | #define RME96_WCR_PRO (1 << 12) |
87 | #define RME96_WCR_EMP (1 << 13) |
88 | #define RME96_WCR_SEL (1 << 14) |
89 | #define RME96_WCR_MASTER (1 << 15) |
90 | #define RME96_WCR_PD (1 << 16) |
91 | #define RME96_WCR_INP_0 (1 << 17) |
92 | #define RME96_WCR_INP_1 (1 << 18) |
93 | #define RME96_WCR_THRU_0 (1 << 19) |
94 | #define RME96_WCR_THRU_1 (1 << 20) |
95 | #define RME96_WCR_THRU_2 (1 << 21) |
96 | #define RME96_WCR_THRU_3 (1 << 22) |
97 | #define RME96_WCR_THRU_4 (1 << 23) |
98 | #define RME96_WCR_THRU_5 (1 << 24) |
99 | #define RME96_WCR_THRU_6 (1 << 25) |
100 | #define RME96_WCR_THRU_7 (1 << 26) |
101 | #define RME96_WCR_DOLBY (1 << 27) |
102 | #define RME96_WCR_MONITOR_0 (1 << 28) |
103 | #define RME96_WCR_MONITOR_1 (1 << 29) |
104 | #define RME96_WCR_ISEL (1 << 30) |
105 | #define RME96_WCR_IDIS (1 << 31) |
106 | |
107 | #define RME96_WCR_BITPOS_GAIN_0 2 |
108 | #define RME96_WCR_BITPOS_GAIN_1 3 |
109 | #define RME96_WCR_BITPOS_FREQ_0 9 |
110 | #define RME96_WCR_BITPOS_FREQ_1 10 |
111 | #define RME96_WCR_BITPOS_INP_0 17 |
112 | #define RME96_WCR_BITPOS_INP_1 18 |
113 | #define RME96_WCR_BITPOS_MONITOR_0 28 |
114 | #define RME96_WCR_BITPOS_MONITOR_1 29 |
115 | |
116 | /* Read control register bits */ |
117 | #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF |
118 | #define RME96_RCR_IRQ_2 (1 << 16) |
119 | #define RME96_RCR_T_OUT (1 << 17) |
120 | #define RME96_RCR_DEV_ID_0 (1 << 21) |
121 | #define RME96_RCR_DEV_ID_1 (1 << 22) |
122 | #define RME96_RCR_LOCK (1 << 23) |
123 | #define RME96_RCR_VERF (1 << 26) |
124 | #define RME96_RCR_F0 (1 << 27) |
125 | #define RME96_RCR_F1 (1 << 28) |
126 | #define RME96_RCR_F2 (1 << 29) |
127 | #define RME96_RCR_AUTOSYNC (1 << 30) |
128 | #define RME96_RCR_IRQ (1 << 31) |
129 | |
130 | #define RME96_RCR_BITPOS_F0 27 |
131 | #define RME96_RCR_BITPOS_F1 28 |
132 | #define RME96_RCR_BITPOS_F2 29 |
133 | |
134 | /* Additional register bits */ |
135 | #define RME96_AR_WSEL (1 << 0) |
136 | #define RME96_AR_ANALOG (1 << 1) |
137 | #define RME96_AR_FREQPAD_0 (1 << 2) |
138 | #define RME96_AR_FREQPAD_1 (1 << 3) |
139 | #define RME96_AR_FREQPAD_2 (1 << 4) |
140 | #define RME96_AR_PD2 (1 << 5) |
141 | #define RME96_AR_DAC_EN (1 << 6) |
142 | #define RME96_AR_CLATCH (1 << 7) |
143 | #define RME96_AR_CCLK (1 << 8) |
144 | #define RME96_AR_CDATA (1 << 9) |
145 | |
146 | #define RME96_AR_BITPOS_F0 2 |
147 | #define RME96_AR_BITPOS_F1 3 |
148 | #define RME96_AR_BITPOS_F2 4 |
149 | |
150 | /* Monitor tracks */ |
151 | #define RME96_MONITOR_TRACKS_1_2 0 |
152 | #define RME96_MONITOR_TRACKS_3_4 1 |
153 | #define RME96_MONITOR_TRACKS_5_6 2 |
154 | #define RME96_MONITOR_TRACKS_7_8 3 |
155 | |
156 | /* Attenuation */ |
157 | #define RME96_ATTENUATION_0 0 |
158 | #define RME96_ATTENUATION_6 1 |
159 | #define RME96_ATTENUATION_12 2 |
160 | #define RME96_ATTENUATION_18 3 |
161 | |
162 | /* Input types */ |
163 | #define RME96_INPUT_OPTICAL 0 |
164 | #define RME96_INPUT_COAXIAL 1 |
165 | #define RME96_INPUT_INTERNAL 2 |
166 | #define RME96_INPUT_XLR 3 |
167 | #define RME96_INPUT_ANALOG 4 |
168 | |
169 | /* Clock modes */ |
170 | #define RME96_CLOCKMODE_SLAVE 0 |
171 | #define RME96_CLOCKMODE_MASTER 1 |
172 | #define RME96_CLOCKMODE_WORDCLOCK 2 |
173 | |
174 | /* Block sizes in bytes */ |
175 | #define RME96_SMALL_BLOCK_SIZE 2048 |
176 | #define RME96_LARGE_BLOCK_SIZE 8192 |
177 | |
178 | /* Volume control */ |
179 | #define RME96_AD1852_VOL_BITS 14 |
180 | #define RME96_AD1855_VOL_BITS 10 |
181 | |
182 | /* Defines for snd_rme96_trigger */ |
183 | #define RME96_TB_START_PLAYBACK 1 |
184 | #define RME96_TB_START_CAPTURE 2 |
185 | #define RME96_TB_STOP_PLAYBACK 4 |
186 | #define RME96_TB_STOP_CAPTURE 8 |
187 | #define RME96_TB_RESET_PLAYPOS 16 |
188 | #define RME96_TB_RESET_CAPTUREPOS 32 |
189 | #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 |
190 | #define RME96_TB_CLEAR_CAPTURE_IRQ 128 |
191 | #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) |
192 | #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) |
193 | #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ |
194 | | RME96_RESUME_CAPTURE) |
195 | #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ |
196 | | RME96_TB_RESET_PLAYPOS) |
197 | #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ |
198 | | RME96_TB_RESET_CAPTUREPOS) |
199 | #define RME96_START_BOTH (RME96_START_PLAYBACK \ |
200 | | RME96_START_CAPTURE) |
201 | #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ |
202 | | RME96_TB_CLEAR_PLAYBACK_IRQ) |
203 | #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ |
204 | | RME96_TB_CLEAR_CAPTURE_IRQ) |
205 | #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ |
206 | | RME96_STOP_CAPTURE) |
207 | |
208 | struct rme96 { |
209 | spinlock_t lock; |
210 | int irq; |
211 | unsigned long port; |
212 | void __iomem *iobase; |
213 | |
214 | u32 wcreg; /* cached write control register value */ |
215 | u32 wcreg_spdif; /* S/PDIF setup */ |
216 | u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ |
217 | u32 rcreg; /* cached read control register value */ |
218 | u32 areg; /* cached additional register value */ |
219 | u16 vol[2]; /* cached volume of analog output */ |
220 | |
221 | u8 rev; /* card revision number */ |
222 | |
223 | #ifdef CONFIG_PM_SLEEP |
224 | u32 playback_pointer; |
225 | u32 capture_pointer; |
226 | void *playback_suspend_buffer; |
227 | void *capture_suspend_buffer; |
228 | #endif |
229 | |
230 | struct snd_pcm_substream *playback_substream; |
231 | struct snd_pcm_substream *capture_substream; |
232 | |
233 | int playback_frlog; /* log2 of framesize */ |
234 | int capture_frlog; |
235 | |
236 | size_t playback_periodsize; /* in bytes, zero if not used */ |
237 | size_t capture_periodsize; /* in bytes, zero if not used */ |
238 | |
239 | struct snd_card *card; |
240 | struct snd_pcm *spdif_pcm; |
241 | struct snd_pcm *adat_pcm; |
242 | struct pci_dev *pci; |
243 | struct snd_kcontrol *spdif_ctl; |
244 | }; |
245 | |
246 | static const struct pci_device_id snd_rme96_ids[] = { |
247 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, |
248 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, |
249 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, |
250 | { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, |
251 | { 0, } |
252 | }; |
253 | |
254 | MODULE_DEVICE_TABLE(pci, snd_rme96_ids); |
255 | |
256 | #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) |
257 | #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) |
258 | #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) |
259 | #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ |
260 | (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) |
261 | #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) |
262 | #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ |
263 | ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) |
264 | #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) |
265 | |
266 | static int |
267 | snd_rme96_playback_prepare(struct snd_pcm_substream *substream); |
268 | |
269 | static int |
270 | snd_rme96_capture_prepare(struct snd_pcm_substream *substream); |
271 | |
272 | static int |
273 | snd_rme96_playback_trigger(struct snd_pcm_substream *substream, |
274 | int cmd); |
275 | |
276 | static int |
277 | snd_rme96_capture_trigger(struct snd_pcm_substream *substream, |
278 | int cmd); |
279 | |
280 | static snd_pcm_uframes_t |
281 | snd_rme96_playback_pointer(struct snd_pcm_substream *substream); |
282 | |
283 | static snd_pcm_uframes_t |
284 | snd_rme96_capture_pointer(struct snd_pcm_substream *substream); |
285 | |
286 | static void snd_rme96_proc_init(struct rme96 *rme96); |
287 | |
288 | static int |
289 | snd_rme96_create_switches(struct snd_card *card, |
290 | struct rme96 *rme96); |
291 | |
292 | static int |
293 | snd_rme96_getinputtype(struct rme96 *rme96); |
294 | |
295 | static inline unsigned int |
296 | snd_rme96_playback_ptr(struct rme96 *rme96) |
297 | { |
298 | return (readl(addr: rme96->iobase + RME96_IO_GET_PLAY_POS) |
299 | & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; |
300 | } |
301 | |
302 | static inline unsigned int |
303 | snd_rme96_capture_ptr(struct rme96 *rme96) |
304 | { |
305 | return (readl(addr: rme96->iobase + RME96_IO_GET_REC_POS) |
306 | & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; |
307 | } |
308 | |
309 | static int |
310 | snd_rme96_playback_silence(struct snd_pcm_substream *substream, |
311 | int channel, unsigned long pos, unsigned long count) |
312 | { |
313 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
314 | |
315 | memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, |
316 | 0, count); |
317 | return 0; |
318 | } |
319 | |
320 | static int |
321 | snd_rme96_playback_copy(struct snd_pcm_substream *substream, |
322 | int channel, unsigned long pos, |
323 | struct iov_iter *src, unsigned long count) |
324 | { |
325 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
326 | |
327 | return copy_from_iter_toio(dst: rme96->iobase + RME96_IO_PLAY_BUFFER + pos, |
328 | iter: src, count); |
329 | } |
330 | |
331 | static int |
332 | snd_rme96_capture_copy(struct snd_pcm_substream *substream, |
333 | int channel, unsigned long pos, |
334 | struct iov_iter *dst, unsigned long count) |
335 | { |
336 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
337 | |
338 | return copy_to_iter_fromio(itert: dst, |
339 | src: rme96->iobase + RME96_IO_REC_BUFFER + pos, |
340 | count); |
341 | } |
342 | |
343 | /* |
344 | * Digital output capabilities (S/PDIF) |
345 | */ |
346 | static const struct snd_pcm_hardware snd_rme96_playback_spdif_info = |
347 | { |
348 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | |
349 | SNDRV_PCM_INFO_MMAP_VALID | |
350 | SNDRV_PCM_INFO_SYNC_START | |
351 | SNDRV_PCM_INFO_RESUME | |
352 | SNDRV_PCM_INFO_INTERLEAVED | |
353 | SNDRV_PCM_INFO_PAUSE), |
354 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | |
355 | SNDRV_PCM_FMTBIT_S32_LE), |
356 | .rates = (SNDRV_PCM_RATE_32000 | |
357 | SNDRV_PCM_RATE_44100 | |
358 | SNDRV_PCM_RATE_48000 | |
359 | SNDRV_PCM_RATE_64000 | |
360 | SNDRV_PCM_RATE_88200 | |
361 | SNDRV_PCM_RATE_96000), |
362 | .rate_min = 32000, |
363 | .rate_max = 96000, |
364 | .channels_min = 2, |
365 | .channels_max = 2, |
366 | .buffer_bytes_max = RME96_BUFFER_SIZE, |
367 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, |
368 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, |
369 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, |
370 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, |
371 | .fifo_size = 0, |
372 | }; |
373 | |
374 | /* |
375 | * Digital input capabilities (S/PDIF) |
376 | */ |
377 | static const struct snd_pcm_hardware snd_rme96_capture_spdif_info = |
378 | { |
379 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | |
380 | SNDRV_PCM_INFO_MMAP_VALID | |
381 | SNDRV_PCM_INFO_SYNC_START | |
382 | SNDRV_PCM_INFO_RESUME | |
383 | SNDRV_PCM_INFO_INTERLEAVED | |
384 | SNDRV_PCM_INFO_PAUSE), |
385 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | |
386 | SNDRV_PCM_FMTBIT_S32_LE), |
387 | .rates = (SNDRV_PCM_RATE_32000 | |
388 | SNDRV_PCM_RATE_44100 | |
389 | SNDRV_PCM_RATE_48000 | |
390 | SNDRV_PCM_RATE_64000 | |
391 | SNDRV_PCM_RATE_88200 | |
392 | SNDRV_PCM_RATE_96000), |
393 | .rate_min = 32000, |
394 | .rate_max = 96000, |
395 | .channels_min = 2, |
396 | .channels_max = 2, |
397 | .buffer_bytes_max = RME96_BUFFER_SIZE, |
398 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, |
399 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, |
400 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, |
401 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, |
402 | .fifo_size = 0, |
403 | }; |
404 | |
405 | /* |
406 | * Digital output capabilities (ADAT) |
407 | */ |
408 | static const struct snd_pcm_hardware snd_rme96_playback_adat_info = |
409 | { |
410 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | |
411 | SNDRV_PCM_INFO_MMAP_VALID | |
412 | SNDRV_PCM_INFO_SYNC_START | |
413 | SNDRV_PCM_INFO_RESUME | |
414 | SNDRV_PCM_INFO_INTERLEAVED | |
415 | SNDRV_PCM_INFO_PAUSE), |
416 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | |
417 | SNDRV_PCM_FMTBIT_S32_LE), |
418 | .rates = (SNDRV_PCM_RATE_44100 | |
419 | SNDRV_PCM_RATE_48000), |
420 | .rate_min = 44100, |
421 | .rate_max = 48000, |
422 | .channels_min = 8, |
423 | .channels_max = 8, |
424 | .buffer_bytes_max = RME96_BUFFER_SIZE, |
425 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, |
426 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, |
427 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, |
428 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, |
429 | .fifo_size = 0, |
430 | }; |
431 | |
432 | /* |
433 | * Digital input capabilities (ADAT) |
434 | */ |
435 | static const struct snd_pcm_hardware snd_rme96_capture_adat_info = |
436 | { |
437 | .info = (SNDRV_PCM_INFO_MMAP_IOMEM | |
438 | SNDRV_PCM_INFO_MMAP_VALID | |
439 | SNDRV_PCM_INFO_SYNC_START | |
440 | SNDRV_PCM_INFO_RESUME | |
441 | SNDRV_PCM_INFO_INTERLEAVED | |
442 | SNDRV_PCM_INFO_PAUSE), |
443 | .formats = (SNDRV_PCM_FMTBIT_S16_LE | |
444 | SNDRV_PCM_FMTBIT_S32_LE), |
445 | .rates = (SNDRV_PCM_RATE_44100 | |
446 | SNDRV_PCM_RATE_48000), |
447 | .rate_min = 44100, |
448 | .rate_max = 48000, |
449 | .channels_min = 8, |
450 | .channels_max = 8, |
451 | .buffer_bytes_max = RME96_BUFFER_SIZE, |
452 | .period_bytes_min = RME96_SMALL_BLOCK_SIZE, |
453 | .period_bytes_max = RME96_LARGE_BLOCK_SIZE, |
454 | .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, |
455 | .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, |
456 | .fifo_size = 0, |
457 | }; |
458 | |
459 | /* |
460 | * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface |
461 | * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up |
462 | * on the falling edge of CCLK and be stable on the rising edge. The rising |
463 | * edge of CLATCH after the last data bit clocks in the whole data word. |
464 | * A fast processor could probably drive the SPI interface faster than the |
465 | * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) |
466 | * limits the data rate to 500KHz and only causes a delay of 33 microsecs. |
467 | * |
468 | * NOTE: increased delay from 1 to 10, since there where problems setting |
469 | * the volume. |
470 | */ |
471 | static void |
472 | snd_rme96_write_SPI(struct rme96 *rme96, u16 val) |
473 | { |
474 | int i; |
475 | |
476 | for (i = 0; i < 16; i++) { |
477 | if (val & 0x8000) { |
478 | rme96->areg |= RME96_AR_CDATA; |
479 | } else { |
480 | rme96->areg &= ~RME96_AR_CDATA; |
481 | } |
482 | rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); |
483 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
484 | udelay(10); |
485 | rme96->areg |= RME96_AR_CCLK; |
486 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
487 | udelay(10); |
488 | val <<= 1; |
489 | } |
490 | rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); |
491 | rme96->areg |= RME96_AR_CLATCH; |
492 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
493 | udelay(10); |
494 | rme96->areg &= ~RME96_AR_CLATCH; |
495 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
496 | } |
497 | |
498 | static void |
499 | snd_rme96_apply_dac_volume(struct rme96 *rme96) |
500 | { |
501 | if (RME96_DAC_IS_1852(rme96)) { |
502 | snd_rme96_write_SPI(rme96, val: (rme96->vol[0] << 2) | 0x0); |
503 | snd_rme96_write_SPI(rme96, val: (rme96->vol[1] << 2) | 0x2); |
504 | } else if (RME96_DAC_IS_1855(rme96)) { |
505 | snd_rme96_write_SPI(rme96, val: (rme96->vol[0] & 0x3FF) | 0x000); |
506 | snd_rme96_write_SPI(rme96, val: (rme96->vol[1] & 0x3FF) | 0x400); |
507 | } |
508 | } |
509 | |
510 | static void |
511 | snd_rme96_reset_dac(struct rme96 *rme96) |
512 | { |
513 | writel(val: rme96->wcreg | RME96_WCR_PD, |
514 | addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
515 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
516 | } |
517 | |
518 | static int |
519 | snd_rme96_getmontracks(struct rme96 *rme96) |
520 | { |
521 | return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + |
522 | (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); |
523 | } |
524 | |
525 | static int |
526 | snd_rme96_setmontracks(struct rme96 *rme96, |
527 | int montracks) |
528 | { |
529 | if (montracks & 1) { |
530 | rme96->wcreg |= RME96_WCR_MONITOR_0; |
531 | } else { |
532 | rme96->wcreg &= ~RME96_WCR_MONITOR_0; |
533 | } |
534 | if (montracks & 2) { |
535 | rme96->wcreg |= RME96_WCR_MONITOR_1; |
536 | } else { |
537 | rme96->wcreg &= ~RME96_WCR_MONITOR_1; |
538 | } |
539 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
540 | return 0; |
541 | } |
542 | |
543 | static int |
544 | snd_rme96_getattenuation(struct rme96 *rme96) |
545 | { |
546 | return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + |
547 | (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); |
548 | } |
549 | |
550 | static int |
551 | snd_rme96_setattenuation(struct rme96 *rme96, |
552 | int attenuation) |
553 | { |
554 | switch (attenuation) { |
555 | case 0: |
556 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & |
557 | ~RME96_WCR_GAIN_1; |
558 | break; |
559 | case 1: |
560 | rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & |
561 | ~RME96_WCR_GAIN_1; |
562 | break; |
563 | case 2: |
564 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | |
565 | RME96_WCR_GAIN_1; |
566 | break; |
567 | case 3: |
568 | rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | |
569 | RME96_WCR_GAIN_1; |
570 | break; |
571 | default: |
572 | return -EINVAL; |
573 | } |
574 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
575 | return 0; |
576 | } |
577 | |
578 | static int |
579 | snd_rme96_capture_getrate(struct rme96 *rme96, |
580 | int *is_adat) |
581 | { |
582 | int n, rate; |
583 | |
584 | *is_adat = 0; |
585 | if (rme96->areg & RME96_AR_ANALOG) { |
586 | /* Analog input, overrides S/PDIF setting */ |
587 | n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + |
588 | (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); |
589 | switch (n) { |
590 | case 1: |
591 | rate = 32000; |
592 | break; |
593 | case 2: |
594 | rate = 44100; |
595 | break; |
596 | case 3: |
597 | rate = 48000; |
598 | break; |
599 | default: |
600 | return -1; |
601 | } |
602 | return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; |
603 | } |
604 | |
605 | rme96->rcreg = readl(addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
606 | if (rme96->rcreg & RME96_RCR_LOCK) { |
607 | /* ADAT rate */ |
608 | *is_adat = 1; |
609 | if (rme96->rcreg & RME96_RCR_T_OUT) { |
610 | return 48000; |
611 | } |
612 | return 44100; |
613 | } |
614 | |
615 | if (rme96->rcreg & RME96_RCR_VERF) { |
616 | return -1; |
617 | } |
618 | |
619 | /* S/PDIF rate */ |
620 | n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + |
621 | (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + |
622 | (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); |
623 | |
624 | switch (n) { |
625 | case 0: |
626 | if (rme96->rcreg & RME96_RCR_T_OUT) { |
627 | return 64000; |
628 | } |
629 | return -1; |
630 | case 3: return 96000; |
631 | case 4: return 88200; |
632 | case 5: return 48000; |
633 | case 6: return 44100; |
634 | case 7: return 32000; |
635 | default: |
636 | break; |
637 | } |
638 | return -1; |
639 | } |
640 | |
641 | static int |
642 | snd_rme96_playback_getrate(struct rme96 *rme96) |
643 | { |
644 | int rate, dummy; |
645 | |
646 | if (!(rme96->wcreg & RME96_WCR_MASTER) && |
647 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
648 | rate = snd_rme96_capture_getrate(rme96, is_adat: &dummy); |
649 | if (rate > 0) { |
650 | /* slave clock */ |
651 | return rate; |
652 | } |
653 | } |
654 | |
655 | rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + |
656 | (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); |
657 | switch (rate) { |
658 | case 1: |
659 | rate = 32000; |
660 | break; |
661 | case 2: |
662 | rate = 44100; |
663 | break; |
664 | case 3: |
665 | rate = 48000; |
666 | break; |
667 | default: |
668 | return -1; |
669 | } |
670 | return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; |
671 | } |
672 | |
673 | static int |
674 | snd_rme96_playback_setrate(struct rme96 *rme96, |
675 | int rate) |
676 | { |
677 | int ds; |
678 | |
679 | ds = rme96->wcreg & RME96_WCR_DS; |
680 | switch (rate) { |
681 | case 32000: |
682 | rme96->wcreg &= ~RME96_WCR_DS; |
683 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & |
684 | ~RME96_WCR_FREQ_1; |
685 | break; |
686 | case 44100: |
687 | rme96->wcreg &= ~RME96_WCR_DS; |
688 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & |
689 | ~RME96_WCR_FREQ_0; |
690 | break; |
691 | case 48000: |
692 | rme96->wcreg &= ~RME96_WCR_DS; |
693 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | |
694 | RME96_WCR_FREQ_1; |
695 | break; |
696 | case 64000: |
697 | rme96->wcreg |= RME96_WCR_DS; |
698 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & |
699 | ~RME96_WCR_FREQ_1; |
700 | break; |
701 | case 88200: |
702 | rme96->wcreg |= RME96_WCR_DS; |
703 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & |
704 | ~RME96_WCR_FREQ_0; |
705 | break; |
706 | case 96000: |
707 | rme96->wcreg |= RME96_WCR_DS; |
708 | rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | |
709 | RME96_WCR_FREQ_1; |
710 | break; |
711 | default: |
712 | return -EINVAL; |
713 | } |
714 | if ((!ds && rme96->wcreg & RME96_WCR_DS) || |
715 | (ds && !(rme96->wcreg & RME96_WCR_DS))) |
716 | { |
717 | /* change to/from double-speed: reset the DAC (if available) */ |
718 | snd_rme96_reset_dac(rme96); |
719 | return 1; /* need to restore volume */ |
720 | } else { |
721 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
722 | return 0; |
723 | } |
724 | } |
725 | |
726 | static int |
727 | snd_rme96_capture_analog_setrate(struct rme96 *rme96, |
728 | int rate) |
729 | { |
730 | switch (rate) { |
731 | case 32000: |
732 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & |
733 | ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; |
734 | break; |
735 | case 44100: |
736 | rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | |
737 | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; |
738 | break; |
739 | case 48000: |
740 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | |
741 | RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; |
742 | break; |
743 | case 64000: |
744 | if (rme96->rev < 4) { |
745 | return -EINVAL; |
746 | } |
747 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & |
748 | ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; |
749 | break; |
750 | case 88200: |
751 | if (rme96->rev < 4) { |
752 | return -EINVAL; |
753 | } |
754 | rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | |
755 | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; |
756 | break; |
757 | case 96000: |
758 | rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | |
759 | RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; |
760 | break; |
761 | default: |
762 | return -EINVAL; |
763 | } |
764 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
765 | return 0; |
766 | } |
767 | |
768 | static int |
769 | snd_rme96_setclockmode(struct rme96 *rme96, |
770 | int mode) |
771 | { |
772 | switch (mode) { |
773 | case RME96_CLOCKMODE_SLAVE: |
774 | /* AutoSync */ |
775 | rme96->wcreg &= ~RME96_WCR_MASTER; |
776 | rme96->areg &= ~RME96_AR_WSEL; |
777 | break; |
778 | case RME96_CLOCKMODE_MASTER: |
779 | /* Internal */ |
780 | rme96->wcreg |= RME96_WCR_MASTER; |
781 | rme96->areg &= ~RME96_AR_WSEL; |
782 | break; |
783 | case RME96_CLOCKMODE_WORDCLOCK: |
784 | /* Word clock is a master mode */ |
785 | rme96->wcreg |= RME96_WCR_MASTER; |
786 | rme96->areg |= RME96_AR_WSEL; |
787 | break; |
788 | default: |
789 | return -EINVAL; |
790 | } |
791 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
792 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
793 | return 0; |
794 | } |
795 | |
796 | static int |
797 | snd_rme96_getclockmode(struct rme96 *rme96) |
798 | { |
799 | if (rme96->areg & RME96_AR_WSEL) { |
800 | return RME96_CLOCKMODE_WORDCLOCK; |
801 | } |
802 | return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : |
803 | RME96_CLOCKMODE_SLAVE; |
804 | } |
805 | |
806 | static int |
807 | snd_rme96_setinputtype(struct rme96 *rme96, |
808 | int type) |
809 | { |
810 | int n; |
811 | |
812 | switch (type) { |
813 | case RME96_INPUT_OPTICAL: |
814 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & |
815 | ~RME96_WCR_INP_1; |
816 | break; |
817 | case RME96_INPUT_COAXIAL: |
818 | rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & |
819 | ~RME96_WCR_INP_1; |
820 | break; |
821 | case RME96_INPUT_INTERNAL: |
822 | rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | |
823 | RME96_WCR_INP_1; |
824 | break; |
825 | case RME96_INPUT_XLR: |
826 | if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && |
827 | rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || |
828 | (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && |
829 | rme96->rev > 4)) |
830 | { |
831 | /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ |
832 | return -EINVAL; |
833 | } |
834 | rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | |
835 | RME96_WCR_INP_1; |
836 | break; |
837 | case RME96_INPUT_ANALOG: |
838 | if (!RME96_HAS_ANALOG_IN(rme96)) { |
839 | return -EINVAL; |
840 | } |
841 | rme96->areg |= RME96_AR_ANALOG; |
842 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
843 | if (rme96->rev < 4) { |
844 | /* |
845 | * Revision less than 004 does not support 64 and |
846 | * 88.2 kHz |
847 | */ |
848 | if (snd_rme96_capture_getrate(rme96, is_adat: &n) == 88200) { |
849 | snd_rme96_capture_analog_setrate(rme96, rate: 44100); |
850 | } |
851 | if (snd_rme96_capture_getrate(rme96, is_adat: &n) == 64000) { |
852 | snd_rme96_capture_analog_setrate(rme96, rate: 32000); |
853 | } |
854 | } |
855 | return 0; |
856 | default: |
857 | return -EINVAL; |
858 | } |
859 | if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { |
860 | rme96->areg &= ~RME96_AR_ANALOG; |
861 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
862 | } |
863 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
864 | return 0; |
865 | } |
866 | |
867 | static int |
868 | snd_rme96_getinputtype(struct rme96 *rme96) |
869 | { |
870 | if (rme96->areg & RME96_AR_ANALOG) { |
871 | return RME96_INPUT_ANALOG; |
872 | } |
873 | return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + |
874 | (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); |
875 | } |
876 | |
877 | static void |
878 | snd_rme96_setframelog(struct rme96 *rme96, |
879 | int n_channels, |
880 | int is_playback) |
881 | { |
882 | int frlog; |
883 | |
884 | if (n_channels == 2) { |
885 | frlog = 1; |
886 | } else { |
887 | /* assume 8 channels */ |
888 | frlog = 3; |
889 | } |
890 | if (is_playback) { |
891 | frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; |
892 | rme96->playback_frlog = frlog; |
893 | } else { |
894 | frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; |
895 | rme96->capture_frlog = frlog; |
896 | } |
897 | } |
898 | |
899 | static int |
900 | snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format) |
901 | { |
902 | switch (format) { |
903 | case SNDRV_PCM_FORMAT_S16_LE: |
904 | rme96->wcreg &= ~RME96_WCR_MODE24; |
905 | break; |
906 | case SNDRV_PCM_FORMAT_S32_LE: |
907 | rme96->wcreg |= RME96_WCR_MODE24; |
908 | break; |
909 | default: |
910 | return -EINVAL; |
911 | } |
912 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
913 | return 0; |
914 | } |
915 | |
916 | static int |
917 | snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format) |
918 | { |
919 | switch (format) { |
920 | case SNDRV_PCM_FORMAT_S16_LE: |
921 | rme96->wcreg &= ~RME96_WCR_MODE24_2; |
922 | break; |
923 | case SNDRV_PCM_FORMAT_S32_LE: |
924 | rme96->wcreg |= RME96_WCR_MODE24_2; |
925 | break; |
926 | default: |
927 | return -EINVAL; |
928 | } |
929 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
930 | return 0; |
931 | } |
932 | |
933 | static void |
934 | snd_rme96_set_period_properties(struct rme96 *rme96, |
935 | size_t period_bytes) |
936 | { |
937 | switch (period_bytes) { |
938 | case RME96_LARGE_BLOCK_SIZE: |
939 | rme96->wcreg &= ~RME96_WCR_ISEL; |
940 | break; |
941 | case RME96_SMALL_BLOCK_SIZE: |
942 | rme96->wcreg |= RME96_WCR_ISEL; |
943 | break; |
944 | default: |
945 | snd_BUG(); |
946 | break; |
947 | } |
948 | rme96->wcreg &= ~RME96_WCR_IDIS; |
949 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
950 | } |
951 | |
952 | static int |
953 | snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, |
954 | struct snd_pcm_hw_params *params) |
955 | { |
956 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
957 | struct snd_pcm_runtime *runtime = substream->runtime; |
958 | int err, rate, dummy; |
959 | bool apply_dac_volume = false; |
960 | |
961 | runtime->dma_area = (void __force *)(rme96->iobase + |
962 | RME96_IO_PLAY_BUFFER); |
963 | runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; |
964 | runtime->dma_bytes = RME96_BUFFER_SIZE; |
965 | |
966 | spin_lock_irq(lock: &rme96->lock); |
967 | rate = 0; |
968 | if (!(rme96->wcreg & RME96_WCR_MASTER) && |
969 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) |
970 | rate = snd_rme96_capture_getrate(rme96, is_adat: &dummy); |
971 | if (rate > 0) { |
972 | /* slave clock */ |
973 | if ((int)params_rate(p: params) != rate) { |
974 | err = -EIO; |
975 | goto error; |
976 | } |
977 | } else { |
978 | err = snd_rme96_playback_setrate(rme96, rate: params_rate(p: params)); |
979 | if (err < 0) |
980 | goto error; |
981 | apply_dac_volume = err > 0; /* need to restore volume later? */ |
982 | } |
983 | |
984 | err = snd_rme96_playback_setformat(rme96, format: params_format(p: params)); |
985 | if (err < 0) |
986 | goto error; |
987 | snd_rme96_setframelog(rme96, n_channels: params_channels(p: params), is_playback: 1); |
988 | if (rme96->capture_periodsize != 0) { |
989 | if (params_period_size(p: params) << rme96->playback_frlog != |
990 | rme96->capture_periodsize) |
991 | { |
992 | err = -EBUSY; |
993 | goto error; |
994 | } |
995 | } |
996 | rme96->playback_periodsize = |
997 | params_period_size(p: params) << rme96->playback_frlog; |
998 | snd_rme96_set_period_properties(rme96, period_bytes: rme96->playback_periodsize); |
999 | /* S/PDIF setup */ |
1000 | if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { |
1001 | rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); |
1002 | writel(val: rme96->wcreg |= rme96->wcreg_spdif_stream, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1003 | } |
1004 | |
1005 | err = 0; |
1006 | error: |
1007 | spin_unlock_irq(lock: &rme96->lock); |
1008 | if (apply_dac_volume) { |
1009 | usleep_range(min: 3000, max: 10000); |
1010 | snd_rme96_apply_dac_volume(rme96); |
1011 | } |
1012 | |
1013 | return err; |
1014 | } |
1015 | |
1016 | static int |
1017 | snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, |
1018 | struct snd_pcm_hw_params *params) |
1019 | { |
1020 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1021 | struct snd_pcm_runtime *runtime = substream->runtime; |
1022 | int err, isadat, rate; |
1023 | |
1024 | runtime->dma_area = (void __force *)(rme96->iobase + |
1025 | RME96_IO_REC_BUFFER); |
1026 | runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; |
1027 | runtime->dma_bytes = RME96_BUFFER_SIZE; |
1028 | |
1029 | spin_lock_irq(lock: &rme96->lock); |
1030 | err = snd_rme96_capture_setformat(rme96, format: params_format(p: params)); |
1031 | if (err < 0) { |
1032 | spin_unlock_irq(lock: &rme96->lock); |
1033 | return err; |
1034 | } |
1035 | if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { |
1036 | err = snd_rme96_capture_analog_setrate(rme96, rate: params_rate(p: params)); |
1037 | if (err < 0) { |
1038 | spin_unlock_irq(lock: &rme96->lock); |
1039 | return err; |
1040 | } |
1041 | } else { |
1042 | rate = snd_rme96_capture_getrate(rme96, is_adat: &isadat); |
1043 | if (rate > 0) { |
1044 | if ((int)params_rate(p: params) != rate) { |
1045 | spin_unlock_irq(lock: &rme96->lock); |
1046 | return -EIO; |
1047 | } |
1048 | if ((isadat && runtime->hw.channels_min == 2) || |
1049 | (!isadat && runtime->hw.channels_min == 8)) { |
1050 | spin_unlock_irq(lock: &rme96->lock); |
1051 | return -EIO; |
1052 | } |
1053 | } |
1054 | } |
1055 | snd_rme96_setframelog(rme96, n_channels: params_channels(p: params), is_playback: 0); |
1056 | if (rme96->playback_periodsize != 0) { |
1057 | if (params_period_size(p: params) << rme96->capture_frlog != |
1058 | rme96->playback_periodsize) |
1059 | { |
1060 | spin_unlock_irq(lock: &rme96->lock); |
1061 | return -EBUSY; |
1062 | } |
1063 | } |
1064 | rme96->capture_periodsize = |
1065 | params_period_size(p: params) << rme96->capture_frlog; |
1066 | snd_rme96_set_period_properties(rme96, period_bytes: rme96->capture_periodsize); |
1067 | spin_unlock_irq(lock: &rme96->lock); |
1068 | |
1069 | return 0; |
1070 | } |
1071 | |
1072 | static void |
1073 | snd_rme96_trigger(struct rme96 *rme96, |
1074 | int op) |
1075 | { |
1076 | if (op & RME96_TB_RESET_PLAYPOS) |
1077 | writel(val: 0, addr: rme96->iobase + RME96_IO_RESET_PLAY_POS); |
1078 | if (op & RME96_TB_RESET_CAPTUREPOS) |
1079 | writel(val: 0, addr: rme96->iobase + RME96_IO_RESET_REC_POS); |
1080 | if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { |
1081 | rme96->rcreg = readl(addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1082 | if (rme96->rcreg & RME96_RCR_IRQ) |
1083 | writel(val: 0, addr: rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); |
1084 | } |
1085 | if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { |
1086 | rme96->rcreg = readl(addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1087 | if (rme96->rcreg & RME96_RCR_IRQ_2) |
1088 | writel(val: 0, addr: rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); |
1089 | } |
1090 | if (op & RME96_TB_START_PLAYBACK) |
1091 | rme96->wcreg |= RME96_WCR_START; |
1092 | if (op & RME96_TB_STOP_PLAYBACK) |
1093 | rme96->wcreg &= ~RME96_WCR_START; |
1094 | if (op & RME96_TB_START_CAPTURE) |
1095 | rme96->wcreg |= RME96_WCR_START_2; |
1096 | if (op & RME96_TB_STOP_CAPTURE) |
1097 | rme96->wcreg &= ~RME96_WCR_START_2; |
1098 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1099 | } |
1100 | |
1101 | |
1102 | |
1103 | static irqreturn_t |
1104 | snd_rme96_interrupt(int irq, |
1105 | void *dev_id) |
1106 | { |
1107 | struct rme96 *rme96 = (struct rme96 *)dev_id; |
1108 | |
1109 | rme96->rcreg = readl(addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1110 | /* fastpath out, to ease interrupt sharing */ |
1111 | if (!((rme96->rcreg & RME96_RCR_IRQ) || |
1112 | (rme96->rcreg & RME96_RCR_IRQ_2))) |
1113 | { |
1114 | return IRQ_NONE; |
1115 | } |
1116 | |
1117 | if (rme96->rcreg & RME96_RCR_IRQ) { |
1118 | /* playback */ |
1119 | snd_pcm_period_elapsed(substream: rme96->playback_substream); |
1120 | writel(val: 0, addr: rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); |
1121 | } |
1122 | if (rme96->rcreg & RME96_RCR_IRQ_2) { |
1123 | /* capture */ |
1124 | snd_pcm_period_elapsed(substream: rme96->capture_substream); |
1125 | writel(val: 0, addr: rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); |
1126 | } |
1127 | return IRQ_HANDLED; |
1128 | } |
1129 | |
1130 | static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; |
1131 | |
1132 | static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { |
1133 | .count = ARRAY_SIZE(period_bytes), |
1134 | .list = period_bytes, |
1135 | .mask = 0 |
1136 | }; |
1137 | |
1138 | static void |
1139 | rme96_set_buffer_size_constraint(struct rme96 *rme96, |
1140 | struct snd_pcm_runtime *runtime) |
1141 | { |
1142 | unsigned int size; |
1143 | |
1144 | snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, |
1145 | RME96_BUFFER_SIZE); |
1146 | size = rme96->playback_periodsize; |
1147 | if (!size) |
1148 | size = rme96->capture_periodsize; |
1149 | if (size) |
1150 | snd_pcm_hw_constraint_single(runtime, |
1151 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
1152 | val: size); |
1153 | else |
1154 | snd_pcm_hw_constraint_list(runtime, cond: 0, |
1155 | SNDRV_PCM_HW_PARAM_PERIOD_BYTES, |
1156 | l: &hw_constraints_period_bytes); |
1157 | } |
1158 | |
1159 | static int |
1160 | snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) |
1161 | { |
1162 | int rate, dummy; |
1163 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1164 | struct snd_pcm_runtime *runtime = substream->runtime; |
1165 | |
1166 | snd_pcm_set_sync(substream); |
1167 | spin_lock_irq(lock: &rme96->lock); |
1168 | if (rme96->playback_substream) { |
1169 | spin_unlock_irq(lock: &rme96->lock); |
1170 | return -EBUSY; |
1171 | } |
1172 | rme96->wcreg &= ~RME96_WCR_ADAT; |
1173 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1174 | rme96->playback_substream = substream; |
1175 | spin_unlock_irq(lock: &rme96->lock); |
1176 | |
1177 | runtime->hw = snd_rme96_playback_spdif_info; |
1178 | if (!(rme96->wcreg & RME96_WCR_MASTER) && |
1179 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
1180 | rate = snd_rme96_capture_getrate(rme96, is_adat: &dummy); |
1181 | if (rate > 0) { |
1182 | /* slave clock */ |
1183 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1184 | runtime->hw.rate_min = rate; |
1185 | runtime->hw.rate_max = rate; |
1186 | } |
1187 | } |
1188 | rme96_set_buffer_size_constraint(rme96, runtime); |
1189 | |
1190 | rme96->wcreg_spdif_stream = rme96->wcreg_spdif; |
1191 | rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; |
1192 | snd_ctl_notify(card: rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | |
1193 | SNDRV_CTL_EVENT_MASK_INFO, id: &rme96->spdif_ctl->id); |
1194 | return 0; |
1195 | } |
1196 | |
1197 | static int |
1198 | snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) |
1199 | { |
1200 | int isadat, rate; |
1201 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1202 | struct snd_pcm_runtime *runtime = substream->runtime; |
1203 | |
1204 | snd_pcm_set_sync(substream); |
1205 | runtime->hw = snd_rme96_capture_spdif_info; |
1206 | if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
1207 | rate = snd_rme96_capture_getrate(rme96, is_adat: &isadat); |
1208 | if (rate > 0) { |
1209 | if (isadat) |
1210 | return -EIO; |
1211 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1212 | runtime->hw.rate_min = rate; |
1213 | runtime->hw.rate_max = rate; |
1214 | } |
1215 | } |
1216 | |
1217 | spin_lock_irq(lock: &rme96->lock); |
1218 | if (rme96->capture_substream) { |
1219 | spin_unlock_irq(lock: &rme96->lock); |
1220 | return -EBUSY; |
1221 | } |
1222 | rme96->capture_substream = substream; |
1223 | spin_unlock_irq(lock: &rme96->lock); |
1224 | |
1225 | rme96_set_buffer_size_constraint(rme96, runtime); |
1226 | return 0; |
1227 | } |
1228 | |
1229 | static int |
1230 | snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) |
1231 | { |
1232 | int rate, dummy; |
1233 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1234 | struct snd_pcm_runtime *runtime = substream->runtime; |
1235 | |
1236 | snd_pcm_set_sync(substream); |
1237 | spin_lock_irq(lock: &rme96->lock); |
1238 | if (rme96->playback_substream) { |
1239 | spin_unlock_irq(lock: &rme96->lock); |
1240 | return -EBUSY; |
1241 | } |
1242 | rme96->wcreg |= RME96_WCR_ADAT; |
1243 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1244 | rme96->playback_substream = substream; |
1245 | spin_unlock_irq(lock: &rme96->lock); |
1246 | |
1247 | runtime->hw = snd_rme96_playback_adat_info; |
1248 | if (!(rme96->wcreg & RME96_WCR_MASTER) && |
1249 | snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { |
1250 | rate = snd_rme96_capture_getrate(rme96, is_adat: &dummy); |
1251 | if (rate > 0) { |
1252 | /* slave clock */ |
1253 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1254 | runtime->hw.rate_min = rate; |
1255 | runtime->hw.rate_max = rate; |
1256 | } |
1257 | } |
1258 | |
1259 | rme96_set_buffer_size_constraint(rme96, runtime); |
1260 | return 0; |
1261 | } |
1262 | |
1263 | static int |
1264 | snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) |
1265 | { |
1266 | int isadat, rate; |
1267 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1268 | struct snd_pcm_runtime *runtime = substream->runtime; |
1269 | |
1270 | snd_pcm_set_sync(substream); |
1271 | runtime->hw = snd_rme96_capture_adat_info; |
1272 | if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { |
1273 | /* makes no sense to use analog input. Note that analog |
1274 | expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ |
1275 | return -EIO; |
1276 | } |
1277 | rate = snd_rme96_capture_getrate(rme96, is_adat: &isadat); |
1278 | if (rate > 0) { |
1279 | if (!isadat) { |
1280 | return -EIO; |
1281 | } |
1282 | runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); |
1283 | runtime->hw.rate_min = rate; |
1284 | runtime->hw.rate_max = rate; |
1285 | } |
1286 | |
1287 | spin_lock_irq(lock: &rme96->lock); |
1288 | if (rme96->capture_substream) { |
1289 | spin_unlock_irq(lock: &rme96->lock); |
1290 | return -EBUSY; |
1291 | } |
1292 | rme96->capture_substream = substream; |
1293 | spin_unlock_irq(lock: &rme96->lock); |
1294 | |
1295 | rme96_set_buffer_size_constraint(rme96, runtime); |
1296 | return 0; |
1297 | } |
1298 | |
1299 | static int |
1300 | snd_rme96_playback_close(struct snd_pcm_substream *substream) |
1301 | { |
1302 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1303 | int spdif = 0; |
1304 | |
1305 | spin_lock_irq(lock: &rme96->lock); |
1306 | if (RME96_ISPLAYING(rme96)) { |
1307 | snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); |
1308 | } |
1309 | rme96->playback_substream = NULL; |
1310 | rme96->playback_periodsize = 0; |
1311 | spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; |
1312 | spin_unlock_irq(lock: &rme96->lock); |
1313 | if (spdif) { |
1314 | rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; |
1315 | snd_ctl_notify(card: rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | |
1316 | SNDRV_CTL_EVENT_MASK_INFO, id: &rme96->spdif_ctl->id); |
1317 | } |
1318 | return 0; |
1319 | } |
1320 | |
1321 | static int |
1322 | snd_rme96_capture_close(struct snd_pcm_substream *substream) |
1323 | { |
1324 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1325 | |
1326 | spin_lock_irq(lock: &rme96->lock); |
1327 | if (RME96_ISRECORDING(rme96)) { |
1328 | snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); |
1329 | } |
1330 | rme96->capture_substream = NULL; |
1331 | rme96->capture_periodsize = 0; |
1332 | spin_unlock_irq(lock: &rme96->lock); |
1333 | return 0; |
1334 | } |
1335 | |
1336 | static int |
1337 | snd_rme96_playback_prepare(struct snd_pcm_substream *substream) |
1338 | { |
1339 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1340 | |
1341 | spin_lock_irq(lock: &rme96->lock); |
1342 | if (RME96_ISPLAYING(rme96)) { |
1343 | snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); |
1344 | } |
1345 | writel(val: 0, addr: rme96->iobase + RME96_IO_RESET_PLAY_POS); |
1346 | spin_unlock_irq(lock: &rme96->lock); |
1347 | return 0; |
1348 | } |
1349 | |
1350 | static int |
1351 | snd_rme96_capture_prepare(struct snd_pcm_substream *substream) |
1352 | { |
1353 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1354 | |
1355 | spin_lock_irq(lock: &rme96->lock); |
1356 | if (RME96_ISRECORDING(rme96)) { |
1357 | snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); |
1358 | } |
1359 | writel(val: 0, addr: rme96->iobase + RME96_IO_RESET_REC_POS); |
1360 | spin_unlock_irq(lock: &rme96->lock); |
1361 | return 0; |
1362 | } |
1363 | |
1364 | static int |
1365 | snd_rme96_playback_trigger(struct snd_pcm_substream *substream, |
1366 | int cmd) |
1367 | { |
1368 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1369 | struct snd_pcm_substream *s; |
1370 | bool sync; |
1371 | |
1372 | snd_pcm_group_for_each_entry(s, substream) { |
1373 | if (snd_pcm_substream_chip(s) == rme96) |
1374 | snd_pcm_trigger_done(substream: s, master: substream); |
1375 | } |
1376 | |
1377 | sync = (rme96->playback_substream && rme96->capture_substream) && |
1378 | (rme96->playback_substream->group == |
1379 | rme96->capture_substream->group); |
1380 | |
1381 | switch (cmd) { |
1382 | case SNDRV_PCM_TRIGGER_START: |
1383 | if (!RME96_ISPLAYING(rme96)) { |
1384 | if (substream != rme96->playback_substream) |
1385 | return -EBUSY; |
1386 | snd_rme96_trigger(rme96, op: sync ? RME96_START_BOTH |
1387 | : RME96_START_PLAYBACK); |
1388 | } |
1389 | break; |
1390 | |
1391 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1392 | case SNDRV_PCM_TRIGGER_STOP: |
1393 | if (RME96_ISPLAYING(rme96)) { |
1394 | if (substream != rme96->playback_substream) |
1395 | return -EBUSY; |
1396 | snd_rme96_trigger(rme96, op: sync ? RME96_STOP_BOTH |
1397 | : RME96_STOP_PLAYBACK); |
1398 | } |
1399 | break; |
1400 | |
1401 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
1402 | if (RME96_ISPLAYING(rme96)) |
1403 | snd_rme96_trigger(rme96, op: sync ? RME96_STOP_BOTH |
1404 | : RME96_STOP_PLAYBACK); |
1405 | break; |
1406 | |
1407 | case SNDRV_PCM_TRIGGER_RESUME: |
1408 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1409 | if (!RME96_ISPLAYING(rme96)) |
1410 | snd_rme96_trigger(rme96, op: sync ? RME96_RESUME_BOTH |
1411 | : RME96_RESUME_PLAYBACK); |
1412 | break; |
1413 | |
1414 | default: |
1415 | return -EINVAL; |
1416 | } |
1417 | |
1418 | return 0; |
1419 | } |
1420 | |
1421 | static int |
1422 | snd_rme96_capture_trigger(struct snd_pcm_substream *substream, |
1423 | int cmd) |
1424 | { |
1425 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1426 | struct snd_pcm_substream *s; |
1427 | bool sync; |
1428 | |
1429 | snd_pcm_group_for_each_entry(s, substream) { |
1430 | if (snd_pcm_substream_chip(s) == rme96) |
1431 | snd_pcm_trigger_done(substream: s, master: substream); |
1432 | } |
1433 | |
1434 | sync = (rme96->playback_substream && rme96->capture_substream) && |
1435 | (rme96->playback_substream->group == |
1436 | rme96->capture_substream->group); |
1437 | |
1438 | switch (cmd) { |
1439 | case SNDRV_PCM_TRIGGER_START: |
1440 | if (!RME96_ISRECORDING(rme96)) { |
1441 | if (substream != rme96->capture_substream) |
1442 | return -EBUSY; |
1443 | snd_rme96_trigger(rme96, op: sync ? RME96_START_BOTH |
1444 | : RME96_START_CAPTURE); |
1445 | } |
1446 | break; |
1447 | |
1448 | case SNDRV_PCM_TRIGGER_SUSPEND: |
1449 | case SNDRV_PCM_TRIGGER_STOP: |
1450 | if (RME96_ISRECORDING(rme96)) { |
1451 | if (substream != rme96->capture_substream) |
1452 | return -EBUSY; |
1453 | snd_rme96_trigger(rme96, op: sync ? RME96_STOP_BOTH |
1454 | : RME96_STOP_CAPTURE); |
1455 | } |
1456 | break; |
1457 | |
1458 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
1459 | if (RME96_ISRECORDING(rme96)) |
1460 | snd_rme96_trigger(rme96, op: sync ? RME96_STOP_BOTH |
1461 | : RME96_STOP_CAPTURE); |
1462 | break; |
1463 | |
1464 | case SNDRV_PCM_TRIGGER_RESUME: |
1465 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
1466 | if (!RME96_ISRECORDING(rme96)) |
1467 | snd_rme96_trigger(rme96, op: sync ? RME96_RESUME_BOTH |
1468 | : RME96_RESUME_CAPTURE); |
1469 | break; |
1470 | |
1471 | default: |
1472 | return -EINVAL; |
1473 | } |
1474 | |
1475 | return 0; |
1476 | } |
1477 | |
1478 | static snd_pcm_uframes_t |
1479 | snd_rme96_playback_pointer(struct snd_pcm_substream *substream) |
1480 | { |
1481 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1482 | return snd_rme96_playback_ptr(rme96); |
1483 | } |
1484 | |
1485 | static snd_pcm_uframes_t |
1486 | snd_rme96_capture_pointer(struct snd_pcm_substream *substream) |
1487 | { |
1488 | struct rme96 *rme96 = snd_pcm_substream_chip(substream); |
1489 | return snd_rme96_capture_ptr(rme96); |
1490 | } |
1491 | |
1492 | static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = { |
1493 | .open = snd_rme96_playback_spdif_open, |
1494 | .close = snd_rme96_playback_close, |
1495 | .hw_params = snd_rme96_playback_hw_params, |
1496 | .prepare = snd_rme96_playback_prepare, |
1497 | .trigger = snd_rme96_playback_trigger, |
1498 | .pointer = snd_rme96_playback_pointer, |
1499 | .copy = snd_rme96_playback_copy, |
1500 | .fill_silence = snd_rme96_playback_silence, |
1501 | .mmap = snd_pcm_lib_mmap_iomem, |
1502 | }; |
1503 | |
1504 | static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = { |
1505 | .open = snd_rme96_capture_spdif_open, |
1506 | .close = snd_rme96_capture_close, |
1507 | .hw_params = snd_rme96_capture_hw_params, |
1508 | .prepare = snd_rme96_capture_prepare, |
1509 | .trigger = snd_rme96_capture_trigger, |
1510 | .pointer = snd_rme96_capture_pointer, |
1511 | .copy = snd_rme96_capture_copy, |
1512 | .mmap = snd_pcm_lib_mmap_iomem, |
1513 | }; |
1514 | |
1515 | static const struct snd_pcm_ops snd_rme96_playback_adat_ops = { |
1516 | .open = snd_rme96_playback_adat_open, |
1517 | .close = snd_rme96_playback_close, |
1518 | .hw_params = snd_rme96_playback_hw_params, |
1519 | .prepare = snd_rme96_playback_prepare, |
1520 | .trigger = snd_rme96_playback_trigger, |
1521 | .pointer = snd_rme96_playback_pointer, |
1522 | .copy = snd_rme96_playback_copy, |
1523 | .fill_silence = snd_rme96_playback_silence, |
1524 | .mmap = snd_pcm_lib_mmap_iomem, |
1525 | }; |
1526 | |
1527 | static const struct snd_pcm_ops snd_rme96_capture_adat_ops = { |
1528 | .open = snd_rme96_capture_adat_open, |
1529 | .close = snd_rme96_capture_close, |
1530 | .hw_params = snd_rme96_capture_hw_params, |
1531 | .prepare = snd_rme96_capture_prepare, |
1532 | .trigger = snd_rme96_capture_trigger, |
1533 | .pointer = snd_rme96_capture_pointer, |
1534 | .copy = snd_rme96_capture_copy, |
1535 | .mmap = snd_pcm_lib_mmap_iomem, |
1536 | }; |
1537 | |
1538 | static void |
1539 | snd_rme96_free(struct rme96 *rme96) |
1540 | { |
1541 | if (rme96->irq >= 0) { |
1542 | snd_rme96_trigger(rme96, RME96_STOP_BOTH); |
1543 | rme96->areg &= ~RME96_AR_DAC_EN; |
1544 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
1545 | } |
1546 | #ifdef CONFIG_PM_SLEEP |
1547 | vfree(addr: rme96->playback_suspend_buffer); |
1548 | vfree(addr: rme96->capture_suspend_buffer); |
1549 | #endif |
1550 | } |
1551 | |
1552 | static void |
1553 | snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) |
1554 | { |
1555 | struct rme96 *rme96 = pcm->private_data; |
1556 | rme96->spdif_pcm = NULL; |
1557 | } |
1558 | |
1559 | static void |
1560 | snd_rme96_free_adat_pcm(struct snd_pcm *pcm) |
1561 | { |
1562 | struct rme96 *rme96 = pcm->private_data; |
1563 | rme96->adat_pcm = NULL; |
1564 | } |
1565 | |
1566 | static int |
1567 | snd_rme96_create(struct rme96 *rme96) |
1568 | { |
1569 | struct pci_dev *pci = rme96->pci; |
1570 | int err; |
1571 | |
1572 | rme96->irq = -1; |
1573 | spin_lock_init(&rme96->lock); |
1574 | |
1575 | err = pcim_enable_device(pdev: pci); |
1576 | if (err < 0) |
1577 | return err; |
1578 | |
1579 | err = pci_request_regions(pci, "RME96" ); |
1580 | if (err < 0) |
1581 | return err; |
1582 | rme96->port = pci_resource_start(rme96->pci, 0); |
1583 | |
1584 | rme96->iobase = devm_ioremap(dev: &pci->dev, offset: rme96->port, RME96_IO_SIZE); |
1585 | if (!rme96->iobase) { |
1586 | dev_err(rme96->card->dev, |
1587 | "unable to remap memory region 0x%lx-0x%lx\n" , |
1588 | rme96->port, rme96->port + RME96_IO_SIZE - 1); |
1589 | return -EBUSY; |
1590 | } |
1591 | |
1592 | if (devm_request_irq(dev: &pci->dev, irq: pci->irq, handler: snd_rme96_interrupt, |
1593 | IRQF_SHARED, KBUILD_MODNAME, dev_id: rme96)) { |
1594 | dev_err(rme96->card->dev, "unable to grab IRQ %d\n" , pci->irq); |
1595 | return -EBUSY; |
1596 | } |
1597 | rme96->irq = pci->irq; |
1598 | rme96->card->sync_irq = rme96->irq; |
1599 | |
1600 | /* read the card's revision number */ |
1601 | pci_read_config_byte(dev: pci, where: 8, val: &rme96->rev); |
1602 | |
1603 | /* set up ALSA pcm device for S/PDIF */ |
1604 | err = snd_pcm_new(card: rme96->card, id: "Digi96 IEC958" , device: 0, |
1605 | playback_count: 1, capture_count: 1, rpcm: &rme96->spdif_pcm); |
1606 | if (err < 0) |
1607 | return err; |
1608 | |
1609 | rme96->spdif_pcm->private_data = rme96; |
1610 | rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; |
1611 | strcpy(p: rme96->spdif_pcm->name, q: "Digi96 IEC958" ); |
1612 | snd_pcm_set_ops(pcm: rme96->spdif_pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_rme96_playback_spdif_ops); |
1613 | snd_pcm_set_ops(pcm: rme96->spdif_pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &snd_rme96_capture_spdif_ops); |
1614 | |
1615 | rme96->spdif_pcm->info_flags = 0; |
1616 | |
1617 | /* set up ALSA pcm device for ADAT */ |
1618 | if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { |
1619 | /* ADAT is not available on the base model */ |
1620 | rme96->adat_pcm = NULL; |
1621 | } else { |
1622 | err = snd_pcm_new(card: rme96->card, id: "Digi96 ADAT" , device: 1, |
1623 | playback_count: 1, capture_count: 1, rpcm: &rme96->adat_pcm); |
1624 | if (err < 0) |
1625 | return err; |
1626 | rme96->adat_pcm->private_data = rme96; |
1627 | rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; |
1628 | strcpy(p: rme96->adat_pcm->name, q: "Digi96 ADAT" ); |
1629 | snd_pcm_set_ops(pcm: rme96->adat_pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_rme96_playback_adat_ops); |
1630 | snd_pcm_set_ops(pcm: rme96->adat_pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &snd_rme96_capture_adat_ops); |
1631 | |
1632 | rme96->adat_pcm->info_flags = 0; |
1633 | } |
1634 | |
1635 | rme96->playback_periodsize = 0; |
1636 | rme96->capture_periodsize = 0; |
1637 | |
1638 | /* make sure playback/capture is stopped, if by some reason active */ |
1639 | snd_rme96_trigger(rme96, RME96_STOP_BOTH); |
1640 | |
1641 | /* set default values in registers */ |
1642 | rme96->wcreg = |
1643 | RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ |
1644 | RME96_WCR_SEL | /* normal playback */ |
1645 | RME96_WCR_MASTER | /* set to master clock mode */ |
1646 | RME96_WCR_INP_0; /* set coaxial input */ |
1647 | |
1648 | rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ |
1649 | |
1650 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1651 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
1652 | |
1653 | /* reset the ADC */ |
1654 | writel(val: rme96->areg | RME96_AR_PD2, |
1655 | addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
1656 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
1657 | |
1658 | /* reset and enable the DAC (order is important). */ |
1659 | snd_rme96_reset_dac(rme96); |
1660 | rme96->areg |= RME96_AR_DAC_EN; |
1661 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
1662 | |
1663 | /* reset playback and record buffer pointers */ |
1664 | writel(val: 0, addr: rme96->iobase + RME96_IO_RESET_PLAY_POS); |
1665 | writel(val: 0, addr: rme96->iobase + RME96_IO_RESET_REC_POS); |
1666 | |
1667 | /* reset volume */ |
1668 | rme96->vol[0] = rme96->vol[1] = 0; |
1669 | if (RME96_HAS_ANALOG_OUT(rme96)) { |
1670 | snd_rme96_apply_dac_volume(rme96); |
1671 | } |
1672 | |
1673 | /* init switch interface */ |
1674 | err = snd_rme96_create_switches(card: rme96->card, rme96); |
1675 | if (err < 0) |
1676 | return err; |
1677 | |
1678 | /* init proc interface */ |
1679 | snd_rme96_proc_init(rme96); |
1680 | |
1681 | return 0; |
1682 | } |
1683 | |
1684 | /* |
1685 | * proc interface |
1686 | */ |
1687 | |
1688 | static void |
1689 | snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) |
1690 | { |
1691 | int n; |
1692 | struct rme96 *rme96 = entry->private_data; |
1693 | |
1694 | rme96->rcreg = readl(addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1695 | |
1696 | snd_iprintf(buffer, rme96->card->longname); |
1697 | snd_iprintf(buffer, " (index #%d)\n" , rme96->card->number + 1); |
1698 | |
1699 | snd_iprintf(buffer, "\nGeneral settings\n" ); |
1700 | if (rme96->wcreg & RME96_WCR_IDIS) { |
1701 | snd_iprintf(buffer, " period size: N/A (interrupts " |
1702 | "disabled)\n" ); |
1703 | } else if (rme96->wcreg & RME96_WCR_ISEL) { |
1704 | snd_iprintf(buffer, " period size: 2048 bytes\n" ); |
1705 | } else { |
1706 | snd_iprintf(buffer, " period size: 8192 bytes\n" ); |
1707 | } |
1708 | snd_iprintf(buffer, "\nInput settings\n" ); |
1709 | switch (snd_rme96_getinputtype(rme96)) { |
1710 | case RME96_INPUT_OPTICAL: |
1711 | snd_iprintf(buffer, " input: optical" ); |
1712 | break; |
1713 | case RME96_INPUT_COAXIAL: |
1714 | snd_iprintf(buffer, " input: coaxial" ); |
1715 | break; |
1716 | case RME96_INPUT_INTERNAL: |
1717 | snd_iprintf(buffer, " input: internal" ); |
1718 | break; |
1719 | case RME96_INPUT_XLR: |
1720 | snd_iprintf(buffer, " input: XLR" ); |
1721 | break; |
1722 | case RME96_INPUT_ANALOG: |
1723 | snd_iprintf(buffer, " input: analog" ); |
1724 | break; |
1725 | } |
1726 | if (snd_rme96_capture_getrate(rme96, is_adat: &n) < 0) { |
1727 | snd_iprintf(buffer, "\n sample rate: no valid signal\n" ); |
1728 | } else { |
1729 | if (n) { |
1730 | snd_iprintf(buffer, " (8 channels)\n" ); |
1731 | } else { |
1732 | snd_iprintf(buffer, " (2 channels)\n" ); |
1733 | } |
1734 | snd_iprintf(buffer, " sample rate: %d Hz\n" , |
1735 | snd_rme96_capture_getrate(rme96, &n)); |
1736 | } |
1737 | if (rme96->wcreg & RME96_WCR_MODE24_2) { |
1738 | snd_iprintf(buffer, " sample format: 24 bit\n" ); |
1739 | } else { |
1740 | snd_iprintf(buffer, " sample format: 16 bit\n" ); |
1741 | } |
1742 | |
1743 | snd_iprintf(buffer, "\nOutput settings\n" ); |
1744 | if (rme96->wcreg & RME96_WCR_SEL) { |
1745 | snd_iprintf(buffer, " output signal: normal playback\n" ); |
1746 | } else { |
1747 | snd_iprintf(buffer, " output signal: same as input\n" ); |
1748 | } |
1749 | snd_iprintf(buffer, " sample rate: %d Hz\n" , |
1750 | snd_rme96_playback_getrate(rme96)); |
1751 | if (rme96->wcreg & RME96_WCR_MODE24) { |
1752 | snd_iprintf(buffer, " sample format: 24 bit\n" ); |
1753 | } else { |
1754 | snd_iprintf(buffer, " sample format: 16 bit\n" ); |
1755 | } |
1756 | if (rme96->areg & RME96_AR_WSEL) { |
1757 | snd_iprintf(buffer, " sample clock source: word clock\n" ); |
1758 | } else if (rme96->wcreg & RME96_WCR_MASTER) { |
1759 | snd_iprintf(buffer, " sample clock source: internal\n" ); |
1760 | } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { |
1761 | snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n" ); |
1762 | } else if (snd_rme96_capture_getrate(rme96, is_adat: &n) < 0) { |
1763 | snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n" ); |
1764 | } else { |
1765 | snd_iprintf(buffer, " sample clock source: autosync\n" ); |
1766 | } |
1767 | if (rme96->wcreg & RME96_WCR_PRO) { |
1768 | snd_iprintf(buffer, " format: AES/EBU (professional)\n" ); |
1769 | } else { |
1770 | snd_iprintf(buffer, " format: IEC958 (consumer)\n" ); |
1771 | } |
1772 | if (rme96->wcreg & RME96_WCR_EMP) { |
1773 | snd_iprintf(buffer, " emphasis: on\n" ); |
1774 | } else { |
1775 | snd_iprintf(buffer, " emphasis: off\n" ); |
1776 | } |
1777 | if (rme96->wcreg & RME96_WCR_DOLBY) { |
1778 | snd_iprintf(buffer, " non-audio (dolby): on\n" ); |
1779 | } else { |
1780 | snd_iprintf(buffer, " non-audio (dolby): off\n" ); |
1781 | } |
1782 | if (RME96_HAS_ANALOG_IN(rme96)) { |
1783 | snd_iprintf(buffer, "\nAnalog output settings\n" ); |
1784 | switch (snd_rme96_getmontracks(rme96)) { |
1785 | case RME96_MONITOR_TRACKS_1_2: |
1786 | snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n" ); |
1787 | break; |
1788 | case RME96_MONITOR_TRACKS_3_4: |
1789 | snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n" ); |
1790 | break; |
1791 | case RME96_MONITOR_TRACKS_5_6: |
1792 | snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n" ); |
1793 | break; |
1794 | case RME96_MONITOR_TRACKS_7_8: |
1795 | snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n" ); |
1796 | break; |
1797 | } |
1798 | switch (snd_rme96_getattenuation(rme96)) { |
1799 | case RME96_ATTENUATION_0: |
1800 | snd_iprintf(buffer, " attenuation: 0 dB\n" ); |
1801 | break; |
1802 | case RME96_ATTENUATION_6: |
1803 | snd_iprintf(buffer, " attenuation: -6 dB\n" ); |
1804 | break; |
1805 | case RME96_ATTENUATION_12: |
1806 | snd_iprintf(buffer, " attenuation: -12 dB\n" ); |
1807 | break; |
1808 | case RME96_ATTENUATION_18: |
1809 | snd_iprintf(buffer, " attenuation: -18 dB\n" ); |
1810 | break; |
1811 | } |
1812 | snd_iprintf(buffer, " volume left: %u\n" , rme96->vol[0]); |
1813 | snd_iprintf(buffer, " volume right: %u\n" , rme96->vol[1]); |
1814 | } |
1815 | } |
1816 | |
1817 | static void snd_rme96_proc_init(struct rme96 *rme96) |
1818 | { |
1819 | snd_card_ro_proc_new(card: rme96->card, name: "rme96" , private_data: rme96, read: snd_rme96_proc_read); |
1820 | } |
1821 | |
1822 | /* |
1823 | * control interface |
1824 | */ |
1825 | |
1826 | #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info |
1827 | |
1828 | static int |
1829 | snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1830 | { |
1831 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1832 | |
1833 | spin_lock_irq(lock: &rme96->lock); |
1834 | ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; |
1835 | spin_unlock_irq(lock: &rme96->lock); |
1836 | return 0; |
1837 | } |
1838 | static int |
1839 | snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1840 | { |
1841 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1842 | unsigned int val; |
1843 | int change; |
1844 | |
1845 | val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; |
1846 | spin_lock_irq(lock: &rme96->lock); |
1847 | val = (rme96->wcreg & ~RME96_WCR_SEL) | val; |
1848 | change = val != rme96->wcreg; |
1849 | rme96->wcreg = val; |
1850 | writel(val, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
1851 | spin_unlock_irq(lock: &rme96->lock); |
1852 | return change; |
1853 | } |
1854 | |
1855 | static int |
1856 | snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1857 | { |
1858 | static const char * const _texts[5] = { |
1859 | "Optical" , "Coaxial" , "Internal" , "XLR" , "Analog" |
1860 | }; |
1861 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1862 | const char *texts[5] = { |
1863 | _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] |
1864 | }; |
1865 | int num_items; |
1866 | |
1867 | switch (rme96->pci->device) { |
1868 | case PCI_DEVICE_ID_RME_DIGI96: |
1869 | case PCI_DEVICE_ID_RME_DIGI96_8: |
1870 | num_items = 3; |
1871 | break; |
1872 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
1873 | num_items = 4; |
1874 | break; |
1875 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
1876 | if (rme96->rev > 4) { |
1877 | /* PST */ |
1878 | num_items = 4; |
1879 | texts[3] = _texts[4]; /* Analog instead of XLR */ |
1880 | } else { |
1881 | /* PAD */ |
1882 | num_items = 5; |
1883 | } |
1884 | break; |
1885 | default: |
1886 | snd_BUG(); |
1887 | return -EINVAL; |
1888 | } |
1889 | return snd_ctl_enum_info(info: uinfo, channels: 1, items: num_items, names: texts); |
1890 | } |
1891 | static int |
1892 | snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1893 | { |
1894 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1895 | unsigned int items = 3; |
1896 | |
1897 | spin_lock_irq(lock: &rme96->lock); |
1898 | ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); |
1899 | |
1900 | switch (rme96->pci->device) { |
1901 | case PCI_DEVICE_ID_RME_DIGI96: |
1902 | case PCI_DEVICE_ID_RME_DIGI96_8: |
1903 | items = 3; |
1904 | break; |
1905 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
1906 | items = 4; |
1907 | break; |
1908 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
1909 | if (rme96->rev > 4) { |
1910 | /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ |
1911 | if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { |
1912 | ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; |
1913 | } |
1914 | items = 4; |
1915 | } else { |
1916 | items = 5; |
1917 | } |
1918 | break; |
1919 | default: |
1920 | snd_BUG(); |
1921 | break; |
1922 | } |
1923 | if (ucontrol->value.enumerated.item[0] >= items) { |
1924 | ucontrol->value.enumerated.item[0] = items - 1; |
1925 | } |
1926 | |
1927 | spin_unlock_irq(lock: &rme96->lock); |
1928 | return 0; |
1929 | } |
1930 | static int |
1931 | snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1932 | { |
1933 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1934 | unsigned int val; |
1935 | int change, items = 3; |
1936 | |
1937 | switch (rme96->pci->device) { |
1938 | case PCI_DEVICE_ID_RME_DIGI96: |
1939 | case PCI_DEVICE_ID_RME_DIGI96_8: |
1940 | items = 3; |
1941 | break; |
1942 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
1943 | items = 4; |
1944 | break; |
1945 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
1946 | if (rme96->rev > 4) { |
1947 | items = 4; |
1948 | } else { |
1949 | items = 5; |
1950 | } |
1951 | break; |
1952 | default: |
1953 | snd_BUG(); |
1954 | break; |
1955 | } |
1956 | val = ucontrol->value.enumerated.item[0] % items; |
1957 | |
1958 | /* special case for PST */ |
1959 | if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { |
1960 | if (val == RME96_INPUT_XLR) { |
1961 | val = RME96_INPUT_ANALOG; |
1962 | } |
1963 | } |
1964 | |
1965 | spin_lock_irq(lock: &rme96->lock); |
1966 | change = (int)val != snd_rme96_getinputtype(rme96); |
1967 | snd_rme96_setinputtype(rme96, type: val); |
1968 | spin_unlock_irq(lock: &rme96->lock); |
1969 | return change; |
1970 | } |
1971 | |
1972 | static int |
1973 | snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1974 | { |
1975 | static const char * const texts[3] = { "AutoSync" , "Internal" , "Word" }; |
1976 | |
1977 | return snd_ctl_enum_info(info: uinfo, channels: 1, items: 3, names: texts); |
1978 | } |
1979 | static int |
1980 | snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1981 | { |
1982 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1983 | |
1984 | spin_lock_irq(lock: &rme96->lock); |
1985 | ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); |
1986 | spin_unlock_irq(lock: &rme96->lock); |
1987 | return 0; |
1988 | } |
1989 | static int |
1990 | snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1991 | { |
1992 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
1993 | unsigned int val; |
1994 | int change; |
1995 | |
1996 | val = ucontrol->value.enumerated.item[0] % 3; |
1997 | spin_lock_irq(lock: &rme96->lock); |
1998 | change = (int)val != snd_rme96_getclockmode(rme96); |
1999 | snd_rme96_setclockmode(rme96, mode: val); |
2000 | spin_unlock_irq(lock: &rme96->lock); |
2001 | return change; |
2002 | } |
2003 | |
2004 | static int |
2005 | snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
2006 | { |
2007 | static const char * const texts[4] = { |
2008 | "0 dB" , "-6 dB" , "-12 dB" , "-18 dB" |
2009 | }; |
2010 | |
2011 | return snd_ctl_enum_info(info: uinfo, channels: 1, items: 4, names: texts); |
2012 | } |
2013 | static int |
2014 | snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2015 | { |
2016 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2017 | |
2018 | spin_lock_irq(lock: &rme96->lock); |
2019 | ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); |
2020 | spin_unlock_irq(lock: &rme96->lock); |
2021 | return 0; |
2022 | } |
2023 | static int |
2024 | snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2025 | { |
2026 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2027 | unsigned int val; |
2028 | int change; |
2029 | |
2030 | val = ucontrol->value.enumerated.item[0] % 4; |
2031 | spin_lock_irq(lock: &rme96->lock); |
2032 | |
2033 | change = (int)val != snd_rme96_getattenuation(rme96); |
2034 | snd_rme96_setattenuation(rme96, attenuation: val); |
2035 | spin_unlock_irq(lock: &rme96->lock); |
2036 | return change; |
2037 | } |
2038 | |
2039 | static int |
2040 | snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
2041 | { |
2042 | static const char * const texts[4] = { "1+2" , "3+4" , "5+6" , "7+8" }; |
2043 | |
2044 | return snd_ctl_enum_info(info: uinfo, channels: 1, items: 4, names: texts); |
2045 | } |
2046 | static int |
2047 | snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2048 | { |
2049 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2050 | |
2051 | spin_lock_irq(lock: &rme96->lock); |
2052 | ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); |
2053 | spin_unlock_irq(lock: &rme96->lock); |
2054 | return 0; |
2055 | } |
2056 | static int |
2057 | snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2058 | { |
2059 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2060 | unsigned int val; |
2061 | int change; |
2062 | |
2063 | val = ucontrol->value.enumerated.item[0] % 4; |
2064 | spin_lock_irq(lock: &rme96->lock); |
2065 | change = (int)val != snd_rme96_getmontracks(rme96); |
2066 | snd_rme96_setmontracks(rme96, montracks: val); |
2067 | spin_unlock_irq(lock: &rme96->lock); |
2068 | return change; |
2069 | } |
2070 | |
2071 | static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) |
2072 | { |
2073 | u32 val = 0; |
2074 | val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; |
2075 | val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; |
2076 | if (val & RME96_WCR_PRO) |
2077 | val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; |
2078 | else |
2079 | val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; |
2080 | return val; |
2081 | } |
2082 | |
2083 | static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) |
2084 | { |
2085 | aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | |
2086 | ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); |
2087 | if (val & RME96_WCR_PRO) |
2088 | aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; |
2089 | else |
2090 | aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; |
2091 | } |
2092 | |
2093 | static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
2094 | { |
2095 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
2096 | uinfo->count = 1; |
2097 | return 0; |
2098 | } |
2099 | |
2100 | static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2101 | { |
2102 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2103 | |
2104 | snd_rme96_convert_to_aes(aes: &ucontrol->value.iec958, val: rme96->wcreg_spdif); |
2105 | return 0; |
2106 | } |
2107 | |
2108 | static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2109 | { |
2110 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2111 | int change; |
2112 | u32 val; |
2113 | |
2114 | val = snd_rme96_convert_from_aes(aes: &ucontrol->value.iec958); |
2115 | spin_lock_irq(lock: &rme96->lock); |
2116 | change = val != rme96->wcreg_spdif; |
2117 | rme96->wcreg_spdif = val; |
2118 | spin_unlock_irq(lock: &rme96->lock); |
2119 | return change; |
2120 | } |
2121 | |
2122 | static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
2123 | { |
2124 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
2125 | uinfo->count = 1; |
2126 | return 0; |
2127 | } |
2128 | |
2129 | static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2130 | { |
2131 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2132 | |
2133 | snd_rme96_convert_to_aes(aes: &ucontrol->value.iec958, val: rme96->wcreg_spdif_stream); |
2134 | return 0; |
2135 | } |
2136 | |
2137 | static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2138 | { |
2139 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2140 | int change; |
2141 | u32 val; |
2142 | |
2143 | val = snd_rme96_convert_from_aes(aes: &ucontrol->value.iec958); |
2144 | spin_lock_irq(lock: &rme96->lock); |
2145 | change = val != rme96->wcreg_spdif_stream; |
2146 | rme96->wcreg_spdif_stream = val; |
2147 | rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); |
2148 | rme96->wcreg |= val; |
2149 | writel(val: rme96->wcreg, addr: rme96->iobase + RME96_IO_CONTROL_REGISTER); |
2150 | spin_unlock_irq(lock: &rme96->lock); |
2151 | return change; |
2152 | } |
2153 | |
2154 | static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
2155 | { |
2156 | uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; |
2157 | uinfo->count = 1; |
2158 | return 0; |
2159 | } |
2160 | |
2161 | static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
2162 | { |
2163 | ucontrol->value.iec958.status[0] = kcontrol->private_value; |
2164 | return 0; |
2165 | } |
2166 | |
2167 | static int |
2168 | snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
2169 | { |
2170 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2171 | |
2172 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
2173 | uinfo->count = 2; |
2174 | uinfo->value.integer.min = 0; |
2175 | uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); |
2176 | return 0; |
2177 | } |
2178 | |
2179 | static int |
2180 | snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) |
2181 | { |
2182 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2183 | |
2184 | spin_lock_irq(lock: &rme96->lock); |
2185 | u->value.integer.value[0] = rme96->vol[0]; |
2186 | u->value.integer.value[1] = rme96->vol[1]; |
2187 | spin_unlock_irq(lock: &rme96->lock); |
2188 | |
2189 | return 0; |
2190 | } |
2191 | |
2192 | static int |
2193 | snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) |
2194 | { |
2195 | struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); |
2196 | int change = 0; |
2197 | unsigned int vol, maxvol; |
2198 | |
2199 | |
2200 | if (!RME96_HAS_ANALOG_OUT(rme96)) |
2201 | return -EINVAL; |
2202 | maxvol = RME96_185X_MAX_OUT(rme96); |
2203 | spin_lock_irq(lock: &rme96->lock); |
2204 | vol = u->value.integer.value[0]; |
2205 | if (vol != rme96->vol[0] && vol <= maxvol) { |
2206 | rme96->vol[0] = vol; |
2207 | change = 1; |
2208 | } |
2209 | vol = u->value.integer.value[1]; |
2210 | if (vol != rme96->vol[1] && vol <= maxvol) { |
2211 | rme96->vol[1] = vol; |
2212 | change = 1; |
2213 | } |
2214 | if (change) |
2215 | snd_rme96_apply_dac_volume(rme96); |
2216 | spin_unlock_irq(lock: &rme96->lock); |
2217 | |
2218 | return change; |
2219 | } |
2220 | |
2221 | static const struct snd_kcontrol_new snd_rme96_controls[] = { |
2222 | { |
2223 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
2224 | .name = SNDRV_CTL_NAME_IEC958("" ,PLAYBACK,DEFAULT), |
2225 | .info = snd_rme96_control_spdif_info, |
2226 | .get = snd_rme96_control_spdif_get, |
2227 | .put = snd_rme96_control_spdif_put |
2228 | }, |
2229 | { |
2230 | .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, |
2231 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
2232 | .name = SNDRV_CTL_NAME_IEC958("" ,PLAYBACK,PCM_STREAM), |
2233 | .info = snd_rme96_control_spdif_stream_info, |
2234 | .get = snd_rme96_control_spdif_stream_get, |
2235 | .put = snd_rme96_control_spdif_stream_put |
2236 | }, |
2237 | { |
2238 | .access = SNDRV_CTL_ELEM_ACCESS_READ, |
2239 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
2240 | .name = SNDRV_CTL_NAME_IEC958("" ,PLAYBACK,CON_MASK), |
2241 | .info = snd_rme96_control_spdif_mask_info, |
2242 | .get = snd_rme96_control_spdif_mask_get, |
2243 | .private_value = IEC958_AES0_NONAUDIO | |
2244 | IEC958_AES0_PROFESSIONAL | |
2245 | IEC958_AES0_CON_EMPHASIS |
2246 | }, |
2247 | { |
2248 | .access = SNDRV_CTL_ELEM_ACCESS_READ, |
2249 | .iface = SNDRV_CTL_ELEM_IFACE_PCM, |
2250 | .name = SNDRV_CTL_NAME_IEC958("" ,PLAYBACK,PRO_MASK), |
2251 | .info = snd_rme96_control_spdif_mask_info, |
2252 | .get = snd_rme96_control_spdif_mask_get, |
2253 | .private_value = IEC958_AES0_NONAUDIO | |
2254 | IEC958_AES0_PROFESSIONAL | |
2255 | IEC958_AES0_PRO_EMPHASIS |
2256 | }, |
2257 | { |
2258 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
2259 | .name = "Input Connector" , |
2260 | .info = snd_rme96_info_inputtype_control, |
2261 | .get = snd_rme96_get_inputtype_control, |
2262 | .put = snd_rme96_put_inputtype_control |
2263 | }, |
2264 | { |
2265 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
2266 | .name = "Loopback Input" , |
2267 | .info = snd_rme96_info_loopback_control, |
2268 | .get = snd_rme96_get_loopback_control, |
2269 | .put = snd_rme96_put_loopback_control |
2270 | }, |
2271 | { |
2272 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
2273 | .name = "Sample Clock Source" , |
2274 | .info = snd_rme96_info_clockmode_control, |
2275 | .get = snd_rme96_get_clockmode_control, |
2276 | .put = snd_rme96_put_clockmode_control |
2277 | }, |
2278 | { |
2279 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
2280 | .name = "Monitor Tracks" , |
2281 | .info = snd_rme96_info_montracks_control, |
2282 | .get = snd_rme96_get_montracks_control, |
2283 | .put = snd_rme96_put_montracks_control |
2284 | }, |
2285 | { |
2286 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
2287 | .name = "Attenuation" , |
2288 | .info = snd_rme96_info_attenuation_control, |
2289 | .get = snd_rme96_get_attenuation_control, |
2290 | .put = snd_rme96_put_attenuation_control |
2291 | }, |
2292 | { |
2293 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
2294 | .name = "DAC Playback Volume" , |
2295 | .info = snd_rme96_dac_volume_info, |
2296 | .get = snd_rme96_dac_volume_get, |
2297 | .put = snd_rme96_dac_volume_put |
2298 | } |
2299 | }; |
2300 | |
2301 | static int |
2302 | snd_rme96_create_switches(struct snd_card *card, |
2303 | struct rme96 *rme96) |
2304 | { |
2305 | int idx, err; |
2306 | struct snd_kcontrol *kctl; |
2307 | |
2308 | for (idx = 0; idx < 7; idx++) { |
2309 | kctl = snd_ctl_new1(kcontrolnew: &snd_rme96_controls[idx], private_data: rme96); |
2310 | err = snd_ctl_add(card, kcontrol: kctl); |
2311 | if (err < 0) |
2312 | return err; |
2313 | if (idx == 1) /* IEC958 (S/PDIF) Stream */ |
2314 | rme96->spdif_ctl = kctl; |
2315 | } |
2316 | |
2317 | if (RME96_HAS_ANALOG_OUT(rme96)) { |
2318 | for (idx = 7; idx < 10; idx++) { |
2319 | err = snd_ctl_add(card, kcontrol: snd_ctl_new1(kcontrolnew: &snd_rme96_controls[idx], private_data: rme96)); |
2320 | if (err < 0) |
2321 | return err; |
2322 | } |
2323 | } |
2324 | |
2325 | return 0; |
2326 | } |
2327 | |
2328 | /* |
2329 | * Card initialisation |
2330 | */ |
2331 | |
2332 | #ifdef CONFIG_PM_SLEEP |
2333 | |
2334 | static int rme96_suspend(struct device *dev) |
2335 | { |
2336 | struct snd_card *card = dev_get_drvdata(dev); |
2337 | struct rme96 *rme96 = card->private_data; |
2338 | |
2339 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
2340 | |
2341 | /* save capture & playback pointers */ |
2342 | rme96->playback_pointer = readl(addr: rme96->iobase + RME96_IO_GET_PLAY_POS) |
2343 | & RME96_RCR_AUDIO_ADDR_MASK; |
2344 | rme96->capture_pointer = readl(addr: rme96->iobase + RME96_IO_GET_REC_POS) |
2345 | & RME96_RCR_AUDIO_ADDR_MASK; |
2346 | |
2347 | /* save playback and capture buffers */ |
2348 | memcpy_fromio(rme96->playback_suspend_buffer, |
2349 | rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); |
2350 | memcpy_fromio(rme96->capture_suspend_buffer, |
2351 | rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); |
2352 | |
2353 | /* disable the DAC */ |
2354 | rme96->areg &= ~RME96_AR_DAC_EN; |
2355 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
2356 | return 0; |
2357 | } |
2358 | |
2359 | static int rme96_resume(struct device *dev) |
2360 | { |
2361 | struct snd_card *card = dev_get_drvdata(dev); |
2362 | struct rme96 *rme96 = card->private_data; |
2363 | |
2364 | /* reset playback and record buffer pointers */ |
2365 | writel(val: 0, addr: rme96->iobase + RME96_IO_SET_PLAY_POS |
2366 | + rme96->playback_pointer); |
2367 | writel(val: 0, addr: rme96->iobase + RME96_IO_SET_REC_POS |
2368 | + rme96->capture_pointer); |
2369 | |
2370 | /* restore playback and capture buffers */ |
2371 | memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, |
2372 | rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); |
2373 | memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, |
2374 | rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); |
2375 | |
2376 | /* reset the ADC */ |
2377 | writel(val: rme96->areg | RME96_AR_PD2, |
2378 | addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
2379 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
2380 | |
2381 | /* reset and enable DAC, restore analog volume */ |
2382 | snd_rme96_reset_dac(rme96); |
2383 | rme96->areg |= RME96_AR_DAC_EN; |
2384 | writel(val: rme96->areg, addr: rme96->iobase + RME96_IO_ADDITIONAL_REG); |
2385 | if (RME96_HAS_ANALOG_OUT(rme96)) { |
2386 | usleep_range(min: 3000, max: 10000); |
2387 | snd_rme96_apply_dac_volume(rme96); |
2388 | } |
2389 | |
2390 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
2391 | |
2392 | return 0; |
2393 | } |
2394 | |
2395 | static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume); |
2396 | #define RME96_PM_OPS &rme96_pm |
2397 | #else |
2398 | #define RME96_PM_OPS NULL |
2399 | #endif /* CONFIG_PM_SLEEP */ |
2400 | |
2401 | static void snd_rme96_card_free(struct snd_card *card) |
2402 | { |
2403 | snd_rme96_free(rme96: card->private_data); |
2404 | } |
2405 | |
2406 | static int |
2407 | __snd_rme96_probe(struct pci_dev *pci, |
2408 | const struct pci_device_id *pci_id) |
2409 | { |
2410 | static int dev; |
2411 | struct rme96 *rme96; |
2412 | struct snd_card *card; |
2413 | int err; |
2414 | u8 val; |
2415 | |
2416 | if (dev >= SNDRV_CARDS) { |
2417 | return -ENODEV; |
2418 | } |
2419 | if (!enable[dev]) { |
2420 | dev++; |
2421 | return -ENOENT; |
2422 | } |
2423 | err = snd_devm_card_new(parent: &pci->dev, idx: index[dev], xid: id[dev], THIS_MODULE, |
2424 | extra_size: sizeof(*rme96), card_ret: &card); |
2425 | if (err < 0) |
2426 | return err; |
2427 | card->private_free = snd_rme96_card_free; |
2428 | rme96 = card->private_data; |
2429 | rme96->card = card; |
2430 | rme96->pci = pci; |
2431 | err = snd_rme96_create(rme96); |
2432 | if (err) |
2433 | return err; |
2434 | |
2435 | #ifdef CONFIG_PM_SLEEP |
2436 | rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); |
2437 | if (!rme96->playback_suspend_buffer) |
2438 | return -ENOMEM; |
2439 | rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); |
2440 | if (!rme96->capture_suspend_buffer) |
2441 | return -ENOMEM; |
2442 | #endif |
2443 | |
2444 | strcpy(p: card->driver, q: "Digi96" ); |
2445 | switch (rme96->pci->device) { |
2446 | case PCI_DEVICE_ID_RME_DIGI96: |
2447 | strcpy(p: card->shortname, q: "RME Digi96" ); |
2448 | break; |
2449 | case PCI_DEVICE_ID_RME_DIGI96_8: |
2450 | strcpy(p: card->shortname, q: "RME Digi96/8" ); |
2451 | break; |
2452 | case PCI_DEVICE_ID_RME_DIGI96_8_PRO: |
2453 | strcpy(p: card->shortname, q: "RME Digi96/8 PRO" ); |
2454 | break; |
2455 | case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: |
2456 | pci_read_config_byte(dev: rme96->pci, where: 8, val: &val); |
2457 | if (val < 5) { |
2458 | strcpy(p: card->shortname, q: "RME Digi96/8 PAD" ); |
2459 | } else { |
2460 | strcpy(p: card->shortname, q: "RME Digi96/8 PST" ); |
2461 | } |
2462 | break; |
2463 | } |
2464 | sprintf(buf: card->longname, fmt: "%s at 0x%lx, irq %d" , card->shortname, |
2465 | rme96->port, rme96->irq); |
2466 | err = snd_card_register(card); |
2467 | if (err) |
2468 | return err; |
2469 | |
2470 | pci_set_drvdata(pdev: pci, data: card); |
2471 | dev++; |
2472 | return 0; |
2473 | } |
2474 | |
2475 | static int snd_rme96_probe(struct pci_dev *pci, |
2476 | const struct pci_device_id *pci_id) |
2477 | { |
2478 | return snd_card_free_on_error(dev: &pci->dev, ret: __snd_rme96_probe(pci, pci_id)); |
2479 | } |
2480 | |
2481 | static struct pci_driver rme96_driver = { |
2482 | .name = KBUILD_MODNAME, |
2483 | .id_table = snd_rme96_ids, |
2484 | .probe = snd_rme96_probe, |
2485 | .driver = { |
2486 | .pm = RME96_PM_OPS, |
2487 | }, |
2488 | }; |
2489 | |
2490 | module_pci_driver(rme96_driver); |
2491 | |