| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | #ifndef __sis7019_h__ |
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| 3 | #define __sis7019_h__ |
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| 4 | |
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| 5 | /* |
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| 6 | * Definitions for SiS7019 Audio Accelerator |
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| 7 | * |
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| 8 | * Copyright (C) 2004-2007, David Dillow |
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| 9 | * Written by David Dillow <dave@thedillows.org> |
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| 10 | * Inspired by the Trident 4D-WaveDX/NX driver. |
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| 11 | * |
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| 12 | * All rights reserved. |
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| 13 | */ |
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| 14 | |
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| 15 | |
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| 16 | /* General Control Register */ |
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| 17 | #define SIS_GCR 0x00 |
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| 18 | #define SIS_GCR_MACRO_POWER_DOWN 0x80000000 |
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| 19 | #define SIS_GCR_MODEM_ENABLE 0x00010000 |
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| 20 | #define SIS_GCR_SOFTWARE_RESET 0x00000001 |
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| 21 | |
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| 22 | /* General Interrupt Enable Register */ |
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| 23 | #define SIS_GIER 0x04 |
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| 24 | #define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000 |
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| 25 | #define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000 |
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| 26 | #define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000 |
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| 27 | #define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000 |
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| 28 | #define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000 |
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| 29 | #define SIS_GIER_AC97_SAMPLE_TIMER_IRQ_ENABLE 0x00000010 |
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| 30 | #define SIS_GIER_AUDIO_GLOBAL_TIMER_IRQ_ENABLE 0x00000008 |
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| 31 | #define SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE 0x00000004 |
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| 32 | #define SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE 0x00000002 |
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| 33 | #define SIS_GIER_AUDIO_WAVE_ENGINE_IRQ_ENABLE 0x00000001 |
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| 34 | |
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| 35 | /* General Interrupt Status Register */ |
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| 36 | #define SIS_GISR 0x08 |
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| 37 | #define SIS_GISR_MODEM_TIMER_IRQ_STATUS 0x00100000 |
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| 38 | #define SIS_GISR_MODEM_RX_DMA_IRQ_STATUS 0x00080000 |
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| 39 | #define SIS_GISR_MODEM_TX_DMA_IRQ_STATUS 0x00040000 |
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| 40 | #define SIS_GISR_AC97_GPIO1_IRQ_STATUS 0x00020000 |
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| 41 | #define SIS_GISR_AC97_GPIO0_IRQ_STATUS 0x00010000 |
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| 42 | #define SIS_GISR_AC97_SAMPLE_TIMER_IRQ_STATUS 0x00000010 |
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| 43 | #define SIS_GISR_AUDIO_GLOBAL_TIMER_IRQ_STATUS 0x00000008 |
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| 44 | #define SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS 0x00000004 |
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| 45 | #define SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS 0x00000002 |
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| 46 | #define SIS_GISR_AUDIO_WAVE_ENGINE_IRQ_STATUS 0x00000001 |
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| 47 | |
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| 48 | /* DMA Control Register */ |
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| 49 | #define SIS_DMA_CSR 0x10 |
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| 50 | #define SIS_DMA_CSR_PCI_SETTINGS 0x0000001d |
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| 51 | #define SIS_DMA_CSR_CONCURRENT_ENABLE 0x00000200 |
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| 52 | #define SIS_DMA_CSR_PIPELINE_ENABLE 0x00000100 |
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| 53 | #define SIS_DMA_CSR_RX_DRAIN_ENABLE 0x00000010 |
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| 54 | #define SIS_DMA_CSR_RX_FILL_ENABLE 0x00000008 |
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| 55 | #define SIS_DMA_CSR_TX_DRAIN_ENABLE 0x00000004 |
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| 56 | #define SIS_DMA_CSR_TX_LOWPRI_FILL_ENABLE 0x00000002 |
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| 57 | #define SIS_DMA_CSR_TX_HIPRI_FILL_ENABLE 0x00000001 |
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| 58 | |
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| 59 | /* Playback Channel Start Registers */ |
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| 60 | #define SIS_PLAY_START_A_REG 0x14 |
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| 61 | #define SIS_PLAY_START_B_REG 0x18 |
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| 62 | |
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| 63 | /* Playback Channel Stop Registers */ |
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| 64 | #define SIS_PLAY_STOP_A_REG 0x1c |
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| 65 | #define SIS_PLAY_STOP_B_REG 0x20 |
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| 66 | |
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| 67 | /* Recording Channel Start Register */ |
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| 68 | #define SIS_RECORD_START_REG 0x24 |
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| 69 | |
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| 70 | /* Recording Channel Stop Register */ |
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| 71 | #define SIS_RECORD_STOP_REG 0x28 |
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| 72 | |
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| 73 | /* Playback Interrupt Status Registers */ |
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| 74 | #define SIS_PISR_A 0x2c |
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| 75 | #define SIS_PISR_B 0x30 |
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| 76 | |
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| 77 | /* Recording Interrupt Status Register */ |
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| 78 | #define SIS_RISR 0x34 |
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| 79 | |
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| 80 | /* AC97 AC-link Playback Source Register */ |
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| 81 | #define SIS_AC97_PSR 0x40 |
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| 82 | #define SIS_AC97_PSR_MODEM_HEADSET_SRC_MIXER 0x0f000000 |
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| 83 | #define SIS_AC97_PSR_MODEM_LINE2_SRC_MIXER 0x00f00000 |
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| 84 | #define SIS_AC97_PSR_MODEM_LINE1_SRC_MIXER 0x000f0000 |
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| 85 | #define SIS_AC97_PSR_PCM_LFR_SRC_MIXER 0x0000f000 |
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| 86 | #define SIS_AC97_PSR_PCM_SURROUND_SRC_MIXER 0x00000f00 |
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| 87 | #define SIS_AC97_PSR_PCM_CENTER_SRC_MIXER 0x000000f0 |
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| 88 | #define SIS_AC97_PSR_PCM_LR_SRC_MIXER 0x0000000f |
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| 89 | |
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| 90 | /* AC97 AC-link Command Register */ |
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| 91 | #define SIS_AC97_CMD 0x50 |
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| 92 | #define SIS_AC97_CMD_DATA_MASK 0xffff0000 |
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| 93 | #define SIS_AC97_CMD_REG_MASK 0x0000ff00 |
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| 94 | #define SIS_AC97_CMD_CODEC3_READ 0x0000000d |
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| 95 | #define SIS_AC97_CMD_CODEC3_WRITE 0x0000000c |
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| 96 | #define SIS_AC97_CMD_CODEC2_READ 0x0000000b |
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| 97 | #define SIS_AC97_CMD_CODEC2_WRITE 0x0000000a |
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| 98 | #define SIS_AC97_CMD_CODEC_READ 0x00000009 |
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| 99 | #define SIS_AC97_CMD_CODEC_WRITE 0x00000008 |
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| 100 | #define SIS_AC97_CMD_CODEC_WARM_RESET 0x00000005 |
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| 101 | #define SIS_AC97_CMD_CODEC_COLD_RESET 0x00000004 |
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| 102 | #define SIS_AC97_CMD_DONE 0x00000000 |
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| 103 | |
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| 104 | /* AC97 AC-link Semaphore Register */ |
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| 105 | #define SIS_AC97_SEMA 0x54 |
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| 106 | #define SIS_AC97_SEMA_BUSY 0x00000001 |
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| 107 | #define SIS_AC97_SEMA_RELEASE 0x00000000 |
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| 108 | |
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| 109 | /* AC97 AC-link Status Register */ |
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| 110 | #define SIS_AC97_STATUS 0x58 |
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| 111 | #define SIS_AC97_STATUS_AUDIO_D2_INACT_SECS 0x03f00000 |
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| 112 | #define SIS_AC97_STATUS_MODEM_ALIVE 0x00002000 |
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| 113 | #define SIS_AC97_STATUS_AUDIO_ALIVE 0x00001000 |
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| 114 | #define SIS_AC97_STATUS_CODEC3_READY 0x00000400 |
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| 115 | #define SIS_AC97_STATUS_CODEC2_READY 0x00000200 |
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| 116 | #define SIS_AC97_STATUS_CODEC_READY 0x00000100 |
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| 117 | #define SIS_AC97_STATUS_WARM_RESET 0x00000080 |
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| 118 | #define SIS_AC97_STATUS_COLD_RESET 0x00000040 |
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| 119 | #define SIS_AC97_STATUS_POWERED_DOWN 0x00000020 |
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| 120 | #define SIS_AC97_STATUS_NORMAL 0x00000010 |
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| 121 | #define SIS_AC97_STATUS_READ_EXPIRED 0x00000004 |
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| 122 | #define SIS_AC97_STATUS_SEMAPHORE 0x00000002 |
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| 123 | #define SIS_AC97_STATUS_BUSY 0x00000001 |
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| 124 | |
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| 125 | /* AC97 AC-link Audio Configuration Register */ |
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| 126 | #define SIS_AC97_CONF 0x5c |
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| 127 | #define SIS_AC97_CONF_AUDIO_ALIVE 0x80000000 |
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| 128 | #define SIS_AC97_CONF_WARM_RESET_ENABLE 0x40000000 |
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| 129 | #define SIS_AC97_CONF_PR6_ENABLE 0x20000000 |
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| 130 | #define SIS_AC97_CONF_PR5_ENABLE 0x10000000 |
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| 131 | #define SIS_AC97_CONF_PR4_ENABLE 0x08000000 |
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| 132 | #define SIS_AC97_CONF_PR3_ENABLE 0x04000000 |
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| 133 | #define SIS_AC97_CONF_PR2_PR7_ENABLE 0x02000000 |
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| 134 | #define SIS_AC97_CONF_PR0_PR1_ENABLE 0x01000000 |
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| 135 | #define SIS_AC97_CONF_AUTO_PM_ENABLE 0x00800000 |
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| 136 | #define SIS_AC97_CONF_PCM_LFE_ENABLE 0x00080000 |
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| 137 | #define SIS_AC97_CONF_PCM_SURROUND_ENABLE 0x00040000 |
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| 138 | #define SIS_AC97_CONF_PCM_CENTER_ENABLE 0x00020000 |
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| 139 | #define SIS_AC97_CONF_PCM_LR_ENABLE 0x00010000 |
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| 140 | #define SIS_AC97_CONF_PCM_CAP_MIC_ENABLE 0x00002000 |
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| 141 | #define SIS_AC97_CONF_PCM_CAP_LR_ENABLE 0x00001000 |
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| 142 | #define SIS_AC97_CONF_PCM_CAP_MIC_FROM_CODEC3 0x00000200 |
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| 143 | #define SIS_AC97_CONF_PCM_CAP_LR_FROM_CODEC3 0x00000100 |
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| 144 | #define SIS_AC97_CONF_CODEC3_PM_VRM 0x00000080 |
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| 145 | #define SIS_AC97_CONF_CODEC_PM_VRM 0x00000040 |
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| 146 | #define SIS_AC97_CONF_CODEC3_VRA_ENABLE 0x00000020 |
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| 147 | #define SIS_AC97_CONF_CODEC_VRA_ENABLE 0x00000010 |
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| 148 | #define SIS_AC97_CONF_CODEC3_PM_EAC 0x00000008 |
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| 149 | #define SIS_AC97_CONF_CODEC_PM_EAC 0x00000004 |
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| 150 | #define SIS_AC97_CONF_CODEC3_EXISTS 0x00000002 |
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| 151 | #define SIS_AC97_CONF_CODEC_EXISTS 0x00000001 |
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| 152 | |
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| 153 | /* Playback Channel Sync Group registers */ |
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| 154 | #define SIS_PLAY_SYNC_GROUP_A 0x80 |
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| 155 | #define SIS_PLAY_SYNC_GROUP_B 0x84 |
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| 156 | #define SIS_PLAY_SYNC_GROUP_C 0x88 |
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| 157 | #define SIS_PLAY_SYNC_GROUP_D 0x8c |
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| 158 | #define SIS_MIXER_SYNC_GROUP 0x90 |
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| 159 | |
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| 160 | /* Wave Engine Config and Control Register */ |
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| 161 | #define SIS_WECCR 0xa0 |
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| 162 | #define SIS_WECCR_TESTMODE_MASK 0x00300000 |
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| 163 | #define SIS_WECCR_TESTMODE_NORMAL 0x00000000 |
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| 164 | #define SIS_WECCR_TESTMODE_BYPASS_NSO_ALPHA 0x00100000 |
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| 165 | #define SIS_WECCR_TESTMODE_BYPASS_FC 0x00200000 |
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| 166 | #define SIS_WECCR_TESTMODE_BYPASS_WOL 0x00300000 |
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| 167 | #define SIS_WECCR_RESONANCE_DELAY_MASK 0x00060000 |
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| 168 | #define SIS_WECCR_RESONANCE_DELAY_NONE 0x00000000 |
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| 169 | #define SIS_WECCR_RESONANCE_DELAY_FC_1F00 0x00020000 |
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| 170 | #define SIS_WECCR_RESONANCE_DELAY_FC_1E00 0x00040000 |
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| 171 | #define SIS_WECCR_RESONANCE_DELAY_FC_1C00 0x00060000 |
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| 172 | #define SIS_WECCR_IGNORE_CHANNEL_PARMS 0x00010000 |
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| 173 | #define SIS_WECCR_COMMAND_CHANNEL_ID_MASK 0x0003ff00 |
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| 174 | #define SIS_WECCR_COMMAND_MASK 0x00000007 |
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| 175 | #define SIS_WECCR_COMMAND_NONE 0x00000000 |
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| 176 | #define SIS_WECCR_COMMAND_DONE 0x00000000 |
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| 177 | #define SIS_WECCR_COMMAND_PAUSE 0x00000001 |
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| 178 | #define SIS_WECCR_COMMAND_TOGGLE_VEG 0x00000002 |
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| 179 | #define SIS_WECCR_COMMAND_TOGGLE_MEG 0x00000003 |
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| 180 | #define SIS_WECCR_COMMAND_TOGGLE_VEG_MEG 0x00000004 |
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| 181 | |
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| 182 | /* Wave Engine Volume Control Register */ |
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| 183 | #define SIS_WEVCR 0xa4 |
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| 184 | #define SIS_WEVCR_LEFT_MUSIC_ATTENUATION_MASK 0xff000000 |
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| 185 | #define SIS_WEVCR_RIGHT_MUSIC_ATTENUATION_MASK 0x00ff0000 |
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| 186 | #define SIS_WEVCR_LEFT_WAVE_ATTENUATION_MASK 0x0000ff00 |
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| 187 | #define SIS_WEVCR_RIGHT_WAVE_ATTENUATION_MASK 0x000000ff |
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| 188 | |
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| 189 | /* Wave Engine Interrupt Status Registers */ |
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| 190 | #define SIS_WEISR_A 0xa8 |
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| 191 | #define SIS_WEISR_B 0xac |
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| 192 | |
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| 193 | |
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| 194 | /* Playback DMA parameters (parameter RAM) */ |
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| 195 | #define SIS_PLAY_DMA_OFFSET 0x0000 |
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| 196 | #define SIS_PLAY_DMA_SIZE 0x10 |
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| 197 | #define SIS_PLAY_DMA_ADDR(addr, num) \ |
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| 198 | ((num * SIS_PLAY_DMA_SIZE) + (addr) + SIS_PLAY_DMA_OFFSET) |
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| 199 | |
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| 200 | #define SIS_PLAY_DMA_FORMAT_CSO 0x00 |
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| 201 | #define SIS_PLAY_DMA_FORMAT_UNSIGNED 0x00080000 |
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| 202 | #define SIS_PLAY_DMA_FORMAT_8BIT 0x00040000 |
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| 203 | #define SIS_PLAY_DMA_FORMAT_MONO 0x00020000 |
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| 204 | #define SIS_PLAY_DMA_CSO_MASK 0x0000ffff |
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| 205 | #define SIS_PLAY_DMA_BASE 0x04 |
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| 206 | #define SIS_PLAY_DMA_CONTROL 0x08 |
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| 207 | #define SIS_PLAY_DMA_STOP_AT_SSO 0x04000000 |
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| 208 | #define SIS_PLAY_DMA_RELEASE 0x02000000 |
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| 209 | #define SIS_PLAY_DMA_LOOP 0x01000000 |
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| 210 | #define SIS_PLAY_DMA_INTR_AT_SSO 0x00080000 |
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| 211 | #define SIS_PLAY_DMA_INTR_AT_ESO 0x00040000 |
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| 212 | #define SIS_PLAY_DMA_INTR_AT_LEO 0x00020000 |
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| 213 | #define SIS_PLAY_DMA_INTR_AT_MLP 0x00010000 |
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| 214 | #define SIS_PLAY_DMA_LEO_MASK 0x0000ffff |
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| 215 | #define SIS_PLAY_DMA_SSO_ESO 0x0c |
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| 216 | #define SIS_PLAY_DMA_SSO_MASK 0xffff0000 |
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| 217 | #define SIS_PLAY_DMA_ESO_MASK 0x0000ffff |
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| 218 | |
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| 219 | /* Capture DMA parameters (parameter RAM) */ |
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| 220 | #define SIS_CAPTURE_DMA_OFFSET 0x0800 |
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| 221 | #define SIS_CAPTURE_DMA_SIZE 0x10 |
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| 222 | #define SIS_CAPTURE_DMA_ADDR(addr, num) \ |
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| 223 | ((num * SIS_CAPTURE_DMA_SIZE) + (addr) + SIS_CAPTURE_DMA_OFFSET) |
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| 224 | |
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| 225 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_0 0 |
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| 226 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_1 1 |
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| 227 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_2 2 |
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| 228 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_3 3 |
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| 229 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_4 4 |
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| 230 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_5 5 |
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| 231 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_6 6 |
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| 232 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_7 7 |
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| 233 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_8 8 |
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| 234 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_9 9 |
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| 235 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_10 10 |
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| 236 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_11 11 |
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| 237 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_12 12 |
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| 238 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_13 13 |
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| 239 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_14 14 |
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| 240 | #define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_15 15 |
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| 241 | #define SIS_CAPTURE_CHAN_AC97_PCM_IN 16 |
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| 242 | #define SIS_CAPTURE_CHAN_AC97_MIC_IN 17 |
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| 243 | #define SIS_CAPTURE_CHAN_AC97_LINE1_IN 18 |
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| 244 | #define SIS_CAPTURE_CHAN_AC97_LINE2_IN 19 |
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| 245 | #define SIS_CAPTURE_CHAN_AC97_HANDSE_IN 20 |
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| 246 | |
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| 247 | #define SIS_CAPTURE_DMA_FORMAT_CSO 0x00 |
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| 248 | #define SIS_CAPTURE_DMA_MONO_MODE_MASK 0xc0000000 |
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| 249 | #define SIS_CAPTURE_DMA_MONO_MODE_AVG 0x00000000 |
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| 250 | #define SIS_CAPTURE_DMA_MONO_MODE_LEFT 0x40000000 |
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| 251 | #define SIS_CAPTURE_DMA_MONO_MODE_RIGHT 0x80000000 |
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| 252 | #define SIS_CAPTURE_DMA_FORMAT_UNSIGNED 0x00080000 |
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| 253 | #define SIS_CAPTURE_DMA_FORMAT_8BIT 0x00040000 |
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| 254 | #define SIS_CAPTURE_DMA_FORMAT_MONO 0x00020000 |
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| 255 | #define SIS_CAPTURE_DMA_CSO_MASK 0x0000ffff |
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| 256 | #define SIS_CAPTURE_DMA_BASE 0x04 |
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| 257 | #define SIS_CAPTURE_DMA_CONTROL 0x08 |
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| 258 | #define SIS_CAPTURE_DMA_STOP_AT_SSO 0x04000000 |
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| 259 | #define SIS_CAPTURE_DMA_RELEASE 0x02000000 |
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| 260 | #define SIS_CAPTURE_DMA_LOOP 0x01000000 |
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| 261 | #define SIS_CAPTURE_DMA_INTR_AT_LEO 0x00020000 |
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| 262 | #define SIS_CAPTURE_DMA_INTR_AT_MLP 0x00010000 |
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| 263 | #define SIS_CAPTURE_DMA_LEO_MASK 0x0000ffff |
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| 264 | #define SIS_CAPTURE_DMA_RESERVED 0x0c |
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| 265 | |
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| 266 | |
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| 267 | /* Mixer routing list start pointer (parameter RAM) */ |
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| 268 | #define SIS_MIXER_START_OFFSET 0x1000 |
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| 269 | #define SIS_MIXER_START_SIZE 0x04 |
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| 270 | #define SIS_MIXER_START_ADDR(addr, num) \ |
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| 271 | ((num * SIS_MIXER_START_SIZE) + (addr) + SIS_MIXER_START_OFFSET) |
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| 272 | |
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| 273 | #define SIS_MIXER_START_MASK 0x0000007f |
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| 274 | |
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| 275 | /* Mixer routing table (parameter RAM) */ |
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| 276 | #define SIS_MIXER_OFFSET 0x1400 |
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| 277 | #define SIS_MIXER_SIZE 0x04 |
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| 278 | #define SIS_MIXER_ADDR(addr, num) \ |
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| 279 | ((num * SIS_MIXER_SIZE) + (addr) + SIS_MIXER_OFFSET) |
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| 280 | |
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| 281 | #define SIS_MIXER_RIGHT_ATTENUTATION_MASK 0xff000000 |
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| 282 | #define SIS_MIXER_RIGHT_NO_ATTEN 0xff000000 |
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| 283 | #define SIS_MIXER_LEFT_ATTENUTATION_MASK 0x00ff0000 |
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| 284 | #define SIS_MIXER_LEFT_NO_ATTEN 0x00ff0000 |
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| 285 | #define SIS_MIXER_NEXT_ENTRY_MASK 0x00007f00 |
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| 286 | #define SIS_MIXER_NEXT_ENTRY_NONE 0x00000000 |
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| 287 | #define SIS_MIXER_DEST_MASK 0x0000007f |
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| 288 | #define SIS_MIXER_DEST_0 0x00000020 |
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| 289 | #define SIS_MIXER_DEST_1 0x00000021 |
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| 290 | #define SIS_MIXER_DEST_2 0x00000022 |
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| 291 | #define SIS_MIXER_DEST_3 0x00000023 |
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| 292 | #define SIS_MIXER_DEST_4 0x00000024 |
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| 293 | #define SIS_MIXER_DEST_5 0x00000025 |
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| 294 | #define SIS_MIXER_DEST_6 0x00000026 |
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| 295 | #define SIS_MIXER_DEST_7 0x00000027 |
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| 296 | #define SIS_MIXER_DEST_8 0x00000028 |
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| 297 | #define SIS_MIXER_DEST_9 0x00000029 |
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| 298 | #define SIS_MIXER_DEST_10 0x0000002a |
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| 299 | #define SIS_MIXER_DEST_11 0x0000002b |
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| 300 | #define SIS_MIXER_DEST_12 0x0000002c |
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| 301 | #define SIS_MIXER_DEST_13 0x0000002d |
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| 302 | #define SIS_MIXER_DEST_14 0x0000002e |
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| 303 | #define SIS_MIXER_DEST_15 0x0000002f |
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| 304 | |
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| 305 | /* Wave Engine Control Parameters (parameter RAM) */ |
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| 306 | #define SIS_WAVE_OFFSET 0x2000 |
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| 307 | #define SIS_WAVE_SIZE 0x40 |
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| 308 | #define SIS_WAVE_ADDR(addr, num) \ |
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| 309 | ((num * SIS_WAVE_SIZE) + (addr) + SIS_WAVE_OFFSET) |
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| 310 | |
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| 311 | #define SIS_WAVE_GENERAL 0x00 |
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| 312 | #define SIS_WAVE_GENERAL_WAVE_VOLUME 0x80000000 |
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| 313 | #define SIS_WAVE_GENERAL_MUSIC_VOLUME 0x00000000 |
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| 314 | #define SIS_WAVE_GENERAL_VOLUME_MASK 0x7f000000 |
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| 315 | #define SIS_WAVE_GENERAL_ARTICULATION 0x04 |
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| 316 | #define SIS_WAVE_GENERAL_ARTICULATION_DELTA_MASK 0x3fff0000 |
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| 317 | #define SIS_WAVE_ARTICULATION 0x08 |
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| 318 | #define SIS_WAVE_TIMER 0x0c |
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| 319 | #define SIS_WAVE_GENERATOR 0x10 |
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| 320 | #define SIS_WAVE_CHANNEL_CONTROL 0x14 |
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| 321 | #define SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE 0x80000000 |
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| 322 | #define SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE 0x40000000 |
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| 323 | #define SIS_WAVE_CHANNEL_CONTROL_FILTER_ENABLE 0x20000000 |
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| 324 | #define SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE 0x10000000 |
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| 325 | #define SIS_WAVE_LFO_EG_CONTROL 0x18 |
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| 326 | #define SIS_WAVE_LFO_EG_CONTROL_2 0x1c |
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| 327 | #define SIS_WAVE_LFO_EG_CONTROL_3 0x20 |
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| 328 | #define SIS_WAVE_LFO_EG_CONTROL_4 0x24 |
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| 329 | |
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| 330 | #endif /* __sis7019_h__ */ |
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| 331 | |
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