1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Driver for AMD7930 sound chips found on Sparcs. |
4 | * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net> |
5 | * |
6 | * Based entirely upon drivers/sbus/audio/amd7930.c which is: |
7 | * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu) |
8 | * |
9 | * --- Notes from Thomas's original driver --- |
10 | * This is the lowlevel driver for the AMD7930 audio chip found on all |
11 | * sun4c machines and some sun4m machines. |
12 | * |
13 | * The amd7930 is actually an ISDN chip which has a very simple |
14 | * integrated audio encoder/decoder. When Sun decided on what chip to |
15 | * use for audio, they had the brilliant idea of using the amd7930 and |
16 | * only connecting the audio encoder/decoder pins. |
17 | * |
18 | * Thanks to the AMD engineer who was able to get us the AMD79C30 |
19 | * databook which has all the programming information and gain tables. |
20 | * |
21 | * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the |
22 | * SparcStation 1+. The chip provides microphone and speaker interfaces |
23 | * which provide mono-channel audio at 8K samples per second via either |
24 | * 8-bit A-law or 8-bit mu-law encoding. Also, the chip features an |
25 | * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface, |
26 | * which performs basic D channel LAPD processing and provides raw |
27 | * B channel data. The digital audio channel, the two ISDN B channels, |
28 | * and two 64 Kbps channels to the microprocessor are all interconnected |
29 | * via a multiplexer. |
30 | * --- End of notes from Thoamas's original driver --- |
31 | */ |
32 | |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> |
35 | #include <linux/slab.h> |
36 | #include <linux/init.h> |
37 | #include <linux/interrupt.h> |
38 | #include <linux/moduleparam.h> |
39 | #include <linux/of.h> |
40 | #include <linux/platform_device.h> |
41 | #include <linux/io.h> |
42 | |
43 | #include <sound/core.h> |
44 | #include <sound/pcm.h> |
45 | #include <sound/info.h> |
46 | #include <sound/control.h> |
47 | #include <sound/initval.h> |
48 | |
49 | #include <asm/irq.h> |
50 | |
51 | static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ |
52 | static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
53 | static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ |
54 | |
55 | module_param_array(index, int, NULL, 0444); |
56 | MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard." ); |
57 | module_param_array(id, charp, NULL, 0444); |
58 | MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard." ); |
59 | module_param_array(enable, bool, NULL, 0444); |
60 | MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard." ); |
61 | MODULE_AUTHOR("Thomas K. Dyas and David S. Miller" ); |
62 | MODULE_DESCRIPTION("Sun AMD7930" ); |
63 | MODULE_LICENSE("GPL" ); |
64 | |
65 | /* Device register layout. */ |
66 | |
67 | /* Register interface presented to the CPU by the amd7930. */ |
68 | #define AMD7930_CR 0x00UL /* Command Register (W) */ |
69 | #define AMD7930_IR AMD7930_CR /* Interrupt Register (R) */ |
70 | #define AMD7930_DR 0x01UL /* Data Register (R/W) */ |
71 | #define AMD7930_DSR1 0x02UL /* D-channel Status Register 1 (R) */ |
72 | #define AMD7930_DER 0x03UL /* D-channel Error Register (R) */ |
73 | #define AMD7930_DCTB 0x04UL /* D-channel Transmit Buffer (W) */ |
74 | #define AMD7930_DCRB AMD7930_DCTB /* D-channel Receive Buffer (R) */ |
75 | #define AMD7930_BBTB 0x05UL /* Bb-channel Transmit Buffer (W) */ |
76 | #define AMD7930_BBRB AMD7930_BBTB /* Bb-channel Receive Buffer (R) */ |
77 | #define AMD7930_BCTB 0x06UL /* Bc-channel Transmit Buffer (W) */ |
78 | #define AMD7930_BCRB AMD7930_BCTB /* Bc-channel Receive Buffer (R) */ |
79 | #define AMD7930_DSR2 0x07UL /* D-channel Status Register 2 (R) */ |
80 | |
81 | /* Indirect registers in the Main Audio Processor. */ |
82 | struct amd7930_map { |
83 | __u16 x[8]; |
84 | __u16 r[8]; |
85 | __u16 gx; |
86 | __u16 gr; |
87 | __u16 ger; |
88 | __u16 stgr; |
89 | __u16 ftgr; |
90 | __u16 atgr; |
91 | __u8 mmr1; |
92 | __u8 mmr2; |
93 | }; |
94 | |
95 | /* After an amd7930 interrupt, reading the Interrupt Register (ir) |
96 | * clears the interrupt and returns a bitmask indicating which |
97 | * interrupt source(s) require service. |
98 | */ |
99 | |
100 | #define AMR_IR_DTTHRSH 0x01 /* D-channel xmit threshold */ |
101 | #define AMR_IR_DRTHRSH 0x02 /* D-channel recv threshold */ |
102 | #define AMR_IR_DSRI 0x04 /* D-channel packet status */ |
103 | #define AMR_IR_DERI 0x08 /* D-channel error */ |
104 | #define AMR_IR_BBUF 0x10 /* B-channel data xfer */ |
105 | #define AMR_IR_LSRI 0x20 /* LIU status */ |
106 | #define AMR_IR_DSR2I 0x40 /* D-channel buffer status */ |
107 | #define AMR_IR_MLTFRMI 0x80 /* multiframe or PP */ |
108 | |
109 | /* The amd7930 has "indirect registers" which are accessed by writing |
110 | * the register number into the Command Register and then reading or |
111 | * writing values from the Data Register as appropriate. We define the |
112 | * AMR_* macros to be the indirect register numbers and AM_* macros to |
113 | * be bits in whatever register is referred to. |
114 | */ |
115 | |
116 | /* Initialization */ |
117 | #define AMR_INIT 0x21 |
118 | #define AM_INIT_ACTIVE 0x01 |
119 | #define AM_INIT_DATAONLY 0x02 |
120 | #define AM_INIT_POWERDOWN 0x03 |
121 | #define AM_INIT_DISABLE_INTS 0x04 |
122 | #define AMR_INIT2 0x20 |
123 | #define AM_INIT2_ENABLE_POWERDOWN 0x20 |
124 | #define AM_INIT2_ENABLE_MULTIFRAME 0x10 |
125 | |
126 | /* Line Interface Unit */ |
127 | #define AMR_LIU_LSR 0xA1 |
128 | #define AM_LIU_LSR_STATE 0x07 |
129 | #define AM_LIU_LSR_F3 0x08 |
130 | #define AM_LIU_LSR_F7 0x10 |
131 | #define AM_LIU_LSR_F8 0x20 |
132 | #define AM_LIU_LSR_HSW 0x40 |
133 | #define AM_LIU_LSR_HSW_CHG 0x80 |
134 | #define AMR_LIU_LPR 0xA2 |
135 | #define AMR_LIU_LMR1 0xA3 |
136 | #define AM_LIU_LMR1_B1_ENABL 0x01 |
137 | #define AM_LIU_LMR1_B2_ENABL 0x02 |
138 | #define AM_LIU_LMR1_F_DISABL 0x04 |
139 | #define AM_LIU_LMR1_FA_DISABL 0x08 |
140 | #define AM_LIU_LMR1_REQ_ACTIV 0x10 |
141 | #define AM_LIU_LMR1_F8_F3 0x20 |
142 | #define AM_LIU_LMR1_LIU_ENABL 0x40 |
143 | #define AMR_LIU_LMR2 0xA4 |
144 | #define AM_LIU_LMR2_DECHO 0x01 |
145 | #define AM_LIU_LMR2_DLOOP 0x02 |
146 | #define AM_LIU_LMR2_DBACKOFF 0x04 |
147 | #define AM_LIU_LMR2_EN_F3_INT 0x08 |
148 | #define AM_LIU_LMR2_EN_F8_INT 0x10 |
149 | #define AM_LIU_LMR2_EN_HSW_INT 0x20 |
150 | #define AM_LIU_LMR2_EN_F7_INT 0x40 |
151 | #define AMR_LIU_2_4 0xA5 |
152 | #define AMR_LIU_MF 0xA6 |
153 | #define AMR_LIU_MFSB 0xA7 |
154 | #define AMR_LIU_MFQB 0xA8 |
155 | |
156 | /* Multiplexor */ |
157 | #define AMR_MUX_MCR1 0x41 |
158 | #define AMR_MUX_MCR2 0x42 |
159 | #define AMR_MUX_MCR3 0x43 |
160 | #define AM_MUX_CHANNEL_B1 0x01 |
161 | #define AM_MUX_CHANNEL_B2 0x02 |
162 | #define AM_MUX_CHANNEL_Ba 0x03 |
163 | #define AM_MUX_CHANNEL_Bb 0x04 |
164 | #define AM_MUX_CHANNEL_Bc 0x05 |
165 | #define AM_MUX_CHANNEL_Bd 0x06 |
166 | #define AM_MUX_CHANNEL_Be 0x07 |
167 | #define AM_MUX_CHANNEL_Bf 0x08 |
168 | #define AMR_MUX_MCR4 0x44 |
169 | #define AM_MUX_MCR4_ENABLE_INTS 0x08 |
170 | #define AM_MUX_MCR4_REVERSE_Bb 0x10 |
171 | #define AM_MUX_MCR4_REVERSE_Bc 0x20 |
172 | #define AMR_MUX_1_4 0x45 |
173 | |
174 | /* Main Audio Processor */ |
175 | #define AMR_MAP_X 0x61 |
176 | #define AMR_MAP_R 0x62 |
177 | #define AMR_MAP_GX 0x63 |
178 | #define AMR_MAP_GR 0x64 |
179 | #define AMR_MAP_GER 0x65 |
180 | #define AMR_MAP_STGR 0x66 |
181 | #define AMR_MAP_FTGR_1_2 0x67 |
182 | #define AMR_MAP_ATGR_1_2 0x68 |
183 | #define AMR_MAP_MMR1 0x69 |
184 | #define AM_MAP_MMR1_ALAW 0x01 |
185 | #define AM_MAP_MMR1_GX 0x02 |
186 | #define AM_MAP_MMR1_GR 0x04 |
187 | #define AM_MAP_MMR1_GER 0x08 |
188 | #define AM_MAP_MMR1_X 0x10 |
189 | #define AM_MAP_MMR1_R 0x20 |
190 | #define AM_MAP_MMR1_STG 0x40 |
191 | #define AM_MAP_MMR1_LOOPBACK 0x80 |
192 | #define AMR_MAP_MMR2 0x6A |
193 | #define AM_MAP_MMR2_AINB 0x01 |
194 | #define AM_MAP_MMR2_LS 0x02 |
195 | #define AM_MAP_MMR2_ENABLE_DTMF 0x04 |
196 | #define AM_MAP_MMR2_ENABLE_TONEGEN 0x08 |
197 | #define AM_MAP_MMR2_ENABLE_TONERING 0x10 |
198 | #define AM_MAP_MMR2_DISABLE_HIGHPASS 0x20 |
199 | #define AM_MAP_MMR2_DISABLE_AUTOZERO 0x40 |
200 | #define AMR_MAP_1_10 0x6B |
201 | #define AMR_MAP_MMR3 0x6C |
202 | #define AMR_MAP_STRA 0x6D |
203 | #define AMR_MAP_STRF 0x6E |
204 | #define AMR_MAP_PEAKX 0x70 |
205 | #define AMR_MAP_PEAKR 0x71 |
206 | #define AMR_MAP_15_16 0x72 |
207 | |
208 | /* Data Link Controller */ |
209 | #define AMR_DLC_FRAR_1_2_3 0x81 |
210 | #define AMR_DLC_SRAR_1_2_3 0x82 |
211 | #define AMR_DLC_TAR 0x83 |
212 | #define AMR_DLC_DRLR 0x84 |
213 | #define AMR_DLC_DTCR 0x85 |
214 | #define AMR_DLC_DMR1 0x86 |
215 | #define AMR_DLC_DMR1_DTTHRSH_INT 0x01 |
216 | #define AMR_DLC_DMR1_DRTHRSH_INT 0x02 |
217 | #define AMR_DLC_DMR1_TAR_ENABL 0x04 |
218 | #define AMR_DLC_DMR1_EORP_INT 0x08 |
219 | #define AMR_DLC_DMR1_EN_ADDR1 0x10 |
220 | #define AMR_DLC_DMR1_EN_ADDR2 0x20 |
221 | #define AMR_DLC_DMR1_EN_ADDR3 0x40 |
222 | #define AMR_DLC_DMR1_EN_ADDR4 0x80 |
223 | #define AMR_DLC_DMR1_EN_ADDRS 0xf0 |
224 | #define AMR_DLC_DMR2 0x87 |
225 | #define AMR_DLC_DMR2_RABRT_INT 0x01 |
226 | #define AMR_DLC_DMR2_RESID_INT 0x02 |
227 | #define AMR_DLC_DMR2_COLL_INT 0x04 |
228 | #define AMR_DLC_DMR2_FCS_INT 0x08 |
229 | #define AMR_DLC_DMR2_OVFL_INT 0x10 |
230 | #define AMR_DLC_DMR2_UNFL_INT 0x20 |
231 | #define AMR_DLC_DMR2_OVRN_INT 0x40 |
232 | #define AMR_DLC_DMR2_UNRN_INT 0x80 |
233 | #define AMR_DLC_1_7 0x88 |
234 | #define AMR_DLC_DRCR 0x89 |
235 | #define AMR_DLC_RNGR1 0x8A |
236 | #define AMR_DLC_RNGR2 0x8B |
237 | #define AMR_DLC_FRAR4 0x8C |
238 | #define AMR_DLC_SRAR4 0x8D |
239 | #define AMR_DLC_DMR3 0x8E |
240 | #define AMR_DLC_DMR3_VA_INT 0x01 |
241 | #define AMR_DLC_DMR3_EOTP_INT 0x02 |
242 | #define AMR_DLC_DMR3_LBRP_INT 0x04 |
243 | #define AMR_DLC_DMR3_RBA_INT 0x08 |
244 | #define AMR_DLC_DMR3_LBT_INT 0x10 |
245 | #define AMR_DLC_DMR3_TBE_INT 0x20 |
246 | #define AMR_DLC_DMR3_RPLOST_INT 0x40 |
247 | #define AMR_DLC_DMR3_KEEP_FCS 0x80 |
248 | #define AMR_DLC_DMR4 0x8F |
249 | #define AMR_DLC_DMR4_RCV_1 0x00 |
250 | #define AMR_DLC_DMR4_RCV_2 0x01 |
251 | #define AMR_DLC_DMR4_RCV_4 0x02 |
252 | #define AMR_DLC_DMR4_RCV_8 0x03 |
253 | #define AMR_DLC_DMR4_RCV_16 0x01 |
254 | #define AMR_DLC_DMR4_RCV_24 0x02 |
255 | #define AMR_DLC_DMR4_RCV_30 0x03 |
256 | #define AMR_DLC_DMR4_XMT_1 0x00 |
257 | #define AMR_DLC_DMR4_XMT_2 0x04 |
258 | #define AMR_DLC_DMR4_XMT_4 0x08 |
259 | #define AMR_DLC_DMR4_XMT_8 0x0c |
260 | #define AMR_DLC_DMR4_XMT_10 0x08 |
261 | #define AMR_DLC_DMR4_XMT_14 0x0c |
262 | #define AMR_DLC_DMR4_IDLE_MARK 0x00 |
263 | #define AMR_DLC_DMR4_IDLE_FLAG 0x10 |
264 | #define AMR_DLC_DMR4_ADDR_BOTH 0x00 |
265 | #define AMR_DLC_DMR4_ADDR_1ST 0x20 |
266 | #define AMR_DLC_DMR4_ADDR_2ND 0xa0 |
267 | #define AMR_DLC_DMR4_CR_ENABLE 0x40 |
268 | #define AMR_DLC_12_15 0x90 |
269 | #define AMR_DLC_ASR 0x91 |
270 | #define AMR_DLC_EFCR 0x92 |
271 | #define AMR_DLC_EFCR_EXTEND_FIFO 0x01 |
272 | #define AMR_DLC_EFCR_SEC_PKT_INT 0x02 |
273 | |
274 | #define AMR_DSR1_VADDR 0x01 |
275 | #define AMR_DSR1_EORP 0x02 |
276 | #define AMR_DSR1_PKT_IP 0x04 |
277 | #define AMR_DSR1_DECHO_ON 0x08 |
278 | #define AMR_DSR1_DLOOP_ON 0x10 |
279 | #define AMR_DSR1_DBACK_OFF 0x20 |
280 | #define AMR_DSR1_EOTP 0x40 |
281 | #define AMR_DSR1_CXMT_ABRT 0x80 |
282 | |
283 | #define AMR_DSR2_LBRP 0x01 |
284 | #define AMR_DSR2_RBA 0x02 |
285 | #define AMR_DSR2_RPLOST 0x04 |
286 | #define AMR_DSR2_LAST_BYTE 0x08 |
287 | #define AMR_DSR2_TBE 0x10 |
288 | #define AMR_DSR2_MARK_IDLE 0x20 |
289 | #define AMR_DSR2_FLAG_IDLE 0x40 |
290 | #define AMR_DSR2_SECOND_PKT 0x80 |
291 | |
292 | #define AMR_DER_RABRT 0x01 |
293 | #define AMR_DER_RFRAME 0x02 |
294 | #define AMR_DER_COLLISION 0x04 |
295 | #define AMR_DER_FCS 0x08 |
296 | #define AMR_DER_OVFL 0x10 |
297 | #define AMR_DER_UNFL 0x20 |
298 | #define AMR_DER_OVRN 0x40 |
299 | #define AMR_DER_UNRN 0x80 |
300 | |
301 | /* Peripheral Port */ |
302 | #define AMR_PP_PPCR1 0xC0 |
303 | #define AMR_PP_PPSR 0xC1 |
304 | #define AMR_PP_PPIER 0xC2 |
305 | #define AMR_PP_MTDR 0xC3 |
306 | #define AMR_PP_MRDR 0xC3 |
307 | #define AMR_PP_CITDR0 0xC4 |
308 | #define AMR_PP_CIRDR0 0xC4 |
309 | #define AMR_PP_CITDR1 0xC5 |
310 | #define AMR_PP_CIRDR1 0xC5 |
311 | #define AMR_PP_PPCR2 0xC8 |
312 | #define AMR_PP_PPCR3 0xC9 |
313 | |
314 | struct snd_amd7930 { |
315 | spinlock_t lock; |
316 | void __iomem *regs; |
317 | u32 flags; |
318 | #define AMD7930_FLAG_PLAYBACK 0x00000001 |
319 | #define AMD7930_FLAG_CAPTURE 0x00000002 |
320 | |
321 | struct amd7930_map map; |
322 | |
323 | struct snd_card *card; |
324 | struct snd_pcm *pcm; |
325 | struct snd_pcm_substream *playback_substream; |
326 | struct snd_pcm_substream *capture_substream; |
327 | |
328 | /* Playback/Capture buffer state. */ |
329 | unsigned char *p_orig, *p_cur; |
330 | int p_left; |
331 | unsigned char *c_orig, *c_cur; |
332 | int c_left; |
333 | |
334 | int rgain; |
335 | int pgain; |
336 | int mgain; |
337 | |
338 | struct platform_device *op; |
339 | unsigned int irq; |
340 | struct snd_amd7930 *next; |
341 | }; |
342 | |
343 | static struct snd_amd7930 *amd7930_list; |
344 | |
345 | /* Idle the AMD7930 chip. The amd->lock is not held. */ |
346 | static __inline__ void amd7930_idle(struct snd_amd7930 *amd) |
347 | { |
348 | unsigned long flags; |
349 | |
350 | spin_lock_irqsave(&amd->lock, flags); |
351 | sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR); |
352 | sbus_writeb(0, amd->regs + AMD7930_DR); |
353 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
354 | } |
355 | |
356 | /* Enable chip interrupts. The amd->lock is not held. */ |
357 | static __inline__ void amd7930_enable_ints(struct snd_amd7930 *amd) |
358 | { |
359 | unsigned long flags; |
360 | |
361 | spin_lock_irqsave(&amd->lock, flags); |
362 | sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR); |
363 | sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR); |
364 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
365 | } |
366 | |
367 | /* Disable chip interrupts. The amd->lock is not held. */ |
368 | static __inline__ void amd7930_disable_ints(struct snd_amd7930 *amd) |
369 | { |
370 | unsigned long flags; |
371 | |
372 | spin_lock_irqsave(&amd->lock, flags); |
373 | sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR); |
374 | sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR); |
375 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
376 | } |
377 | |
378 | /* Commit amd7930_map settings to the hardware. |
379 | * The amd->lock is held and local interrupts are disabled. |
380 | */ |
381 | static void __amd7930_write_map(struct snd_amd7930 *amd) |
382 | { |
383 | struct amd7930_map *map = &amd->map; |
384 | |
385 | sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR); |
386 | sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR); |
387 | sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR); |
388 | |
389 | sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR); |
390 | sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR); |
391 | sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR); |
392 | |
393 | sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR); |
394 | sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR); |
395 | sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR); |
396 | |
397 | sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR); |
398 | sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR); |
399 | sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR); |
400 | |
401 | sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR); |
402 | sbus_writeb(map->mmr1, amd->regs + AMD7930_DR); |
403 | |
404 | sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR); |
405 | sbus_writeb(map->mmr2, amd->regs + AMD7930_DR); |
406 | } |
407 | |
408 | /* gx, gr & stg gains. this table must contain 256 elements with |
409 | * the 0th being "infinity" (the magic value 9008). The remaining |
410 | * elements match sun's gain curve (but with higher resolution): |
411 | * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps. |
412 | */ |
413 | static __const__ __u16 gx_coeff[256] = { |
414 | 0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33, |
415 | 0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22, |
416 | 0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b, |
417 | 0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb, |
418 | 0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a, |
419 | 0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213, |
420 | 0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231, |
421 | 0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4, |
422 | 0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2, |
423 | 0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa, |
424 | 0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b, |
425 | 0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b, |
426 | 0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd, |
427 | 0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808, |
428 | 0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243, |
429 | 0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224, |
430 | 0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb, |
431 | 0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33, |
432 | 0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32, |
433 | 0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323, |
434 | 0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a, |
435 | 0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23, |
436 | 0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1, |
437 | 0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333, |
438 | 0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227, |
439 | 0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6, |
440 | 0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2, |
441 | 0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba, |
442 | 0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033, |
443 | 0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021, |
444 | 0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012, |
445 | 0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e, |
446 | }; |
447 | |
448 | static __const__ __u16 ger_coeff[] = { |
449 | 0x431f, /* 5. dB */ |
450 | 0x331f, /* 5.5 dB */ |
451 | 0x40dd, /* 6. dB */ |
452 | 0x11dd, /* 6.5 dB */ |
453 | 0x440f, /* 7. dB */ |
454 | 0x411f, /* 7.5 dB */ |
455 | 0x311f, /* 8. dB */ |
456 | 0x5520, /* 8.5 dB */ |
457 | 0x10dd, /* 9. dB */ |
458 | 0x4211, /* 9.5 dB */ |
459 | 0x410f, /* 10. dB */ |
460 | 0x111f, /* 10.5 dB */ |
461 | 0x600b, /* 11. dB */ |
462 | 0x00dd, /* 11.5 dB */ |
463 | 0x4210, /* 12. dB */ |
464 | 0x110f, /* 13. dB */ |
465 | 0x7200, /* 14. dB */ |
466 | 0x2110, /* 15. dB */ |
467 | 0x2200, /* 15.9 dB */ |
468 | 0x000b, /* 16.9 dB */ |
469 | 0x000f /* 18. dB */ |
470 | }; |
471 | |
472 | /* Update amd7930_map settings and program them into the hardware. |
473 | * The amd->lock is held and local interrupts are disabled. |
474 | */ |
475 | static void __amd7930_update_map(struct snd_amd7930 *amd) |
476 | { |
477 | struct amd7930_map *map = &amd->map; |
478 | int level; |
479 | |
480 | map->gx = gx_coeff[amd->rgain]; |
481 | map->stgr = gx_coeff[amd->mgain]; |
482 | level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8; |
483 | if (level >= 256) { |
484 | map->ger = ger_coeff[level - 256]; |
485 | map->gr = gx_coeff[255]; |
486 | } else { |
487 | map->ger = ger_coeff[0]; |
488 | map->gr = gx_coeff[level]; |
489 | } |
490 | __amd7930_write_map(amd); |
491 | } |
492 | |
493 | static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id) |
494 | { |
495 | struct snd_amd7930 *amd = dev_id; |
496 | unsigned int elapsed; |
497 | u8 ir; |
498 | |
499 | spin_lock(lock: &amd->lock); |
500 | |
501 | elapsed = 0; |
502 | |
503 | ir = sbus_readb(amd->regs + AMD7930_IR); |
504 | if (ir & AMR_IR_BBUF) { |
505 | u8 byte; |
506 | |
507 | if (amd->flags & AMD7930_FLAG_PLAYBACK) { |
508 | if (amd->p_left > 0) { |
509 | byte = *(amd->p_cur++); |
510 | amd->p_left--; |
511 | sbus_writeb(byte, amd->regs + AMD7930_BBTB); |
512 | if (amd->p_left == 0) |
513 | elapsed |= AMD7930_FLAG_PLAYBACK; |
514 | } else |
515 | sbus_writeb(0, amd->regs + AMD7930_BBTB); |
516 | } else if (amd->flags & AMD7930_FLAG_CAPTURE) { |
517 | byte = sbus_readb(amd->regs + AMD7930_BBRB); |
518 | if (amd->c_left > 0) { |
519 | *(amd->c_cur++) = byte; |
520 | amd->c_left--; |
521 | if (amd->c_left == 0) |
522 | elapsed |= AMD7930_FLAG_CAPTURE; |
523 | } |
524 | } |
525 | } |
526 | spin_unlock(lock: &amd->lock); |
527 | |
528 | if (elapsed & AMD7930_FLAG_PLAYBACK) |
529 | snd_pcm_period_elapsed(substream: amd->playback_substream); |
530 | else |
531 | snd_pcm_period_elapsed(substream: amd->capture_substream); |
532 | |
533 | return IRQ_HANDLED; |
534 | } |
535 | |
536 | static int snd_amd7930_trigger(struct snd_amd7930 *amd, unsigned int flag, int cmd) |
537 | { |
538 | unsigned long flags; |
539 | int result = 0; |
540 | |
541 | spin_lock_irqsave(&amd->lock, flags); |
542 | if (cmd == SNDRV_PCM_TRIGGER_START) { |
543 | if (!(amd->flags & flag)) { |
544 | amd->flags |= flag; |
545 | |
546 | /* Enable B channel interrupts. */ |
547 | sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR); |
548 | sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR); |
549 | } |
550 | } else if (cmd == SNDRV_PCM_TRIGGER_STOP) { |
551 | if (amd->flags & flag) { |
552 | amd->flags &= ~flag; |
553 | |
554 | /* Disable B channel interrupts. */ |
555 | sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR); |
556 | sbus_writeb(0, amd->regs + AMD7930_DR); |
557 | } |
558 | } else { |
559 | result = -EINVAL; |
560 | } |
561 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
562 | |
563 | return result; |
564 | } |
565 | |
566 | static int snd_amd7930_playback_trigger(struct snd_pcm_substream *substream, |
567 | int cmd) |
568 | { |
569 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
570 | return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd); |
571 | } |
572 | |
573 | static int snd_amd7930_capture_trigger(struct snd_pcm_substream *substream, |
574 | int cmd) |
575 | { |
576 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
577 | return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd); |
578 | } |
579 | |
580 | static int snd_amd7930_playback_prepare(struct snd_pcm_substream *substream) |
581 | { |
582 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
583 | struct snd_pcm_runtime *runtime = substream->runtime; |
584 | unsigned int size = snd_pcm_lib_buffer_bytes(substream); |
585 | unsigned long flags; |
586 | u8 new_mmr1; |
587 | |
588 | spin_lock_irqsave(&amd->lock, flags); |
589 | |
590 | amd->flags |= AMD7930_FLAG_PLAYBACK; |
591 | |
592 | /* Setup the pseudo-dma transfer pointers. */ |
593 | amd->p_orig = amd->p_cur = runtime->dma_area; |
594 | amd->p_left = size; |
595 | |
596 | /* Put the chip into the correct encoding format. */ |
597 | new_mmr1 = amd->map.mmr1; |
598 | if (runtime->format == SNDRV_PCM_FORMAT_A_LAW) |
599 | new_mmr1 |= AM_MAP_MMR1_ALAW; |
600 | else |
601 | new_mmr1 &= ~AM_MAP_MMR1_ALAW; |
602 | if (new_mmr1 != amd->map.mmr1) { |
603 | amd->map.mmr1 = new_mmr1; |
604 | __amd7930_update_map(amd); |
605 | } |
606 | |
607 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
608 | |
609 | return 0; |
610 | } |
611 | |
612 | static int snd_amd7930_capture_prepare(struct snd_pcm_substream *substream) |
613 | { |
614 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
615 | struct snd_pcm_runtime *runtime = substream->runtime; |
616 | unsigned int size = snd_pcm_lib_buffer_bytes(substream); |
617 | unsigned long flags; |
618 | u8 new_mmr1; |
619 | |
620 | spin_lock_irqsave(&amd->lock, flags); |
621 | |
622 | amd->flags |= AMD7930_FLAG_CAPTURE; |
623 | |
624 | /* Setup the pseudo-dma transfer pointers. */ |
625 | amd->c_orig = amd->c_cur = runtime->dma_area; |
626 | amd->c_left = size; |
627 | |
628 | /* Put the chip into the correct encoding format. */ |
629 | new_mmr1 = amd->map.mmr1; |
630 | if (runtime->format == SNDRV_PCM_FORMAT_A_LAW) |
631 | new_mmr1 |= AM_MAP_MMR1_ALAW; |
632 | else |
633 | new_mmr1 &= ~AM_MAP_MMR1_ALAW; |
634 | if (new_mmr1 != amd->map.mmr1) { |
635 | amd->map.mmr1 = new_mmr1; |
636 | __amd7930_update_map(amd); |
637 | } |
638 | |
639 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
640 | |
641 | return 0; |
642 | } |
643 | |
644 | static snd_pcm_uframes_t snd_amd7930_playback_pointer(struct snd_pcm_substream *substream) |
645 | { |
646 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
647 | size_t ptr; |
648 | |
649 | if (!(amd->flags & AMD7930_FLAG_PLAYBACK)) |
650 | return 0; |
651 | ptr = amd->p_cur - amd->p_orig; |
652 | return bytes_to_frames(runtime: substream->runtime, size: ptr); |
653 | } |
654 | |
655 | static snd_pcm_uframes_t snd_amd7930_capture_pointer(struct snd_pcm_substream *substream) |
656 | { |
657 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
658 | size_t ptr; |
659 | |
660 | if (!(amd->flags & AMD7930_FLAG_CAPTURE)) |
661 | return 0; |
662 | |
663 | ptr = amd->c_cur - amd->c_orig; |
664 | return bytes_to_frames(runtime: substream->runtime, size: ptr); |
665 | } |
666 | |
667 | /* Playback and capture have identical properties. */ |
668 | static const struct snd_pcm_hardware snd_amd7930_pcm_hw = |
669 | { |
670 | .info = (SNDRV_PCM_INFO_MMAP | |
671 | SNDRV_PCM_INFO_MMAP_VALID | |
672 | SNDRV_PCM_INFO_INTERLEAVED | |
673 | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
674 | SNDRV_PCM_INFO_HALF_DUPLEX), |
675 | .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW, |
676 | .rates = SNDRV_PCM_RATE_8000, |
677 | .rate_min = 8000, |
678 | .rate_max = 8000, |
679 | .channels_min = 1, |
680 | .channels_max = 1, |
681 | .buffer_bytes_max = (64*1024), |
682 | .period_bytes_min = 1, |
683 | .period_bytes_max = (64*1024), |
684 | .periods_min = 1, |
685 | .periods_max = 1024, |
686 | }; |
687 | |
688 | static int snd_amd7930_playback_open(struct snd_pcm_substream *substream) |
689 | { |
690 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
691 | struct snd_pcm_runtime *runtime = substream->runtime; |
692 | |
693 | amd->playback_substream = substream; |
694 | runtime->hw = snd_amd7930_pcm_hw; |
695 | return 0; |
696 | } |
697 | |
698 | static int snd_amd7930_capture_open(struct snd_pcm_substream *substream) |
699 | { |
700 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
701 | struct snd_pcm_runtime *runtime = substream->runtime; |
702 | |
703 | amd->capture_substream = substream; |
704 | runtime->hw = snd_amd7930_pcm_hw; |
705 | return 0; |
706 | } |
707 | |
708 | static int snd_amd7930_playback_close(struct snd_pcm_substream *substream) |
709 | { |
710 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
711 | |
712 | amd->playback_substream = NULL; |
713 | return 0; |
714 | } |
715 | |
716 | static int snd_amd7930_capture_close(struct snd_pcm_substream *substream) |
717 | { |
718 | struct snd_amd7930 *amd = snd_pcm_substream_chip(substream); |
719 | |
720 | amd->capture_substream = NULL; |
721 | return 0; |
722 | } |
723 | |
724 | static const struct snd_pcm_ops snd_amd7930_playback_ops = { |
725 | .open = snd_amd7930_playback_open, |
726 | .close = snd_amd7930_playback_close, |
727 | .prepare = snd_amd7930_playback_prepare, |
728 | .trigger = snd_amd7930_playback_trigger, |
729 | .pointer = snd_amd7930_playback_pointer, |
730 | }; |
731 | |
732 | static const struct snd_pcm_ops snd_amd7930_capture_ops = { |
733 | .open = snd_amd7930_capture_open, |
734 | .close = snd_amd7930_capture_close, |
735 | .prepare = snd_amd7930_capture_prepare, |
736 | .trigger = snd_amd7930_capture_trigger, |
737 | .pointer = snd_amd7930_capture_pointer, |
738 | }; |
739 | |
740 | static int snd_amd7930_pcm(struct snd_amd7930 *amd) |
741 | { |
742 | struct snd_pcm *pcm; |
743 | int err; |
744 | |
745 | if ((err = snd_pcm_new(card: amd->card, |
746 | /* ID */ id: "sun_amd7930" , |
747 | /* device */ 0, |
748 | /* playback count */ playback_count: 1, |
749 | /* capture count */ capture_count: 1, rpcm: &pcm)) < 0) |
750 | return err; |
751 | |
752 | snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_amd7930_playback_ops); |
753 | snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &snd_amd7930_capture_ops); |
754 | |
755 | pcm->private_data = amd; |
756 | pcm->info_flags = 0; |
757 | strcpy(p: pcm->name, q: amd->card->shortname); |
758 | amd->pcm = pcm; |
759 | |
760 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, |
761 | NULL, size: 64*1024, max: 64*1024); |
762 | |
763 | return 0; |
764 | } |
765 | |
766 | #define VOLUME_MONITOR 0 |
767 | #define VOLUME_CAPTURE 1 |
768 | #define VOLUME_PLAYBACK 2 |
769 | |
770 | static int snd_amd7930_info_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo) |
771 | { |
772 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
773 | uinfo->count = 1; |
774 | uinfo->value.integer.min = 0; |
775 | uinfo->value.integer.max = 255; |
776 | |
777 | return 0; |
778 | } |
779 | |
780 | static int snd_amd7930_get_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol) |
781 | { |
782 | struct snd_amd7930 *amd = snd_kcontrol_chip(kctl); |
783 | int type = kctl->private_value; |
784 | int *swval; |
785 | |
786 | switch (type) { |
787 | case VOLUME_MONITOR: |
788 | swval = &amd->mgain; |
789 | break; |
790 | case VOLUME_CAPTURE: |
791 | swval = &amd->rgain; |
792 | break; |
793 | case VOLUME_PLAYBACK: |
794 | default: |
795 | swval = &amd->pgain; |
796 | break; |
797 | } |
798 | |
799 | ucontrol->value.integer.value[0] = *swval; |
800 | |
801 | return 0; |
802 | } |
803 | |
804 | static int snd_amd7930_put_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol) |
805 | { |
806 | struct snd_amd7930 *amd = snd_kcontrol_chip(kctl); |
807 | unsigned long flags; |
808 | int type = kctl->private_value; |
809 | int *swval, change; |
810 | |
811 | switch (type) { |
812 | case VOLUME_MONITOR: |
813 | swval = &amd->mgain; |
814 | break; |
815 | case VOLUME_CAPTURE: |
816 | swval = &amd->rgain; |
817 | break; |
818 | case VOLUME_PLAYBACK: |
819 | default: |
820 | swval = &amd->pgain; |
821 | break; |
822 | } |
823 | |
824 | spin_lock_irqsave(&amd->lock, flags); |
825 | |
826 | if (*swval != ucontrol->value.integer.value[0]) { |
827 | *swval = ucontrol->value.integer.value[0] & 0xff; |
828 | __amd7930_update_map(amd); |
829 | change = 1; |
830 | } else |
831 | change = 0; |
832 | |
833 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
834 | |
835 | return change; |
836 | } |
837 | |
838 | static const struct snd_kcontrol_new amd7930_controls[] = { |
839 | { |
840 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
841 | .name = "Monitor Volume" , |
842 | .index = 0, |
843 | .info = snd_amd7930_info_volume, |
844 | .get = snd_amd7930_get_volume, |
845 | .put = snd_amd7930_put_volume, |
846 | .private_value = VOLUME_MONITOR, |
847 | }, |
848 | { |
849 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
850 | .name = "Capture Volume" , |
851 | .index = 0, |
852 | .info = snd_amd7930_info_volume, |
853 | .get = snd_amd7930_get_volume, |
854 | .put = snd_amd7930_put_volume, |
855 | .private_value = VOLUME_CAPTURE, |
856 | }, |
857 | { |
858 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
859 | .name = "Playback Volume" , |
860 | .index = 0, |
861 | .info = snd_amd7930_info_volume, |
862 | .get = snd_amd7930_get_volume, |
863 | .put = snd_amd7930_put_volume, |
864 | .private_value = VOLUME_PLAYBACK, |
865 | }, |
866 | }; |
867 | |
868 | static int snd_amd7930_mixer(struct snd_amd7930 *amd) |
869 | { |
870 | struct snd_card *card; |
871 | int idx, err; |
872 | |
873 | if (snd_BUG_ON(!amd || !amd->card)) |
874 | return -EINVAL; |
875 | |
876 | card = amd->card; |
877 | strcpy(p: card->mixername, q: card->shortname); |
878 | |
879 | for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) { |
880 | if ((err = snd_ctl_add(card, |
881 | kcontrol: snd_ctl_new1(kcontrolnew: &amd7930_controls[idx], private_data: amd))) < 0) |
882 | return err; |
883 | } |
884 | |
885 | return 0; |
886 | } |
887 | |
888 | static int snd_amd7930_free(struct snd_amd7930 *amd) |
889 | { |
890 | struct platform_device *op = amd->op; |
891 | |
892 | amd7930_idle(amd); |
893 | |
894 | if (amd->irq) |
895 | free_irq(amd->irq, amd); |
896 | |
897 | if (amd->regs) |
898 | of_iounmap(&op->resource[0], amd->regs, |
899 | resource_size(res: &op->resource[0])); |
900 | |
901 | kfree(objp: amd); |
902 | |
903 | return 0; |
904 | } |
905 | |
906 | static int snd_amd7930_dev_free(struct snd_device *device) |
907 | { |
908 | struct snd_amd7930 *amd = device->device_data; |
909 | |
910 | return snd_amd7930_free(amd); |
911 | } |
912 | |
913 | static const struct snd_device_ops snd_amd7930_dev_ops = { |
914 | .dev_free = snd_amd7930_dev_free, |
915 | }; |
916 | |
917 | static int snd_amd7930_create(struct snd_card *card, |
918 | struct platform_device *op, |
919 | int irq, int dev, |
920 | struct snd_amd7930 **ramd) |
921 | { |
922 | struct snd_amd7930 *amd; |
923 | unsigned long flags; |
924 | int err; |
925 | |
926 | *ramd = NULL; |
927 | amd = kzalloc(size: sizeof(*amd), GFP_KERNEL); |
928 | if (amd == NULL) |
929 | return -ENOMEM; |
930 | |
931 | spin_lock_init(&amd->lock); |
932 | amd->card = card; |
933 | amd->op = op; |
934 | |
935 | amd->regs = of_ioremap(&op->resource[0], 0, |
936 | resource_size(res: &op->resource[0]), "amd7930" ); |
937 | if (!amd->regs) { |
938 | snd_printk(KERN_ERR |
939 | "amd7930-%d: Unable to map chip registers.\n" , dev); |
940 | kfree(objp: amd); |
941 | return -EIO; |
942 | } |
943 | |
944 | amd7930_idle(amd); |
945 | |
946 | if (request_irq(irq, handler: snd_amd7930_interrupt, |
947 | IRQF_SHARED, name: "amd7930" , dev: amd)) { |
948 | snd_printk(KERN_ERR "amd7930-%d: Unable to grab IRQ %d\n" , |
949 | dev, irq); |
950 | snd_amd7930_free(amd); |
951 | return -EBUSY; |
952 | } |
953 | amd->irq = irq; |
954 | |
955 | amd7930_enable_ints(amd); |
956 | |
957 | spin_lock_irqsave(&amd->lock, flags); |
958 | |
959 | amd->rgain = 128; |
960 | amd->pgain = 200; |
961 | amd->mgain = 0; |
962 | |
963 | memset(&amd->map, 0, sizeof(amd->map)); |
964 | amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER | |
965 | AM_MAP_MMR1_GR | AM_MAP_MMR1_STG); |
966 | amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB); |
967 | |
968 | __amd7930_update_map(amd); |
969 | |
970 | /* Always MUX audio (Ba) to channel Bb. */ |
971 | sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR); |
972 | sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4), |
973 | amd->regs + AMD7930_DR); |
974 | |
975 | spin_unlock_irqrestore(lock: &amd->lock, flags); |
976 | |
977 | err = snd_device_new(card, type: SNDRV_DEV_LOWLEVEL, |
978 | device_data: amd, ops: &snd_amd7930_dev_ops); |
979 | if (err < 0) { |
980 | snd_amd7930_free(amd); |
981 | return err; |
982 | } |
983 | |
984 | *ramd = amd; |
985 | return 0; |
986 | } |
987 | |
988 | static int amd7930_sbus_probe(struct platform_device *op) |
989 | { |
990 | struct resource *rp = &op->resource[0]; |
991 | static int dev_num; |
992 | struct snd_card *card; |
993 | struct snd_amd7930 *amd; |
994 | int err, irq; |
995 | |
996 | irq = op->archdata.irqs[0]; |
997 | |
998 | if (dev_num >= SNDRV_CARDS) |
999 | return -ENODEV; |
1000 | if (!enable[dev_num]) { |
1001 | dev_num++; |
1002 | return -ENOENT; |
1003 | } |
1004 | |
1005 | err = snd_card_new(parent: &op->dev, idx: index[dev_num], xid: id[dev_num], |
1006 | THIS_MODULE, extra_size: 0, card_ret: &card); |
1007 | if (err < 0) |
1008 | return err; |
1009 | |
1010 | strcpy(p: card->driver, q: "AMD7930" ); |
1011 | strcpy(p: card->shortname, q: "Sun AMD7930" ); |
1012 | sprintf(buf: card->longname, fmt: "%s at 0x%02lx:0x%08Lx, irq %d" , |
1013 | card->shortname, |
1014 | rp->flags & 0xffL, |
1015 | (unsigned long long)rp->start, |
1016 | irq); |
1017 | |
1018 | if ((err = snd_amd7930_create(card, op, |
1019 | irq, dev: dev_num, ramd: &amd)) < 0) |
1020 | goto out_err; |
1021 | |
1022 | err = snd_amd7930_pcm(amd); |
1023 | if (err < 0) |
1024 | goto out_err; |
1025 | |
1026 | err = snd_amd7930_mixer(amd); |
1027 | if (err < 0) |
1028 | goto out_err; |
1029 | |
1030 | err = snd_card_register(card); |
1031 | if (err < 0) |
1032 | goto out_err; |
1033 | |
1034 | amd->next = amd7930_list; |
1035 | amd7930_list = amd; |
1036 | |
1037 | dev_num++; |
1038 | |
1039 | return 0; |
1040 | |
1041 | out_err: |
1042 | snd_card_free(card); |
1043 | return err; |
1044 | } |
1045 | |
1046 | static const struct of_device_id amd7930_match[] = { |
1047 | { |
1048 | .name = "audio" , |
1049 | }, |
1050 | {}, |
1051 | }; |
1052 | MODULE_DEVICE_TABLE(of, amd7930_match); |
1053 | |
1054 | static struct platform_driver amd7930_sbus_driver = { |
1055 | .driver = { |
1056 | .name = "audio" , |
1057 | .of_match_table = amd7930_match, |
1058 | }, |
1059 | .probe = amd7930_sbus_probe, |
1060 | }; |
1061 | |
1062 | static int __init amd7930_init(void) |
1063 | { |
1064 | return platform_driver_register(&amd7930_sbus_driver); |
1065 | } |
1066 | |
1067 | static void __exit amd7930_exit(void) |
1068 | { |
1069 | struct snd_amd7930 *p = amd7930_list; |
1070 | |
1071 | while (p != NULL) { |
1072 | struct snd_amd7930 *next = p->next; |
1073 | |
1074 | snd_card_free(card: p->card); |
1075 | |
1076 | p = next; |
1077 | } |
1078 | |
1079 | amd7930_list = NULL; |
1080 | |
1081 | platform_driver_unregister(&amd7930_sbus_driver); |
1082 | } |
1083 | |
1084 | module_init(amd7930_init); |
1085 | module_exit(amd7930_exit); |
1086 | |