1//===--- arm_cde.td - ACLE intrinsic functions for CDE --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the set of ACLE-specified source-level intrinsic
10// functions wrapping the CDE instructions.
11//
12//===----------------------------------------------------------------------===//
13
14include "arm_mve_defs.td"
15
16// f64 is not defined in arm_mve_defs.td because MVE instructions only work with
17// f16 and f32
18def f64: PrimitiveType<"f", 64>;
19
20// Float<t> expects t to be a scalar type, and expands to the floating-point
21// type of the same width.
22class Float<Type t>: ComplexType<(CTO_CopyKind t, f32)>;
23def FScalar: Float<Scalar>;
24
25// ACLE CDE intrinsic
26class CDEIntrinsic<Type ret, dag args, dag codegen>
27 : Intrinsic<ret, args, codegen> {
28 let builtinExtension = "cde";
29}
30
31// Immediate (in range [0, 2^numBits - 1])
32class IB_ConstBits<int numBits> : IB_ConstRange<0, !add(!shl(1, numBits), -1)>;
33// numBits-wide immediate of type u32
34class CDEImmediateBits<int numBits> : Immediate<u32, IB_ConstBits<numBits>>;
35
36// LLVM IR CDE intrinsic
37class CDEIRInt<string name, list<Type> params = [], bit appendKind = 0>
38 : IRIntBase<"arm_cde_" # name, params, appendKind>;
39
40// Class for generating function macros in arm_cde.h:
41// "#define <name>(<params>) <definition>"
42class FunctionMacro<list<string> params_, string definition_> {
43 list<string> params = params_;
44 string definition = definition_;
45}
46
47// Coprocessor immediate
48def imm_coproc : Immediate<sint, IB_ConstRange<0, 7>>;
49
50// Immediate integer parameters
51def imm_3b : CDEImmediateBits<3>;
52def imm_4b : CDEImmediateBits<4>;
53def imm_6b : CDEImmediateBits<6>;
54def imm_7b : CDEImmediateBits<7>;
55def imm_9b : CDEImmediateBits<9>;
56def imm_11b : CDEImmediateBits<11>;
57def imm_12b : CDEImmediateBits<12>;
58def imm_13b : CDEImmediateBits<13>;
59
60// CX* instructions operating on GPRs
61multiclass CDE_CX_m<dag argsImm, dag argsReg, dag cgArgs> {
62 defvar cp = (args imm_coproc:$cp);
63 let pnt = PNT_None, params = T.None in {
64 def "" : CDEIntrinsic<u32, !con(cp, argsReg, argsImm),
65 !con((CDEIRInt<NAME> $cp), cgArgs, (? $imm))>;
66 def a : CDEIntrinsic<u32, !con(cp, (args u32:$acc), argsReg, argsImm),
67 !con((CDEIRInt<NAME # "a"> $cp, $acc),
68 cgArgs, (? $imm))>;
69
70 def d :
71 CDEIntrinsic<u64, !con(cp, argsReg, argsImm),
72 (seq !con((CDEIRInt<NAME # "d"> $cp), cgArgs, (? $imm)):$pair,
73 (or (shl (u64 (xval $pair, 1)), (u64 32)),
74 (u64 (xval $pair, 0))))>;
75 def da :
76 CDEIntrinsic<u64, !con(cp, (args u64:$acc), argsReg, argsImm),
77 (seq (u32 (lshr $acc, (u64 32))):$acc_hi,
78 (u32 $acc):$acc_lo,
79 !con((CDEIRInt<NAME # "da"> $cp, $acc_lo, $acc_hi), cgArgs,
80 (? $imm)):$pair,
81 (or (shl (u64 (xval $pair, 1)), (u64 32)),
82 (u64 (xval $pair, 0))))>;
83 }
84}
85
86defm cx1 : CDE_CX_m<(args imm_13b:$imm), (args), (?)>;
87defm cx2 : CDE_CX_m<(args imm_9b:$imm), (args u32:$n), (? $n)>;
88defm cx3 : CDE_CX_m<(args imm_6b:$imm), (args u32:$n, u32:$m), (? $n, $m)>;
89
90// VCX* instructions operating on VFP registers
91multiclass CDE_VCXFP_m<dag argsImm, dag argsReg32, dag argsReg64, dag cgArgs> {
92 defvar cp = (args imm_coproc:$cp);
93 let pnt = PNT_None, params = [u32] in {
94 def "" : CDEIntrinsic<u32, !con(cp, argsReg32, argsImm),
95 (bitcast !con((CDEIRInt<NAME, [f32]> $cp), cgArgs, (? $imm)),
96 Scalar)>;
97 def a : CDEIntrinsic<u32, !con(cp, (args u32:$acc), argsReg32, argsImm),
98 (bitcast !con((CDEIRInt<NAME # "a", [f32]> $cp,
99 (bitcast $acc, FScalar)), cgArgs, (? $imm)), Scalar)>;
100 }
101 let pnt = PNT_None, params = [u64] in {
102 def d : CDEIntrinsic<u64, !con(cp, argsReg64, argsImm),
103 (bitcast !con((CDEIRInt<NAME, [f64]> $cp), cgArgs, (? $imm)),
104 Scalar)>;
105 def da : CDEIntrinsic<u64, !con(cp, (args u64:$acc), argsReg64, argsImm),
106 (bitcast !con((CDEIRInt<NAME # "a", [f64]> $cp,
107 (bitcast $acc, FScalar)), cgArgs, (? $imm)), Scalar)>;
108 }
109}
110
111defm vcx1: CDE_VCXFP_m<(args imm_11b:$imm), (args), (args), (?)>;
112defm vcx2: CDE_VCXFP_m<(args imm_6b:$imm), (args u32:$n), (args u64:$n),
113 (? (bitcast $n, FScalar))>;
114defm vcx3: CDE_VCXFP_m<(args imm_3b:$imm),
115 (args u32:$n, u32:$m), (args u64:$n, u64:$m),
116 (? (bitcast $n, FScalar), (bitcast $m, FScalar))>;
117
118// VCX* instructions operating on Q vector registers
119
120def v16u8 : VecOf<u8>;
121
122let pnt = PNT_None, params = [u8] in
123def vcx1q : CDEIntrinsic<Vector, (args imm_coproc:$cp, imm_12b:$imm),
124 (CDEIRInt<"vcx1q"> $cp, $imm)>;
125
126let pnt = PNT_Type, params = T.All, polymorphicOnly = 1 in {
127 def vcx1qa :
128 CDEIntrinsic<Vector, (args imm_coproc:$cp, Vector:$acc, imm_12b:$imm),
129 (bitcast (CDEIRInt<"vcx1qa"> $cp, (bitcast $acc, v16u8), $imm),
130 Vector)>;
131
132 def vcx2q :
133 CDEIntrinsic<Vector, (args imm_coproc:$cp, Vector:$n, imm_7b:$imm),
134 (bitcast (CDEIRInt<"vcx2q"> $cp, (bitcast $n, VecOf<u8>), $imm),
135 Vector)>;
136 def vcx2q_u8 :
137 CDEIntrinsic<v16u8, (args imm_coproc:$cp, Vector:$n, imm_7b:$imm),
138 (CDEIRInt<"vcx2q"> $cp, (bitcast $n, VecOf<u8>), $imm)>;
139
140 def vcx2qa_impl :
141 CDEIntrinsic<Vector,
142 (args imm_coproc:$cp, Vector:$acc, v16u8:$n, imm_7b:$imm),
143 (bitcast (CDEIRInt<"vcx2qa"> $cp, (bitcast $acc, v16u8), $n, $imm),
144 Vector)>;
145
146 def vcx3q_impl :
147 CDEIntrinsic<Vector,
148 (args imm_coproc:$cp, Vector:$n, v16u8:$m, imm_4b:$imm),
149 (bitcast (CDEIRInt<"vcx3q"> $cp, (bitcast $n, v16u8), $m, $imm),
150 Vector)>;
151 def vcx3q_u8_impl :
152 CDEIntrinsic<v16u8,
153 (args imm_coproc:$cp, Vector:$n, v16u8:$m, imm_4b:$imm),
154 (CDEIRInt<"vcx3q"> $cp, (bitcast $n, v16u8), $m, $imm)>;
155 def vcx3qa_impl :
156 CDEIntrinsic<Vector,
157 (args imm_coproc:$cp, Vector:$acc, v16u8:$n, v16u8:$m, imm_4b:$imm),
158 (bitcast (CDEIRInt<"vcx3qa"> $cp, (bitcast $acc, v16u8), $n, $m,
159 $imm),
160 Vector)>;
161}
162
163// Reinterpret intrinsics required to implement __arm_vcx*q with 2 or 3
164// polymorphic paramters.
165let params = [/* no u8 */ s8, u16, s16, u32, s32, u64, s64, f16, f32],
166 headerOnly = 1, polymorphicOnly = 1 in
167def vreinterpretq_u8 :
168 Intrinsic<v16u8, (args Vector:$x), (vreinterpret $x, v16u8)>;
169
170// We need vreinterpretq_u8_u8 to avoid doing smart tricks in the macros
171let params = [u8], polymorphicOnly = 1 in
172def vreinterpretq_u8_cde :
173 CDEIntrinsic<v16u8, (args Vector:$x), (id $x)>,
174 NameOverride<"vreinterpretq_u8">;
175
176
177def vcx2qa : FunctionMacro<
178 ["cp", "acc", "n", "imm"],
179 "__arm_vcx2qa_impl((cp), (acc), __arm_vreinterpretq_u8(n), (imm))">;
180
181def vcx3q : FunctionMacro<
182 ["cp", "n", "m", "imm"],
183 "__arm_vcx3q_impl((cp), (n), __arm_vreinterpretq_u8(m), (imm))">;
184def vcx3q_u8 : FunctionMacro<
185 ["cp", "n", "m", "imm"],
186 "__arm_vcx3q_u8_impl((cp), (n), __arm_vreinterpretq_u8(m), (imm))">;
187def vcx3qa : FunctionMacro<
188 ["cp", "acc", "n", "m", "imm"],
189 "__arm_vcx3qa_impl((cp), (acc), __arm_vreinterpretq_u8(n), "
190 "__arm_vreinterpretq_u8(m), (imm))">;
191
192class CDEIntrinsicMasked<string irname, dag argsReg, dag imm, dag cgArgs>
193 : CDEIntrinsic<Vector,
194 !con((args imm_coproc:$cp, Vector:$inactive_or_acc),
195 argsReg, imm, (args Predicate:$pred)),
196 !con((CDEIRInt<irname # "_predicated", [Vector,Predicate]>
197 $cp, $inactive_or_acc), cgArgs, (? $imm, $pred))> {
198 let params = T.All;
199 let polymorphicOnly = 1;
200}
201
202def vcx1q_m : CDEIntrinsicMasked<"vcx1q", (args), (args imm_12b:$imm), (?)>;
203def vcx1qa_m : CDEIntrinsicMasked<"vcx1qa", (args), (args imm_12b:$imm), (?)>;
204
205multiclass VCXPredicated<dag argsReg, dag imm, dag cgArgs,
206 list<string> macroArgs, string macro> {
207 def _m_impl : CDEIntrinsicMasked<NAME, argsReg, imm, cgArgs>;
208 def a_m_impl : CDEIntrinsicMasked<NAME#"a", argsReg, imm, cgArgs>;
209
210 def _m: FunctionMacro<
211 !listconcat(["cp", "inactive"], macroArgs, ["imm", "pred"]),
212 "__arm_"#NAME#"_m_impl((cp), (inactive), "#macro#" (imm), (pred))">;
213 def a_m: FunctionMacro<
214 !listconcat(["cp", "acc"], macroArgs, ["imm", "pred"]),
215 "__arm_"#NAME#"a_m_impl((cp), (acc), "#macro#" (imm), (pred))">;
216}
217
218defm vcx2q :
219 VCXPredicated<(args v16u8:$n), (args imm_7b:$imm), (? $n), ["n"],
220 "__arm_vreinterpretq_u8(n),">;
221defm vcx3q :
222 VCXPredicated<(args v16u8:$n, v16u8:$m), (args imm_4b:$imm), (? $n, $m),
223 ["n", "m"], "__arm_vreinterpretq_u8(n), "
224 "__arm_vreinterpretq_u8(m),">;
225
226// vreinterpretq intrinsics required by the ACLE CDE specification
227
228foreach desttype = [/* no u8 */ s8, u16, s16, u32, s32, u64, s64, f16, f32] in {
229 let params = [u8], headerOnly = 1, pnt = PNT_None in
230 def "vreinterpretq_" # desttype : Intrinsic<
231 VecOf<desttype>, (args Vector:$x), (vreinterpret $x, VecOf<desttype>)>;
232}
233