1//===--- arm_fp16.td - ARM FP16 compiler interface ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the TableGen definitions from which the ARM FP16 header
10// file will be generated.
11//
12//===----------------------------------------------------------------------===//
13
14include "arm_neon_incl.td"
15
16// ARMv8.2-A FP16 intrinsics.
17let ArchGuard = "defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) && defined(__aarch64__)" in {
18
19 // Negate
20 def VNEGSH : SInst<"vneg", "11", "Sh">;
21
22 // Reciprocal/Sqrt
23 def SCALAR_FRECPSH : IInst<"vrecps", "111", "Sh">;
24 def FSQRTSH : SInst<"vsqrt", "11", "Sh">;
25 def SCALAR_FRSQRTSH : IInst<"vrsqrts", "111", "Sh">;
26
27 // Reciprocal Estimate
28 def SCALAR_FRECPEH : IInst<"vrecpe", "11", "Sh">;
29
30 // Reciprocal Exponent
31 def SCALAR_FRECPXH : IInst<"vrecpx", "11", "Sh">;
32
33 // Reciprocal Square Root Estimate
34 def SCALAR_FRSQRTEH : IInst<"vrsqrte", "11", "Sh">;
35
36 // Rounding
37 def FRINTZ_S64H : SInst<"vrnd", "11", "Sh">;
38 def FRINTA_S64H : SInst<"vrnda", "11", "Sh">;
39 def FRINTI_S64H : SInst<"vrndi", "11", "Sh">;
40 def FRINTM_S64H : SInst<"vrndm", "11", "Sh">;
41 def FRINTN_S64H : SInst<"vrndn", "11", "Sh">;
42 def FRINTP_S64H : SInst<"vrndp", "11", "Sh">;
43 def FRINTX_S64H : SInst<"vrndx", "11", "Sh">;
44
45 // Conversion
46 def SCALAR_SCVTFSH : SInst<"vcvth_f16", "(1F)(1!)", "sUs">;
47 def SCALAR_SCVTFSH1 : SInst<"vcvth_f16", "(1F<)(1!)", "iUi">;
48 def SCALAR_SCVTFSH2 : SInst<"vcvth_f16", "(1F<<)(1!)", "lUl">;
49 def SCALAR_FCVTZSH : SInst<"vcvt_s16", "(1S)1", "Sh">;
50 def SCALAR_FCVTZSH1 : SInst<"vcvt_s32", "(1S>)1", "Sh">;
51 def SCALAR_FCVTZSH2 : SInst<"vcvt_s64", "(1S>>)1", "Sh">;
52 def SCALAR_FCVTZUH : SInst<"vcvt_u16", "(1U)1", "Sh">;
53 def SCALAR_FCVTZUH1 : SInst<"vcvt_u32", "(1U>)1", "Sh">;
54 def SCALAR_FCVTZUH2 : SInst<"vcvt_u64", "(1U>>)1", "Sh">;
55 def SCALAR_FCVTASH : SInst<"vcvta_s16", "(1S)1", "Sh">;
56 def SCALAR_FCVTASH1 : SInst<"vcvta_s32", "(1S>)1", "Sh">;
57 def SCALAR_FCVTASH2 : SInst<"vcvta_s64", "(1S>>)1", "Sh">;
58 def SCALAR_FCVTAUH : SInst<"vcvta_u16", "(1U)1", "Sh">;
59 def SCALAR_FCVTAUH1 : SInst<"vcvta_u32", "(1U>)1", "Sh">;
60 def SCALAR_FCVTAUH2 : SInst<"vcvta_u64", "(1U>>)1", "Sh">;
61 def SCALAR_FCVTMSH : SInst<"vcvtm_s16", "(1S)1", "Sh">;
62 def SCALAR_FCVTMSH1 : SInst<"vcvtm_s32", "(1S>)1", "Sh">;
63 def SCALAR_FCVTMSH2 : SInst<"vcvtm_s64", "(1S>>)1", "Sh">;
64 def SCALAR_FCVTMUH : SInst<"vcvtm_u16", "(1U)1", "Sh">;
65 def SCALAR_FCVTMUH1 : SInst<"vcvtm_u32", "(1U>)1", "Sh">;
66 def SCALAR_FCVTMUH2 : SInst<"vcvtm_u64", "(1U>>)1", "Sh">;
67 def SCALAR_FCVTNSH : SInst<"vcvtn_s16", "(1S)1", "Sh">;
68 def SCALAR_FCVTNSH1 : SInst<"vcvtn_s32", "(1S>)1", "Sh">;
69 def SCALAR_FCVTNSH2 : SInst<"vcvtn_s64", "(1S>>)1", "Sh">;
70 def SCALAR_FCVTNUH : SInst<"vcvtn_u16", "(1U)1", "Sh">;
71 def SCALAR_FCVTNUH1 : SInst<"vcvtn_u32", "(1U>)1", "Sh">;
72 def SCALAR_FCVTNUH2 : SInst<"vcvtn_u64", "(1U>>)1", "Sh">;
73 def SCALAR_FCVTPSH : SInst<"vcvtp_s16", "(1S)1", "Sh">;
74 def SCALAR_FCVTPSH1 : SInst<"vcvtp_s32", "(1S>)1", "Sh">;
75 def SCALAR_FCVTPSH2 : SInst<"vcvtp_s64", "(1S>>)1", "Sh">;
76 def SCALAR_FCVTPUH : SInst<"vcvtp_u16", "(1U)1", "Sh">;
77 def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "(1U>)1", "Sh">;
78 def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "(1U>>)1", "Sh">;
79 let isVCVT_N = 1 in {
80 def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "(1F)(1!)I", "sUs">;
81 def SCALAR_SCVTFSH1O: SInst<"vcvth_n_f16", "(1F<)(1!)I", "iUi">;
82 def SCALAR_SCVTFSH2O: SInst<"vcvth_n_f16", "(1F<<)(1!)I", "lUl">;
83 def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "(1S)1I", "Sh">;
84 def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "(1S>)1I", "Sh">;
85 def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "(1S>>)1I", "Sh">;
86 def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "(1U)1I", "Sh">;
87 def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "(1U>)1I", "Sh">;
88 def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "(1U>>)1I", "Sh">;
89 }
90 // Comparison
91 def SCALAR_CMEQRH : SInst<"vceq", "(1U)11", "Sh">;
92 def SCALAR_CMEQZH : SInst<"vceqz", "(1U)1", "Sh">;
93 def SCALAR_CMGERH : SInst<"vcge", "(1U)11", "Sh">;
94 def SCALAR_CMGEZH : SInst<"vcgez", "(1U)1", "Sh">;
95 def SCALAR_CMGTRH : SInst<"vcgt", "(1U)11", "Sh">;
96 def SCALAR_CMGTZH : SInst<"vcgtz", "(1U)1", "Sh">;
97 def SCALAR_CMLERH : SInst<"vcle", "(1U)11", "Sh">;
98 def SCALAR_CMLEZH : SInst<"vclez", "(1U)1", "Sh">;
99 def SCALAR_CMLTH : SInst<"vclt", "(1U)11", "Sh">;
100 def SCALAR_CMLTZH : SInst<"vcltz", "(1U)1", "Sh">;
101
102 // Absolute Compare Mask Greater Than Or Equal
103 def SCALAR_FACGEH : IInst<"vcage", "(1U)11", "Sh">;
104 def SCALAR_FACLEH : IInst<"vcale", "(1U)11", "Sh">;
105
106 // Absolute Compare Mask Greater Than
107 def SCALAR_FACGT : IInst<"vcagt", "(1U)11", "Sh">;
108 def SCALAR_FACLT : IInst<"vcalt", "(1U)11", "Sh">;
109
110 // Scalar Absolute Value
111 def SCALAR_ABSH : SInst<"vabs", "11", "Sh">;
112
113 // Scalar Absolute Difference
114 def SCALAR_ABDH: IInst<"vabd", "111", "Sh">;
115
116 // Add/Sub
117 def VADDSH : SInst<"vadd", "111", "Sh">;
118 def VSUBHS : SInst<"vsub", "111", "Sh">;
119
120 // Max/Min
121 def VMAXHS : SInst<"vmax", "111", "Sh">;
122 def VMINHS : SInst<"vmin", "111", "Sh">;
123 def FMAXNMHS : SInst<"vmaxnm", "111", "Sh">;
124 def FMINNMHS : SInst<"vminnm", "111", "Sh">;
125
126 // Multiplication/Division
127 def VMULHS : SInst<"vmul", "111", "Sh">;
128 def MULXHS : SInst<"vmulx", "111", "Sh">;
129 def FDIVHS : SInst<"vdiv", "111", "Sh">;
130
131 // Vector fused multiply-add operations
132 def VFMAHS : SInst<"vfma", "1111", "Sh">;
133 def VFMSHS : SInst<"vfms", "1111", "Sh">;
134}
135