1//===- llvm/CallingConvLower.h - Calling Conventions ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the CCState and CCValAssign classes, used for lowering
10// and implementing calling conventions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_CALLINGCONVLOWER_H
15#define LLVM_CODEGEN_CALLINGCONVLOWER_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/Register.h"
20#include "llvm/CodeGen/TargetCallingConv.h"
21#include "llvm/IR/CallingConv.h"
22#include "llvm/Support/Alignment.h"
23#include <variant>
24
25namespace llvm {
26
27class CCState;
28class MachineFunction;
29class MVT;
30class TargetRegisterInfo;
31
32/// CCValAssign - Represent assignment of one arg/retval to a location.
33class CCValAssign {
34public:
35 enum LocInfo {
36 Full, // The value fills the full location.
37 SExt, // The value is sign extended in the location.
38 ZExt, // The value is zero extended in the location.
39 AExt, // The value is extended with undefined upper bits.
40 SExtUpper, // The value is in the upper bits of the location and should be
41 // sign extended when retrieved.
42 ZExtUpper, // The value is in the upper bits of the location and should be
43 // zero extended when retrieved.
44 AExtUpper, // The value is in the upper bits of the location and should be
45 // extended with undefined upper bits when retrieved.
46 BCvt, // The value is bit-converted in the location.
47 Trunc, // The value is truncated in the location.
48 VExt, // The value is vector-widened in the location.
49 // FIXME: Not implemented yet. Code that uses AExt to mean
50 // vector-widen should be fixed to use VExt instead.
51 FPExt, // The floating-point value is fp-extended in the location.
52 Indirect // The location contains pointer to the value.
53 // TODO: a subset of the value is in the location.
54 };
55
56private:
57 // Holds one of:
58 // - the register that the value is assigned to;
59 // - the memory offset at which the value resides;
60 // - additional information about pending location; the exact interpretation
61 // of the data is target-dependent.
62 std::variant<Register, int64_t, unsigned> Data;
63
64 /// ValNo - This is the value number being assigned (e.g. an argument number).
65 unsigned ValNo;
66
67 /// isCustom - True if this arg/retval requires special handling.
68 unsigned isCustom : 1;
69
70 /// Information about how the value is assigned.
71 LocInfo HTP : 6;
72
73 /// ValVT - The type of the value being assigned.
74 MVT ValVT;
75
76 /// LocVT - The type of the location being assigned to.
77 MVT LocVT;
78
79 CCValAssign(LocInfo HTP, unsigned ValNo, MVT ValVT, MVT LocVT, bool IsCustom)
80 : ValNo(ValNo), isCustom(IsCustom), HTP(HTP), ValVT(ValVT), LocVT(LocVT) {
81 }
82
83public:
84 static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo,
85 MVT LocVT, LocInfo HTP, bool IsCustom = false) {
86 CCValAssign Ret(HTP, ValNo, ValVT, LocVT, IsCustom);
87 Ret.Data = Register(RegNo);
88 return Ret;
89 }
90
91 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo,
92 MVT LocVT, LocInfo HTP) {
93 return getReg(ValNo, ValVT, RegNo, LocVT, HTP, /*IsCustom=*/IsCustom: true);
94 }
95
96 static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset,
97 MVT LocVT, LocInfo HTP, bool IsCustom = false) {
98 CCValAssign Ret(HTP, ValNo, ValVT, LocVT, IsCustom);
99 Ret.Data = Offset;
100 return Ret;
101 }
102
103 static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, int64_t Offset,
104 MVT LocVT, LocInfo HTP) {
105 return getMem(ValNo, ValVT, Offset, LocVT, HTP, /*IsCustom=*/IsCustom: true);
106 }
107
108 static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT,
109 LocInfo HTP, unsigned ExtraInfo = 0) {
110 CCValAssign Ret(HTP, ValNo, ValVT, LocVT, false);
111 Ret.Data = ExtraInfo;
112 return Ret;
113 }
114
115 void convertToReg(unsigned RegNo) { Data = Register(RegNo); }
116
117 void convertToMem(int64_t Offset) { Data = Offset; }
118
119 unsigned getValNo() const { return ValNo; }
120 MVT getValVT() const { return ValVT; }
121
122 bool isRegLoc() const { return std::holds_alternative<Register>(v: Data); }
123 bool isMemLoc() const { return std::holds_alternative<int64_t>(v: Data); }
124 bool isPendingLoc() const { return std::holds_alternative<unsigned>(v: Data); }
125
126 bool needsCustom() const { return isCustom; }
127
128 Register getLocReg() const { return std::get<Register>(v: Data); }
129 int64_t getLocMemOffset() const { return std::get<int64_t>(v: Data); }
130 unsigned getExtraInfo() const { return std::get<unsigned>(v: Data); }
131
132 MVT getLocVT() const { return LocVT; }
133
134 LocInfo getLocInfo() const { return HTP; }
135 bool isExtInLoc() const {
136 return (HTP == AExt || HTP == SExt || HTP == ZExt);
137 }
138
139 bool isUpperBitsInLoc() const {
140 return HTP == AExtUpper || HTP == SExtUpper || HTP == ZExtUpper;
141 }
142};
143
144/// Describes a register that needs to be forwarded from the prologue to a
145/// musttail call.
146struct ForwardedRegister {
147 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT)
148 : VReg(VReg), PReg(PReg), VT(VT) {}
149 Register VReg;
150 MCPhysReg PReg;
151 MVT VT;
152};
153
154/// CCAssignFn - This function assigns a location for Val, updating State to
155/// reflect the change. It returns 'true' if it failed to handle Val.
156typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
157 MVT LocVT, CCValAssign::LocInfo LocInfo,
158 ISD::ArgFlagsTy ArgFlags, CCState &State);
159
160/// CCCustomFn - This function assigns a location for Val, possibly updating
161/// all args to reflect changes and indicates if it handled it. It must set
162/// isCustom if it handles the arg and returns true.
163typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
164 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
165 ISD::ArgFlagsTy &ArgFlags, CCState &State);
166
167/// CCState - This class holds information needed while lowering arguments and
168/// return values. It captures which registers are already assigned and which
169/// stack slots are used. It provides accessors to allocate these values.
170class CCState {
171private:
172 CallingConv::ID CallingConv;
173 bool IsVarArg;
174 bool AnalyzingMustTailForwardedRegs = false;
175 MachineFunction &MF;
176 const TargetRegisterInfo &TRI;
177 SmallVectorImpl<CCValAssign> &Locs;
178 LLVMContext &Context;
179 // True if arguments should be allocated at negative offsets.
180 bool NegativeOffsets;
181
182 uint64_t StackSize;
183 Align MaxStackArgAlign;
184 SmallVector<uint32_t, 16> UsedRegs;
185 SmallVector<CCValAssign, 4> PendingLocs;
186 SmallVector<ISD::ArgFlagsTy, 4> PendingArgFlags;
187
188 // ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
189 //
190 // Vector of ByValInfo instances (ByValRegs) is introduced for byval registers
191 // tracking.
192 // Or, in another words it tracks byval parameters that are stored in
193 // general purpose registers.
194 //
195 // For 4 byte stack alignment,
196 // instance index means byval parameter number in formal
197 // arguments set. Assume, we have some "struct_type" with size = 4 bytes,
198 // then, for function "foo":
199 //
200 // i32 foo(i32 %p, %struct_type* %r, i32 %s, %struct_type* %t)
201 //
202 // ByValRegs[0] describes how "%r" is stored (Begin == r1, End == r2)
203 // ByValRegs[1] describes how "%t" is stored (Begin == r3, End == r4).
204 //
205 // In case of 8 bytes stack alignment,
206 // In function shown above, r3 would be wasted according to AAPCS rules.
207 // ByValRegs vector size still would be 2,
208 // while "%t" goes to the stack: it wouldn't be described in ByValRegs.
209 //
210 // Supposed use-case for this collection:
211 // 1. Initially ByValRegs is empty, InRegsParamsProcessed is 0.
212 // 2. HandleByVal fills up ByValRegs.
213 // 3. Argument analysis (LowerFormatArguments, for example). After
214 // some byval argument was analyzed, InRegsParamsProcessed is increased.
215 struct ByValInfo {
216 ByValInfo(unsigned B, unsigned E) : Begin(B), End(E) {}
217
218 // First register allocated for current parameter.
219 unsigned Begin;
220
221 // First after last register allocated for current parameter.
222 unsigned End;
223 };
224 SmallVector<ByValInfo, 4 > ByValRegs;
225
226 // InRegsParamsProcessed - shows how many instances of ByValRegs was proceed
227 // during argument analysis.
228 unsigned InRegsParamsProcessed;
229
230public:
231 CCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
232 SmallVectorImpl<CCValAssign> &Locs, LLVMContext &Context,
233 bool NegativeOffsets = false);
234
235 void addLoc(const CCValAssign &V) {
236 Locs.push_back(Elt: V);
237 }
238
239 LLVMContext &getContext() const { return Context; }
240 MachineFunction &getMachineFunction() const { return MF; }
241 CallingConv::ID getCallingConv() const { return CallingConv; }
242 bool isVarArg() const { return IsVarArg; }
243
244 /// Returns the size of the currently allocated portion of the stack.
245 uint64_t getStackSize() const { return StackSize; }
246
247 /// getAlignedCallFrameSize - Return the size of the call frame needed to
248 /// be able to store all arguments and such that the alignment requirement
249 /// of each of the arguments is satisfied.
250 uint64_t getAlignedCallFrameSize() const {
251 return alignTo(Size: StackSize, A: MaxStackArgAlign);
252 }
253
254 /// isAllocated - Return true if the specified register (or an alias) is
255 /// allocated.
256 bool isAllocated(MCRegister Reg) const {
257 return UsedRegs[Reg / 32] & (1 << (Reg & 31));
258 }
259
260 /// AnalyzeFormalArguments - Analyze an array of argument values,
261 /// incorporating info about the formals into this state.
262 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
263 CCAssignFn Fn);
264
265 /// The function will invoke AnalyzeFormalArguments.
266 void AnalyzeArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
267 CCAssignFn Fn) {
268 AnalyzeFormalArguments(Ins, Fn);
269 }
270
271 /// AnalyzeReturn - Analyze the returned values of a return,
272 /// incorporating info about the result values into this state.
273 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
274 CCAssignFn Fn);
275
276 /// CheckReturn - Analyze the return values of a function, returning
277 /// true if the return can be performed without sret-demotion, and
278 /// false otherwise.
279 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
280 CCAssignFn Fn);
281
282 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
283 /// incorporating info about the passed values into this state.
284 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
285 CCAssignFn Fn);
286
287 /// AnalyzeCallOperands - Same as above except it takes vectors of types
288 /// and argument flags.
289 void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
290 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
291 CCAssignFn Fn);
292
293 /// The function will invoke AnalyzeCallOperands.
294 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs,
295 CCAssignFn Fn) {
296 AnalyzeCallOperands(Outs, Fn);
297 }
298
299 /// AnalyzeCallResult - Analyze the return values of a call,
300 /// incorporating info about the passed values into this state.
301 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
302 CCAssignFn Fn);
303
304 /// A shadow allocated register is a register that was allocated
305 /// but wasn't added to the location list (Locs).
306 /// \returns true if the register was allocated as shadow or false otherwise.
307 bool IsShadowAllocatedReg(MCRegister Reg) const;
308
309 /// AnalyzeCallResult - Same as above except it's specialized for calls which
310 /// produce a single value.
311 void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
312
313 /// getFirstUnallocated - Return the index of the first unallocated register
314 /// in the set, or Regs.size() if they are all allocated.
315 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
316 for (unsigned i = 0; i < Regs.size(); ++i)
317 if (!isAllocated(Reg: Regs[i]))
318 return i;
319 return Regs.size();
320 }
321
322 void DeallocateReg(MCPhysReg Reg) {
323 assert(isAllocated(Reg) && "Trying to deallocate an unallocated register");
324 MarkUnallocated(Reg);
325 }
326
327 /// AllocateReg - Attempt to allocate one register. If it is not available,
328 /// return zero. Otherwise, return the register, marking it and any aliases
329 /// as allocated.
330 MCRegister AllocateReg(MCPhysReg Reg) {
331 if (isAllocated(Reg))
332 return MCRegister();
333 MarkAllocated(Reg);
334 return Reg;
335 }
336
337 /// Version of AllocateReg with extra register to be shadowed.
338 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) {
339 if (isAllocated(Reg))
340 return MCRegister();
341 MarkAllocated(Reg);
342 MarkAllocated(Reg: ShadowReg);
343 return Reg;
344 }
345
346 /// AllocateReg - Attempt to allocate one of the specified registers. If none
347 /// are available, return zero. Otherwise, return the first one available,
348 /// marking it and any aliases as allocated.
349 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) {
350 unsigned FirstUnalloc = getFirstUnallocated(Regs);
351 if (FirstUnalloc == Regs.size())
352 return MCRegister(); // Didn't find the reg.
353
354 // Mark the register and any aliases as allocated.
355 MCPhysReg Reg = Regs[FirstUnalloc];
356 MarkAllocated(Reg);
357 return Reg;
358 }
359
360 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
361 /// registers. If this is not possible, return zero. Otherwise, return the first
362 /// register of the block that were allocated, marking the entire block as allocated.
363 MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
364 if (RegsRequired > Regs.size())
365 return 0;
366
367 for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
368 ++StartIdx) {
369 bool BlockAvailable = true;
370 // Check for already-allocated regs in this block
371 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
372 if (isAllocated(Reg: Regs[StartIdx + BlockIdx])) {
373 BlockAvailable = false;
374 break;
375 }
376 }
377 if (BlockAvailable) {
378 // Mark the entire block as allocated
379 for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
380 MarkAllocated(Reg: Regs[StartIdx + BlockIdx]);
381 }
382 return Regs[StartIdx];
383 }
384 }
385 // No block was available
386 return 0;
387 }
388
389 /// Version of AllocateReg with list of registers to be shadowed.
390 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
391 unsigned FirstUnalloc = getFirstUnallocated(Regs);
392 if (FirstUnalloc == Regs.size())
393 return MCRegister(); // Didn't find the reg.
394
395 // Mark the register and any aliases as allocated.
396 MCRegister Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
397 MarkAllocated(Reg);
398 MarkAllocated(Reg: ShadowReg);
399 return Reg;
400 }
401
402 /// AllocateStack - Allocate a chunk of stack space with the specified size
403 /// and alignment.
404 int64_t AllocateStack(unsigned Size, Align Alignment) {
405 int64_t Offset;
406 if (NegativeOffsets) {
407 StackSize = alignTo(Size: StackSize + Size, A: Alignment);
408 Offset = -StackSize;
409 } else {
410 Offset = alignTo(Size: StackSize, A: Alignment);
411 StackSize = Offset + Size;
412 }
413 MaxStackArgAlign = std::max(a: Alignment, b: MaxStackArgAlign);
414 ensureMaxAlignment(Alignment);
415 return Offset;
416 }
417
418 void ensureMaxAlignment(Align Alignment);
419
420 /// Version of AllocateStack with list of extra registers to be shadowed.
421 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
422 int64_t AllocateStack(unsigned Size, Align Alignment,
423 ArrayRef<MCPhysReg> ShadowRegs) {
424 for (MCPhysReg Reg : ShadowRegs)
425 MarkAllocated(Reg);
426 return AllocateStack(Size, Alignment);
427 }
428
429 // HandleByVal - Allocate a stack slot large enough to pass an argument by
430 // value. The size and alignment information of the argument is encoded in its
431 // parameter attribute.
432 void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
433 CCValAssign::LocInfo LocInfo, int MinSize, Align MinAlign,
434 ISD::ArgFlagsTy ArgFlags);
435
436 // Returns count of byval arguments that are to be stored (even partly)
437 // in registers.
438 unsigned getInRegsParamsCount() const { return ByValRegs.size(); }
439
440 // Returns count of byval in-regs arguments processed.
441 unsigned getInRegsParamsProcessed() const { return InRegsParamsProcessed; }
442
443 // Get information about N-th byval parameter that is stored in registers.
444 // Here "ByValParamIndex" is N.
445 void getInRegsParamInfo(unsigned InRegsParamRecordIndex,
446 unsigned& BeginReg, unsigned& EndReg) const {
447 assert(InRegsParamRecordIndex < ByValRegs.size() &&
448 "Wrong ByVal parameter index");
449
450 const ByValInfo& info = ByValRegs[InRegsParamRecordIndex];
451 BeginReg = info.Begin;
452 EndReg = info.End;
453 }
454
455 // Add information about parameter that is kept in registers.
456 void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd) {
457 ByValRegs.push_back(Elt: ByValInfo(RegBegin, RegEnd));
458 }
459
460 // Goes either to next byval parameter (excluding "waste" record), or
461 // to the end of collection.
462 // Returns false, if end is reached.
463 bool nextInRegsParam() {
464 unsigned e = ByValRegs.size();
465 if (InRegsParamsProcessed < e)
466 ++InRegsParamsProcessed;
467 return InRegsParamsProcessed < e;
468 }
469
470 // Clear byval registers tracking info.
471 void clearByValRegsInfo() {
472 InRegsParamsProcessed = 0;
473 ByValRegs.clear();
474 }
475
476 // Rewind byval registers tracking info.
477 void rewindByValRegsInfo() {
478 InRegsParamsProcessed = 0;
479 }
480
481 // Get list of pending assignments
482 SmallVectorImpl<CCValAssign> &getPendingLocs() {
483 return PendingLocs;
484 }
485
486 // Get a list of argflags for pending assignments.
487 SmallVectorImpl<ISD::ArgFlagsTy> &getPendingArgFlags() {
488 return PendingArgFlags;
489 }
490
491 /// Compute the remaining unused register parameters that would be used for
492 /// the given value type. This is useful when varargs are passed in the
493 /// registers that normal prototyped parameters would be passed in, or for
494 /// implementing perfect forwarding.
495 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
496 CCAssignFn Fn);
497
498 /// Compute the set of registers that need to be preserved and forwarded to
499 /// any musttail calls.
500 void analyzeMustTailForwardedRegisters(
501 SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
502 CCAssignFn Fn);
503
504 /// Returns true if the results of the two calling conventions are compatible.
505 /// This is usually part of the check for tailcall eligibility.
506 static bool resultsCompatible(CallingConv::ID CalleeCC,
507 CallingConv::ID CallerCC, MachineFunction &MF,
508 LLVMContext &C,
509 const SmallVectorImpl<ISD::InputArg> &Ins,
510 CCAssignFn CalleeFn, CCAssignFn CallerFn);
511
512 /// The function runs an additional analysis pass over function arguments.
513 /// It will mark each argument with the attribute flag SecArgPass.
514 /// After running, it will sort the locs list.
515 template <class T>
516 void AnalyzeArgumentsSecondPass(const SmallVectorImpl<T> &Args,
517 CCAssignFn Fn) {
518 unsigned NumFirstPassLocs = Locs.size();
519
520 /// Creates similar argument list to \p Args in which each argument is
521 /// marked using SecArgPass flag.
522 SmallVector<T, 16> SecPassArg;
523 // SmallVector<ISD::InputArg, 16> SecPassArg;
524 for (auto Arg : Args) {
525 Arg.Flags.setSecArgPass();
526 SecPassArg.push_back(Arg);
527 }
528
529 // Run the second argument pass
530 AnalyzeArguments(SecPassArg, Fn);
531
532 // Sort the locations of the arguments according to their original position.
533 SmallVector<CCValAssign, 16> TmpArgLocs;
534 TmpArgLocs.swap(RHS&: Locs);
535 auto B = TmpArgLocs.begin(), E = TmpArgLocs.end();
536 std::merge(B, B + NumFirstPassLocs, B + NumFirstPassLocs, E,
537 std::back_inserter(x&: Locs),
538 [](const CCValAssign &A, const CCValAssign &B) -> bool {
539 return A.getValNo() < B.getValNo();
540 });
541 }
542
543private:
544 /// MarkAllocated - Mark a register and all of its aliases as allocated.
545 void MarkAllocated(MCPhysReg Reg);
546
547 void MarkUnallocated(MCPhysReg Reg);
548};
549
550} // end namespace llvm
551
552#endif // LLVM_CODEGEN_CALLINGCONVLOWER_H
553

source code of llvm/include/llvm/CodeGen/CallingConvLower.h