1//===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
2// combiner ------*- C++ -*-===//
3//
4// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5// See https://llvm.org/LICENSE.txt for license information.
6// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines instruction pattern supported by combiner
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
15#define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
16
17namespace llvm {
18
19/// These are instruction patterns matched by the machine combiner pass.
20enum class MachineCombinerPattern {
21 // These are commutative variants for reassociating a computation chain. See
22 // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
23 REASSOC_AX_BY,
24 REASSOC_AX_YB,
25 REASSOC_XA_BY,
26 REASSOC_XA_YB,
27
28 // These are patterns matched by the PowerPC to reassociate FMA chains.
29 REASSOC_XY_AMM_BMM,
30 REASSOC_XMM_AMM_BMM,
31
32 // These are patterns matched by the PowerPC to reassociate FMA and FSUB to
33 // reduce register pressure.
34 REASSOC_XY_BCA,
35 REASSOC_XY_BAC,
36
37 // These are patterns used to reduce the length of dependence chain.
38 SUBADD_OP1,
39 SUBADD_OP2,
40
41 // These are multiply-add patterns matched by the AArch64 machine combiner.
42 MULADDW_OP1,
43 MULADDW_OP2,
44 MULSUBW_OP1,
45 MULSUBW_OP2,
46 MULADDWI_OP1,
47 MULSUBWI_OP1,
48 MULADDX_OP1,
49 MULADDX_OP2,
50 MULSUBX_OP1,
51 MULSUBX_OP2,
52 MULADDXI_OP1,
53 MULSUBXI_OP1,
54 // NEON integers vectors
55 MULADDv8i8_OP1,
56 MULADDv8i8_OP2,
57 MULADDv16i8_OP1,
58 MULADDv16i8_OP2,
59 MULADDv4i16_OP1,
60 MULADDv4i16_OP2,
61 MULADDv8i16_OP1,
62 MULADDv8i16_OP2,
63 MULADDv2i32_OP1,
64 MULADDv2i32_OP2,
65 MULADDv4i32_OP1,
66 MULADDv4i32_OP2,
67
68 MULSUBv8i8_OP1,
69 MULSUBv8i8_OP2,
70 MULSUBv16i8_OP1,
71 MULSUBv16i8_OP2,
72 MULSUBv4i16_OP1,
73 MULSUBv4i16_OP2,
74 MULSUBv8i16_OP1,
75 MULSUBv8i16_OP2,
76 MULSUBv2i32_OP1,
77 MULSUBv2i32_OP2,
78 MULSUBv4i32_OP1,
79 MULSUBv4i32_OP2,
80
81 MULADDv4i16_indexed_OP1,
82 MULADDv4i16_indexed_OP2,
83 MULADDv8i16_indexed_OP1,
84 MULADDv8i16_indexed_OP2,
85 MULADDv2i32_indexed_OP1,
86 MULADDv2i32_indexed_OP2,
87 MULADDv4i32_indexed_OP1,
88 MULADDv4i32_indexed_OP2,
89
90 MULSUBv4i16_indexed_OP1,
91 MULSUBv4i16_indexed_OP2,
92 MULSUBv8i16_indexed_OP1,
93 MULSUBv8i16_indexed_OP2,
94 MULSUBv2i32_indexed_OP1,
95 MULSUBv2i32_indexed_OP2,
96 MULSUBv4i32_indexed_OP1,
97 MULSUBv4i32_indexed_OP2,
98
99 // Floating Point
100 FMULADDH_OP1,
101 FMULADDH_OP2,
102 FMULSUBH_OP1,
103 FMULSUBH_OP2,
104 FMULADDS_OP1,
105 FMULADDS_OP2,
106 FMULSUBS_OP1,
107 FMULSUBS_OP2,
108 FMULADDD_OP1,
109 FMULADDD_OP2,
110 FMULSUBD_OP1,
111 FMULSUBD_OP2,
112 FNMULSUBH_OP1,
113 FNMULSUBS_OP1,
114 FNMULSUBD_OP1,
115 FMLAv1i32_indexed_OP1,
116 FMLAv1i32_indexed_OP2,
117 FMLAv1i64_indexed_OP1,
118 FMLAv1i64_indexed_OP2,
119 FMLAv4f16_OP1,
120 FMLAv4f16_OP2,
121 FMLAv8f16_OP1,
122 FMLAv8f16_OP2,
123 FMLAv2f32_OP2,
124 FMLAv2f32_OP1,
125 FMLAv2f64_OP1,
126 FMLAv2f64_OP2,
127 FMLAv4i16_indexed_OP1,
128 FMLAv4i16_indexed_OP2,
129 FMLAv8i16_indexed_OP1,
130 FMLAv8i16_indexed_OP2,
131 FMLAv2i32_indexed_OP1,
132 FMLAv2i32_indexed_OP2,
133 FMLAv2i64_indexed_OP1,
134 FMLAv2i64_indexed_OP2,
135 FMLAv4f32_OP1,
136 FMLAv4f32_OP2,
137 FMLAv4i32_indexed_OP1,
138 FMLAv4i32_indexed_OP2,
139 FMLSv1i32_indexed_OP2,
140 FMLSv1i64_indexed_OP2,
141 FMLSv4f16_OP1,
142 FMLSv4f16_OP2,
143 FMLSv8f16_OP1,
144 FMLSv8f16_OP2,
145 FMLSv2f32_OP1,
146 FMLSv2f32_OP2,
147 FMLSv2f64_OP1,
148 FMLSv2f64_OP2,
149 FMLSv4i16_indexed_OP1,
150 FMLSv4i16_indexed_OP2,
151 FMLSv8i16_indexed_OP1,
152 FMLSv8i16_indexed_OP2,
153 FMLSv2i32_indexed_OP1,
154 FMLSv2i32_indexed_OP2,
155 FMLSv2i64_indexed_OP1,
156 FMLSv2i64_indexed_OP2,
157 FMLSv4f32_OP1,
158 FMLSv4f32_OP2,
159 FMLSv4i32_indexed_OP1,
160 FMLSv4i32_indexed_OP2,
161
162 FMULv2i32_indexed_OP1,
163 FMULv2i32_indexed_OP2,
164 FMULv2i64_indexed_OP1,
165 FMULv2i64_indexed_OP2,
166 FMULv4i16_indexed_OP1,
167 FMULv4i16_indexed_OP2,
168 FMULv4i32_indexed_OP1,
169 FMULv4i32_indexed_OP2,
170 FMULv8i16_indexed_OP1,
171 FMULv8i16_indexed_OP2,
172
173 // RISCV FMADD, FMSUB, FNMSUB patterns
174 FMADD_AX,
175 FMADD_XA,
176 FMSUB,
177 FNMSUB,
178
179 // X86 VNNI
180 DPWSSD,
181
182 FNMADD,
183};
184
185} // end namespace llvm
186
187#endif
188

source code of llvm/include/llvm/CodeGen/MachineCombinerPattern.h