1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/SmallSet.h"
21#include "llvm/ADT/ilist.h"
22#include "llvm/ADT/ilist_node.h"
23#include "llvm/ADT/iterator_range.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineOperand.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/PseudoProbe.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Support/ArrayRecycler.h"
33#include "llvm/Support/TrailingObjects.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41class AAResults;
42template <typename T> class ArrayRef;
43class DIExpression;
44class DILocalVariable;
45class MachineBasicBlock;
46class MachineFunction;
47class MachineRegisterInfo;
48class ModuleSlotTracker;
49class raw_ostream;
50template <typename T> class SmallVectorImpl;
51class SmallBitVector;
52class StringRef;
53class TargetInstrInfo;
54class TargetRegisterClass;
55class TargetRegisterInfo;
56
57//===----------------------------------------------------------------------===//
58/// Representation of each machine instruction.
59///
60/// This class isn't a POD type, but it must have a trivial destructor. When a
61/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62/// without having their destructor called.
63///
64class MachineInstr
65 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
66 ilist_sentinel_tracking<true>> {
67public:
68 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
69
70 /// Flags to specify different kinds of comments to output in
71 /// assembly code. These flags carry semantic information not
72 /// otherwise easily derivable from the IR text.
73 ///
74 enum CommentFlag {
75 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
76 NoSchedComment = 0x2,
77 TAsmComments = 0x4 // Target Asm comments should start from this value.
78 };
79
80 enum MIFlag {
81 NoFlags = 0,
82 FrameSetup = 1 << 0, // Instruction is used as a part of
83 // function frame setup code.
84 FrameDestroy = 1 << 1, // Instruction is used as a part of
85 // function frame destruction code.
86 BundledPred = 1 << 2, // Instruction has bundled predecessors.
87 BundledSucc = 1 << 3, // Instruction has bundled successors.
88 FmNoNans = 1 << 4, // Instruction does not support Fast
89 // math nan values.
90 FmNoInfs = 1 << 5, // Instruction does not support Fast
91 // math infinity values.
92 FmNsz = 1 << 6, // Instruction is not required to retain
93 // signed zero values.
94 FmArcp = 1 << 7, // Instruction supports Fast math
95 // reciprocal approximations.
96 FmContract = 1 << 8, // Instruction supports Fast math
97 // contraction operations like fma.
98 FmAfn = 1 << 9, // Instruction may map to Fast math
99 // instrinsic approximation.
100 FmReassoc = 1 << 10, // Instruction supports Fast math
101 // reassociation of operand order.
102 NoUWrap = 1 << 11, // Instruction supports binary operator
103 // no unsigned wrap.
104 NoSWrap = 1 << 12, // Instruction supports binary operator
105 // no signed wrap.
106 IsExact = 1 << 13, // Instruction supports division is
107 // known to be exact.
108 NoFPExcept = 1 << 14, // Instruction does not raise
109 // floatint-point exceptions.
110 NoMerge = 1 << 15, // Passes that drop source location info
111 // (e.g. branch folding) should skip
112 // this instruction.
113 };
114
115private:
116 const MCInstrDesc *MCID; // Instruction descriptor.
117 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
118
119 // Operands are allocated by an ArrayRecycler.
120 MachineOperand *Operands = nullptr; // Pointer to the first operand.
121 unsigned NumOperands = 0; // Number of operands on instruction.
122
123 uint16_t Flags = 0; // Various bits of additional
124 // information about machine
125 // instruction.
126
127 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
128 // the AsmPrinter to emit helpful
129 // comments. This is *not* semantic
130 // information. Do not use this for
131 // anything other than to convey comment
132 // information to AsmPrinter.
133
134 // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
135 // to properly pack.
136 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
137 OperandCapacity CapOperands; // Capacity of the Operands array.
138
139 /// Internal implementation detail class that provides out-of-line storage for
140 /// extra info used by the machine instruction when this info cannot be stored
141 /// in-line within the instruction itself.
142 ///
143 /// This has to be defined eagerly due to the implementation constraints of
144 /// `PointerSumType` where it is used.
145 class ExtraInfo final
146 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
147 public:
148 static ExtraInfo *create(BumpPtrAllocator &Allocator,
149 ArrayRef<MachineMemOperand *> MMOs,
150 MCSymbol *PreInstrSymbol = nullptr,
151 MCSymbol *PostInstrSymbol = nullptr,
152 MDNode *HeapAllocMarker = nullptr) {
153 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
154 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
155 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
156 auto *Result = new (Allocator.Allocate(
157 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
158 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
159 HasHeapAllocMarker),
160 alignof(ExtraInfo)))
161 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
162 HasHeapAllocMarker);
163
164 // Copy the actual data into the trailing objects.
165 std::copy(MMOs.begin(), MMOs.end(),
166 Result->getTrailingObjects<MachineMemOperand *>());
167
168 if (HasPreInstrSymbol)
169 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
170 if (HasPostInstrSymbol)
171 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
172 PostInstrSymbol;
173 if (HasHeapAllocMarker)
174 Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
175
176 return Result;
177 }
178
179 ArrayRef<MachineMemOperand *> getMMOs() const {
180 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
181 }
182
183 MCSymbol *getPreInstrSymbol() const {
184 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
185 }
186
187 MCSymbol *getPostInstrSymbol() const {
188 return HasPostInstrSymbol
189 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
190 : nullptr;
191 }
192
193 MDNode *getHeapAllocMarker() const {
194 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
195 }
196
197 private:
198 friend TrailingObjects;
199
200 // Description of the extra info, used to interpret the actual optional
201 // data appended.
202 //
203 // Note that this is not terribly space optimized. This leaves a great deal
204 // of flexibility to fit more in here later.
205 const int NumMMOs;
206 const bool HasPreInstrSymbol;
207 const bool HasPostInstrSymbol;
208 const bool HasHeapAllocMarker;
209
210 // Implement the `TrailingObjects` internal API.
211 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
212 return NumMMOs;
213 }
214 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
215 return HasPreInstrSymbol + HasPostInstrSymbol;
216 }
217 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
218 return HasHeapAllocMarker;
219 }
220
221 // Just a boring constructor to allow us to initialize the sizes. Always use
222 // the `create` routine above.
223 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
224 bool HasHeapAllocMarker)
225 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
226 HasPostInstrSymbol(HasPostInstrSymbol),
227 HasHeapAllocMarker(HasHeapAllocMarker) {}
228 };
229
230 /// Enumeration of the kinds of inline extra info available. It is important
231 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
232 /// it accessible as an `ArrayRef`.
233 enum ExtraInfoInlineKinds {
234 EIIK_MMO = 0,
235 EIIK_PreInstrSymbol,
236 EIIK_PostInstrSymbol,
237 EIIK_OutOfLine
238 };
239
240 // We store extra information about the instruction here. The common case is
241 // expected to be nothing or a single pointer (typically a MMO or a symbol).
242 // We work to optimize this common case by storing it inline here rather than
243 // requiring a separate allocation, but we fall back to an allocation when
244 // multiple pointers are needed.
245 PointerSumType<ExtraInfoInlineKinds,
246 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
247 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
248 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
249 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
250 Info;
251
252 DebugLoc debugLoc; // Source line information.
253
254 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
255 /// defined by this instruction.
256 unsigned DebugInstrNum;
257
258 // Intrusive list support
259 friend struct ilist_traits<MachineInstr>;
260 friend struct ilist_callback_traits<MachineBasicBlock>;
261 void setParent(MachineBasicBlock *P) { Parent = P; }
262
263 /// This constructor creates a copy of the given
264 /// MachineInstr in the given MachineFunction.
265 MachineInstr(MachineFunction &, const MachineInstr &);
266
267 /// This constructor create a MachineInstr and add the implicit operands.
268 /// It reserves space for number of operands specified by
269 /// MCInstrDesc. An explicit DebugLoc is supplied.
270 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
271 bool NoImp = false);
272
273 // MachineInstrs are pool-allocated and owned by MachineFunction.
274 friend class MachineFunction;
275
276 void
277 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
278 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
279
280public:
281 MachineInstr(const MachineInstr &) = delete;
282 MachineInstr &operator=(const MachineInstr &) = delete;
283 // Use MachineFunction::DeleteMachineInstr() instead.
284 ~MachineInstr() = delete;
285
286 const MachineBasicBlock* getParent() const { return Parent; }
287 MachineBasicBlock* getParent() { return Parent; }
288
289 /// Move the instruction before \p MovePos.
290 void moveBefore(MachineInstr *MovePos);
291
292 /// Return the function that contains the basic block that this instruction
293 /// belongs to.
294 ///
295 /// Note: this is undefined behaviour if the instruction does not have a
296 /// parent.
297 const MachineFunction *getMF() const;
298 MachineFunction *getMF() {
299 return const_cast<MachineFunction *>(
300 static_cast<const MachineInstr *>(this)->getMF());
301 }
302
303 /// Return the asm printer flags bitvector.
304 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
305
306 /// Clear the AsmPrinter bitvector.
307 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
308
309 /// Return whether an AsmPrinter flag is set.
310 bool getAsmPrinterFlag(CommentFlag Flag) const {
311 return AsmPrinterFlags & Flag;
312 }
313
314 /// Set a flag for the AsmPrinter.
315 void setAsmPrinterFlag(uint8_t Flag) {
316 AsmPrinterFlags |= Flag;
317 }
318
319 /// Clear specific AsmPrinter flags.
320 void clearAsmPrinterFlag(CommentFlag Flag) {
321 AsmPrinterFlags &= ~Flag;
322 }
323
324 /// Return the MI flags bitvector.
325 uint16_t getFlags() const {
326 return Flags;
327 }
328
329 /// Return whether an MI flag is set.
330 bool getFlag(MIFlag Flag) const {
331 return Flags & Flag;
332 }
333
334 /// Set a MI flag.
335 void setFlag(MIFlag Flag) {
336 Flags |= (uint16_t)Flag;
337 }
338
339 void setFlags(unsigned flags) {
340 // Filter out the automatically maintained flags.
341 unsigned Mask = BundledPred | BundledSucc;
342 Flags = (Flags & Mask) | (flags & ~Mask);
343 }
344
345 /// clearFlag - Clear a MI flag.
346 void clearFlag(MIFlag Flag) {
347 Flags &= ~((uint16_t)Flag);
348 }
349
350 /// Return true if MI is in a bundle (but not the first MI in a bundle).
351 ///
352 /// A bundle looks like this before it's finalized:
353 /// ----------------
354 /// | MI |
355 /// ----------------
356 /// |
357 /// ----------------
358 /// | MI * |
359 /// ----------------
360 /// |
361 /// ----------------
362 /// | MI * |
363 /// ----------------
364 /// In this case, the first MI starts a bundle but is not inside a bundle, the
365 /// next 2 MIs are considered "inside" the bundle.
366 ///
367 /// After a bundle is finalized, it looks like this:
368 /// ----------------
369 /// | Bundle |
370 /// ----------------
371 /// |
372 /// ----------------
373 /// | MI * |
374 /// ----------------
375 /// |
376 /// ----------------
377 /// | MI * |
378 /// ----------------
379 /// |
380 /// ----------------
381 /// | MI * |
382 /// ----------------
383 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
384 /// a bundle, but the next three MIs are.
385 bool isInsideBundle() const {
386 return getFlag(BundledPred);
387 }
388
389 /// Return true if this instruction part of a bundle. This is true
390 /// if either itself or its following instruction is marked "InsideBundle".
391 bool isBundled() const {
392 return isBundledWithPred() || isBundledWithSucc();
393 }
394
395 /// Return true if this instruction is part of a bundle, and it is not the
396 /// first instruction in the bundle.
397 bool isBundledWithPred() const { return getFlag(BundledPred); }
398
399 /// Return true if this instruction is part of a bundle, and it is not the
400 /// last instruction in the bundle.
401 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
402
403 /// Bundle this instruction with its predecessor. This can be an unbundled
404 /// instruction, or it can be the first instruction in a bundle.
405 void bundleWithPred();
406
407 /// Bundle this instruction with its successor. This can be an unbundled
408 /// instruction, or it can be the last instruction in a bundle.
409 void bundleWithSucc();
410
411 /// Break bundle above this instruction.
412 void unbundleFromPred();
413
414 /// Break bundle below this instruction.
415 void unbundleFromSucc();
416
417 /// Returns the debug location id of this MachineInstr.
418 const DebugLoc &getDebugLoc() const { return debugLoc; }
419
420 /// Return the operand containing the offset to be used if this DBG_VALUE
421 /// instruction is indirect; will be an invalid register if this value is
422 /// not indirect, and an immediate with value 0 otherwise.
423 const MachineOperand &getDebugOffset() const {
424 assert(isNonListDebugValue() && "not a DBG_VALUE");
425 return getOperand(1);
426 }
427 MachineOperand &getDebugOffset() {
428 assert(isNonListDebugValue() && "not a DBG_VALUE");
429 return getOperand(1);
430 }
431
432 /// Return the operand for the debug variable referenced by
433 /// this DBG_VALUE instruction.
434 const MachineOperand &getDebugVariableOp() const;
435 MachineOperand &getDebugVariableOp();
436
437 /// Return the debug variable referenced by
438 /// this DBG_VALUE instruction.
439 const DILocalVariable *getDebugVariable() const;
440
441 /// Return the operand for the complex address expression referenced by
442 /// this DBG_VALUE instruction.
443 const MachineOperand &getDebugExpressionOp() const;
444 MachineOperand &getDebugExpressionOp();
445
446 /// Return the complex address expression referenced by
447 /// this DBG_VALUE instruction.
448 const DIExpression *getDebugExpression() const;
449
450 /// Return the debug label referenced by
451 /// this DBG_LABEL instruction.
452 const DILabel *getDebugLabel() const;
453
454 /// Fetch the instruction number of this MachineInstr. If it does not have
455 /// one already, a new and unique number will be assigned.
456 unsigned getDebugInstrNum();
457
458 /// Examine the instruction number of this MachineInstr. May be zero if
459 /// it hasn't been assigned a number yet.
460 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
461
462 /// Set instruction number of this MachineInstr. Avoid using unless you're
463 /// deserializing this information.
464 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
465
466 /// Emit an error referring to the source location of this instruction.
467 /// This should only be used for inline assembly that is somehow
468 /// impossible to compile. Other errors should have been handled much
469 /// earlier.
470 ///
471 /// If this method returns, the caller should try to recover from the error.
472 void emitError(StringRef Msg) const;
473
474 /// Returns the target instruction descriptor of this MachineInstr.
475 const MCInstrDesc &getDesc() const { return *MCID; }
476
477 /// Returns the opcode of this MachineInstr.
478 unsigned getOpcode() const { return MCID->Opcode; }
479
480 /// Retuns the total number of operands.
481 unsigned getNumOperands() const { return NumOperands; }
482
483 /// Returns the total number of operands which are debug locations.
484 unsigned getNumDebugOperands() const {
485 return std::distance(debug_operands().begin(), debug_operands().end());
486 }
487
488 const MachineOperand& getOperand(unsigned i) const {
489 assert(i < getNumOperands() && "getOperand() out of range!");
490 return Operands[i];
491 }
492 MachineOperand& getOperand(unsigned i) {
493 assert(i < getNumOperands() && "getOperand() out of range!");
494 return Operands[i];
495 }
496
497 MachineOperand &getDebugOperand(unsigned Index) {
498 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
499 return *(debug_operands().begin() + Index);
500 }
501 const MachineOperand &getDebugOperand(unsigned Index) const {
502 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
503 return *(debug_operands().begin() + Index);
504 }
505
506 SmallSet<Register, 4> getUsedDebugRegs() const {
507 assert(isDebugValue() && "not a DBG_VALUE*");
508 SmallSet<Register, 4> UsedRegs;
509 for (auto MO : debug_operands())
510 if (MO.isReg() && MO.getReg())
511 UsedRegs.insert(MO.getReg());
512 return UsedRegs;
513 }
514
515 /// Returns whether this debug value has at least one debug operand with the
516 /// register \p Reg.
517 bool hasDebugOperandForReg(Register Reg) const {
518 return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
519 return Op.isReg() && Op.getReg() == Reg;
520 });
521 }
522
523 /// Returns a range of all of the operands that correspond to a debug use of
524 /// \p Reg.
525 template <typename Operand, typename Instruction>
526 static iterator_range<
527 filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
528 getDebugOperandsForReg(Instruction *MI, Register Reg) {
529 std::function<bool(Operand & Op)> OpUsesReg(
530 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
531 return make_filter_range(MI->debug_operands(), OpUsesReg);
532 }
533 iterator_range<filter_iterator<const MachineOperand *,
534 std::function<bool(const MachineOperand &Op)>>>
535 getDebugOperandsForReg(Register Reg) const {
536 return MachineInstr::getDebugOperandsForReg<const MachineOperand,
537 const MachineInstr>(this, Reg);
538 }
539 iterator_range<filter_iterator<MachineOperand *,
540 std::function<bool(MachineOperand &Op)>>>
541 getDebugOperandsForReg(Register Reg) {
542 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
543 this, Reg);
544 }
545
546 bool isDebugOperand(const MachineOperand *Op) const {
547 return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
548 }
549
550 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
551 assert(isDebugOperand(Op) && "Expected a debug operand.");
552 return std::distance(adl_begin(debug_operands()), Op);
553 }
554
555 /// Returns the total number of definitions.
556 unsigned getNumDefs() const {
557 return getNumExplicitDefs() + MCID->getNumImplicitDefs();
558 }
559
560 /// Returns true if the instruction has implicit definition.
561 bool hasImplicitDef() const {
562 for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
563 I != E; ++I) {
564 const MachineOperand &MO = getOperand(I);
565 if (MO.isDef() && MO.isImplicit())
566 return true;
567 }
568 return false;
569 }
570
571 /// Returns the implicit operands number.
572 unsigned getNumImplicitOperands() const {
573 return getNumOperands() - getNumExplicitOperands();
574 }
575
576 /// Return true if operand \p OpIdx is a subregister index.
577 bool isOperandSubregIdx(unsigned OpIdx) const {
578 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
579 "Expected MO_Immediate operand type.");
580 if (isExtractSubreg() && OpIdx == 2)
581 return true;
582 if (isInsertSubreg() && OpIdx == 3)
583 return true;
584 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
585 return true;
586 if (isSubregToReg() && OpIdx == 3)
587 return true;
588 return false;
589 }
590
591 /// Returns the number of non-implicit operands.
592 unsigned getNumExplicitOperands() const;
593
594 /// Returns the number of non-implicit definitions.
595 unsigned getNumExplicitDefs() const;
596
597 /// iterator/begin/end - Iterate over all operands of a machine instruction.
598 using mop_iterator = MachineOperand *;
599 using const_mop_iterator = const MachineOperand *;
600
601 mop_iterator operands_begin() { return Operands; }
602 mop_iterator operands_end() { return Operands + NumOperands; }
603
604 const_mop_iterator operands_begin() const { return Operands; }
605 const_mop_iterator operands_end() const { return Operands + NumOperands; }
606
607 iterator_range<mop_iterator> operands() {
608 return make_range(operands_begin(), operands_end());
609 }
610 iterator_range<const_mop_iterator> operands() const {
611 return make_range(operands_begin(), operands_end());
612 }
613 iterator_range<mop_iterator> explicit_operands() {
614 return make_range(operands_begin(),
615 operands_begin() + getNumExplicitOperands());
616 }
617 iterator_range<const_mop_iterator> explicit_operands() const {
618 return make_range(operands_begin(),
619 operands_begin() + getNumExplicitOperands());
620 }
621 iterator_range<mop_iterator> implicit_operands() {
622 return make_range(explicit_operands().end(), operands_end());
623 }
624 iterator_range<const_mop_iterator> implicit_operands() const {
625 return make_range(explicit_operands().end(), operands_end());
626 }
627 /// Returns a range over all operands that are used to determine the variable
628 /// location for this DBG_VALUE instruction.
629 iterator_range<mop_iterator> debug_operands() {
630 assert(isDebugValue() && "Must be a debug value instruction.");
631 return isDebugValueList()
632 ? make_range(operands_begin() + 2, operands_end())
633 : make_range(operands_begin(), operands_begin() + 1);
634 }
635 /// \copydoc debug_operands()
636 iterator_range<const_mop_iterator> debug_operands() const {
637 assert(isDebugValue() && "Must be a debug value instruction.");
638 return isDebugValueList()
639 ? make_range(operands_begin() + 2, operands_end())
640 : make_range(operands_begin(), operands_begin() + 1);
641 }
642 /// Returns a range over all explicit operands that are register definitions.
643 /// Implicit definition are not included!
644 iterator_range<mop_iterator> defs() {
645 return make_range(operands_begin(),
646 operands_begin() + getNumExplicitDefs());
647 }
648 /// \copydoc defs()
649 iterator_range<const_mop_iterator> defs() const {
650 return make_range(operands_begin(),
651 operands_begin() + getNumExplicitDefs());
652 }
653 /// Returns a range that includes all operands that are register uses.
654 /// This may include unrelated operands which are not register uses.
655 iterator_range<mop_iterator> uses() {
656 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
657 }
658 /// \copydoc uses()
659 iterator_range<const_mop_iterator> uses() const {
660 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
661 }
662 iterator_range<mop_iterator> explicit_uses() {
663 return make_range(operands_begin() + getNumExplicitDefs(),
664 operands_begin() + getNumExplicitOperands());
665 }
666 iterator_range<const_mop_iterator> explicit_uses() const {
667 return make_range(operands_begin() + getNumExplicitDefs(),
668 operands_begin() + getNumExplicitOperands());
669 }
670
671 /// Returns the number of the operand iterator \p I points to.
672 unsigned getOperandNo(const_mop_iterator I) const {
673 return I - operands_begin();
674 }
675
676 /// Access to memory operands of the instruction. If there are none, that does
677 /// not imply anything about whether the function accesses memory. Instead,
678 /// the caller must behave conservatively.
679 ArrayRef<MachineMemOperand *> memoperands() const {
680 if (!Info)
681 return {};
682
683 if (Info.is<EIIK_MMO>())
684 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
685
686 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
687 return EI->getMMOs();
688
689 return {};
690 }
691
692 /// Access to memory operands of the instruction.
693 ///
694 /// If `memoperands_begin() == memoperands_end()`, that does not imply
695 /// anything about whether the function accesses memory. Instead, the caller
696 /// must behave conservatively.
697 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
698
699 /// Access to memory operands of the instruction.
700 ///
701 /// If `memoperands_begin() == memoperands_end()`, that does not imply
702 /// anything about whether the function accesses memory. Instead, the caller
703 /// must behave conservatively.
704 mmo_iterator memoperands_end() const { return memoperands().end(); }
705
706 /// Return true if we don't have any memory operands which described the
707 /// memory access done by this instruction. If this is true, calling code
708 /// must be conservative.
709 bool memoperands_empty() const { return memoperands().empty(); }
710
711 /// Return true if this instruction has exactly one MachineMemOperand.
712 bool hasOneMemOperand() const { return memoperands().size() == 1; }
713
714 /// Return the number of memory operands.
715 unsigned getNumMemOperands() const { return memoperands().size(); }
716
717 /// Helper to extract a pre-instruction symbol if one has been added.
718 MCSymbol *getPreInstrSymbol() const {
719 if (!Info)
720 return nullptr;
721 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
722 return S;
723 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
724 return EI->getPreInstrSymbol();
725
726 return nullptr;
727 }
728
729 /// Helper to extract a post-instruction symbol if one has been added.
730 MCSymbol *getPostInstrSymbol() const {
731 if (!Info)
732 return nullptr;
733 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
734 return S;
735 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
736 return EI->getPostInstrSymbol();
737
738 return nullptr;
739 }
740
741 /// Helper to extract a heap alloc marker if one has been added.
742 MDNode *getHeapAllocMarker() const {
743 if (!Info)
744 return nullptr;
745 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
746 return EI->getHeapAllocMarker();
747
748 return nullptr;
749 }
750
751 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
752 /// queries but they are bundle aware.
753
754 enum QueryType {
755 IgnoreBundle, // Ignore bundles
756 AnyInBundle, // Return true if any instruction in bundle has property
757 AllInBundle // Return true if all instructions in bundle have property
758 };
759
760 /// Return true if the instruction (or in the case of a bundle,
761 /// the instructions inside the bundle) has the specified property.
762 /// The first argument is the property being queried.
763 /// The second argument indicates whether the query should look inside
764 /// instruction bundles.
765 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
766 assert(MCFlag < 64 &&
767 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
768 // Inline the fast path for unbundled or bundle-internal instructions.
769 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
770 return getDesc().getFlags() & (1ULL << MCFlag);
771
772 // If this is the first instruction in a bundle, take the slow path.
773 return hasPropertyInBundle(1ULL << MCFlag, Type);
774 }
775
776 /// Return true if this is an instruction that should go through the usual
777 /// legalization steps.
778 bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
779 return hasProperty(MCID::PreISelOpcode, Type);
780 }
781
782 /// Return true if this instruction can have a variable number of operands.
783 /// In this case, the variable operands will be after the normal
784 /// operands but before the implicit definitions and uses (if any are
785 /// present).
786 bool isVariadic(QueryType Type = IgnoreBundle) const {
787 return hasProperty(MCID::Variadic, Type);
788 }
789
790 /// Set if this instruction has an optional definition, e.g.
791 /// ARM instructions which can set condition code if 's' bit is set.
792 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
793 return hasProperty(MCID::HasOptionalDef, Type);
794 }
795
796 /// Return true if this is a pseudo instruction that doesn't
797 /// correspond to a real machine instruction.
798 bool isPseudo(QueryType Type = IgnoreBundle) const {
799 return hasProperty(MCID::Pseudo, Type);
800 }
801
802 bool isReturn(QueryType Type = AnyInBundle) const {
803 return hasProperty(MCID::Return, Type);
804 }
805
806 /// Return true if this is an instruction that marks the end of an EH scope,
807 /// i.e., a catchpad or a cleanuppad instruction.
808 bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
809 return hasProperty(MCID::EHScopeReturn, Type);
810 }
811
812 bool isCall(QueryType Type = AnyInBundle) const {
813 return hasProperty(MCID::Call, Type);
814 }
815
816 /// Return true if this is a call instruction that may have an associated
817 /// call site entry in the debug info.
818 bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
819 /// Return true if copying, moving, or erasing this instruction requires
820 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
821 /// \ref eraseCallSiteInfo).
822 bool shouldUpdateCallSiteInfo() const;
823
824 /// Returns true if the specified instruction stops control flow
825 /// from executing the instruction immediately following it. Examples include
826 /// unconditional branches and return instructions.
827 bool isBarrier(QueryType Type = AnyInBundle) const {
828 return hasProperty(MCID::Barrier, Type);
829 }
830
831 /// Returns true if this instruction part of the terminator for a basic block.
832 /// Typically this is things like return and branch instructions.
833 ///
834 /// Various passes use this to insert code into the bottom of a basic block,
835 /// but before control flow occurs.
836 bool isTerminator(QueryType Type = AnyInBundle) const {
837 return hasProperty(MCID::Terminator, Type);
838 }
839
840 /// Returns true if this is a conditional, unconditional, or indirect branch.
841 /// Predicates below can be used to discriminate between
842 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
843 /// get more information.
844 bool isBranch(QueryType Type = AnyInBundle) const {
845 return hasProperty(MCID::Branch, Type);
846 }
847
848 /// Return true if this is an indirect branch, such as a
849 /// branch through a register.
850 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
851 return hasProperty(MCID::IndirectBranch, Type);
852 }
853
854 /// Return true if this is a branch which may fall
855 /// through to the next instruction or may transfer control flow to some other
856 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
857 /// information about this branch.
858 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
859 return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
860 }
861
862 /// Return true if this is a branch which always
863 /// transfers control flow to some other block. The
864 /// TargetInstrInfo::analyzeBranch method can be used to get more information
865 /// about this branch.
866 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
867 return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
868 }
869
870 /// Return true if this instruction has a predicate operand that
871 /// controls execution. It may be set to 'always', or may be set to other
872 /// values. There are various methods in TargetInstrInfo that can be used to
873 /// control and modify the predicate in this instruction.
874 bool isPredicable(QueryType Type = AllInBundle) const {
875 // If it's a bundle than all bundled instructions must be predicable for this
876 // to return true.
877 return hasProperty(MCID::Predicable, Type);
878 }
879
880 /// Return true if this instruction is a comparison.
881 bool isCompare(QueryType Type = IgnoreBundle) const {
882 return hasProperty(MCID::Compare, Type);
883 }
884
885 /// Return true if this instruction is a move immediate
886 /// (including conditional moves) instruction.
887 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
888 return hasProperty(MCID::MoveImm, Type);
889 }
890
891 /// Return true if this instruction is a register move.
892 /// (including moving values from subreg to reg)
893 bool isMoveReg(QueryType Type = IgnoreBundle) const {
894 return hasProperty(MCID::MoveReg, Type);
895 }
896
897 /// Return true if this instruction is a bitcast instruction.
898 bool isBitcast(QueryType Type = IgnoreBundle) const {
899 return hasProperty(MCID::Bitcast, Type);
900 }
901
902 /// Return true if this instruction is a select instruction.
903 bool isSelect(QueryType Type = IgnoreBundle) const {
904 return hasProperty(MCID::Select, Type);
905 }
906
907 /// Return true if this instruction cannot be safely duplicated.
908 /// For example, if the instruction has a unique labels attached
909 /// to it, duplicating it would cause multiple definition errors.
910 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
911 return hasProperty(MCID::NotDuplicable, Type);
912 }
913
914 /// Return true if this instruction is convergent.
915 /// Convergent instructions can not be made control-dependent on any
916 /// additional values.
917 bool isConvergent(QueryType Type = AnyInBundle) const {
918 if (isInlineAsm()) {
919 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
920 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
921 return true;
922 }
923 return hasProperty(MCID::Convergent, Type);
924 }
925
926 /// Returns true if the specified instruction has a delay slot
927 /// which must be filled by the code generator.
928 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
929 return hasProperty(MCID::DelaySlot, Type);
930 }
931
932 /// Return true for instructions that can be folded as
933 /// memory operands in other instructions. The most common use for this
934 /// is instructions that are simple loads from memory that don't modify
935 /// the loaded value in any way, but it can also be used for instructions
936 /// that can be expressed as constant-pool loads, such as V_SETALLONES
937 /// on x86, to allow them to be folded when it is beneficial.
938 /// This should only be set on instructions that return a value in their
939 /// only virtual register definition.
940 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
941 return hasProperty(MCID::FoldableAsLoad, Type);
942 }
943
944 /// Return true if this instruction behaves
945 /// the same way as the generic REG_SEQUENCE instructions.
946 /// E.g., on ARM,
947 /// dX VMOVDRR rY, rZ
948 /// is equivalent to
949 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
950 ///
951 /// Note that for the optimizers to be able to take advantage of
952 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
953 /// override accordingly.
954 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
955 return hasProperty(MCID::RegSequence, Type);
956 }
957
958 /// Return true if this instruction behaves
959 /// the same way as the generic EXTRACT_SUBREG instructions.
960 /// E.g., on ARM,
961 /// rX, rY VMOVRRD dZ
962 /// is equivalent to two EXTRACT_SUBREG:
963 /// rX = EXTRACT_SUBREG dZ, ssub_0
964 /// rY = EXTRACT_SUBREG dZ, ssub_1
965 ///
966 /// Note that for the optimizers to be able to take advantage of
967 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
968 /// override accordingly.
969 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
970 return hasProperty(MCID::ExtractSubreg, Type);
971 }
972
973 /// Return true if this instruction behaves
974 /// the same way as the generic INSERT_SUBREG instructions.
975 /// E.g., on ARM,
976 /// dX = VSETLNi32 dY, rZ, Imm
977 /// is equivalent to a INSERT_SUBREG:
978 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
979 ///
980 /// Note that for the optimizers to be able to take advantage of
981 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
982 /// override accordingly.
983 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
984 return hasProperty(MCID::InsertSubreg, Type);
985 }
986
987 //===--------------------------------------------------------------------===//
988 // Side Effect Analysis
989 //===--------------------------------------------------------------------===//
990
991 /// Return true if this instruction could possibly read memory.
992 /// Instructions with this flag set are not necessarily simple load
993 /// instructions, they may load a value and modify it, for example.
994 bool mayLoad(QueryType Type = AnyInBundle) const {
995 if (isInlineAsm()) {
996 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
997 if (ExtraInfo & InlineAsm::Extra_MayLoad)
998 return true;
999 }
1000 return hasProperty(MCID::MayLoad, Type);
1001 }
1002
1003 /// Return true if this instruction could possibly modify memory.
1004 /// Instructions with this flag set are not necessarily simple store
1005 /// instructions, they may store a modified value based on their operands, or
1006 /// may not actually modify anything, for example.
1007 bool mayStore(QueryType Type = AnyInBundle) const {
1008 if (isInlineAsm()) {
1009 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1010 if (ExtraInfo & InlineAsm::Extra_MayStore)
1011 return true;
1012 }
1013 return hasProperty(MCID::MayStore, Type);
1014 }
1015
1016 /// Return true if this instruction could possibly read or modify memory.
1017 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
1018 return mayLoad(Type) || mayStore(Type);
1019 }
1020
1021 /// Return true if this instruction could possibly raise a floating-point
1022 /// exception. This is the case if the instruction is a floating-point
1023 /// instruction that can in principle raise an exception, as indicated
1024 /// by the MCID::MayRaiseFPException property, *and* at the same time,
1025 /// the instruction is used in a context where we expect floating-point
1026 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1027 bool mayRaiseFPException() const {
1028 return hasProperty(MCID::MayRaiseFPException) &&
1029 !getFlag(MachineInstr::MIFlag::NoFPExcept);
1030 }
1031
1032 //===--------------------------------------------------------------------===//
1033 // Flags that indicate whether an instruction can be modified by a method.
1034 //===--------------------------------------------------------------------===//
1035
1036 /// Return true if this may be a 2- or 3-address
1037 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1038 /// result if Y and Z are exchanged. If this flag is set, then the
1039 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1040 /// instruction.
1041 ///
1042 /// Note that this flag may be set on instructions that are only commutable
1043 /// sometimes. In these cases, the call to commuteInstruction will fail.
1044 /// Also note that some instructions require non-trivial modification to
1045 /// commute them.
1046 bool isCommutable(QueryType Type = IgnoreBundle) const {
1047 return hasProperty(MCID::Commutable, Type);
1048 }
1049
1050 /// Return true if this is a 2-address instruction
1051 /// which can be changed into a 3-address instruction if needed. Doing this
1052 /// transformation can be profitable in the register allocator, because it
1053 /// means that the instruction can use a 2-address form if possible, but
1054 /// degrade into a less efficient form if the source and dest register cannot
1055 /// be assigned to the same register. For example, this allows the x86
1056 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1057 /// is the same speed as the shift but has bigger code size.
1058 ///
1059 /// If this returns true, then the target must implement the
1060 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1061 /// is allowed to fail if the transformation isn't valid for this specific
1062 /// instruction (e.g. shl reg, 4 on x86).
1063 ///
1064 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
1065 return hasProperty(MCID::ConvertibleTo3Addr, Type);
1066 }
1067
1068 /// Return true if this instruction requires
1069 /// custom insertion support when the DAG scheduler is inserting it into a
1070 /// machine basic block. If this is true for the instruction, it basically
1071 /// means that it is a pseudo instruction used at SelectionDAG time that is
1072 /// expanded out into magic code by the target when MachineInstrs are formed.
1073 ///
1074 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1075 /// is used to insert this into the MachineBasicBlock.
1076 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
1077 return hasProperty(MCID::UsesCustomInserter, Type);
1078 }
1079
1080 /// Return true if this instruction requires *adjustment*
1081 /// after instruction selection by calling a target hook. For example, this
1082 /// can be used to fill in ARM 's' optional operand depending on whether
1083 /// the conditional flag register is used.
1084 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
1085 return hasProperty(MCID::HasPostISelHook, Type);
1086 }
1087
1088 /// Returns true if this instruction is a candidate for remat.
1089 /// This flag is deprecated, please don't use it anymore. If this
1090 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1091 /// verify the instruction is really rematable.
1092 bool isRematerializable(QueryType Type = AllInBundle) const {
1093 // It's only possible to re-mat a bundle if all bundled instructions are
1094 // re-materializable.
1095 return hasProperty(MCID::Rematerializable, Type);
1096 }
1097
1098 /// Returns true if this instruction has the same cost (or less) than a move
1099 /// instruction. This is useful during certain types of optimizations
1100 /// (e.g., remat during two-address conversion or machine licm)
1101 /// where we would like to remat or hoist the instruction, but not if it costs
1102 /// more than moving the instruction into the appropriate register. Note, we
1103 /// are not marking copies from and to the same register class with this flag.
1104 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
1105 // Only returns true for a bundle if all bundled instructions are cheap.
1106 return hasProperty(MCID::CheapAsAMove, Type);
1107 }
1108
1109 /// Returns true if this instruction source operands
1110 /// have special register allocation requirements that are not captured by the
1111 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1112 /// even / odd pair, ARM::STM registers have to be in ascending order.
1113 /// Post-register allocation passes should not attempt to change allocations
1114 /// for sources of instructions with this flag.
1115 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
1116 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
1117 }
1118
1119 /// Returns true if this instruction def operands
1120 /// have special register allocation requirements that are not captured by the
1121 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1122 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1123 /// Post-register allocation passes should not attempt to change allocations
1124 /// for definitions of instructions with this flag.
1125 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
1126 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
1127 }
1128
1129 enum MICheckType {
1130 CheckDefs, // Check all operands for equality
1131 CheckKillDead, // Check all operands including kill / dead markers
1132 IgnoreDefs, // Ignore all definitions
1133 IgnoreVRegDefs // Ignore virtual register definitions
1134 };
1135
1136 /// Return true if this instruction is identical to \p Other.
1137 /// Two instructions are identical if they have the same opcode and all their
1138 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1139 /// Note that this means liveness related flags (dead, undef, kill) do not
1140 /// affect the notion of identical.
1141 bool isIdenticalTo(const MachineInstr &Other,
1142 MICheckType Check = CheckDefs) const;
1143
1144 /// Unlink 'this' from the containing basic block, and return it without
1145 /// deleting it.
1146 ///
1147 /// This function can not be used on bundled instructions, use
1148 /// removeFromBundle() to remove individual instructions from a bundle.
1149 MachineInstr *removeFromParent();
1150
1151 /// Unlink this instruction from its basic block and return it without
1152 /// deleting it.
1153 ///
1154 /// If the instruction is part of a bundle, the other instructions in the
1155 /// bundle remain bundled.
1156 MachineInstr *removeFromBundle();
1157
1158 /// Unlink 'this' from the containing basic block and delete it.
1159 ///
1160 /// If this instruction is the header of a bundle, the whole bundle is erased.
1161 /// This function can not be used for instructions inside a bundle, use
1162 /// eraseFromBundle() to erase individual bundled instructions.
1163 void eraseFromParent();
1164
1165 /// Unlink 'this' from the containing basic block and delete it.
1166 ///
1167 /// For all definitions mark their uses in DBG_VALUE nodes
1168 /// as undefined. Otherwise like eraseFromParent().
1169 void eraseFromParentAndMarkDBGValuesForRemoval();
1170
1171 /// Unlink 'this' form its basic block and delete it.
1172 ///
1173 /// If the instruction is part of a bundle, the other instructions in the
1174 /// bundle remain bundled.
1175 void eraseFromBundle();
1176
1177 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1178 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1179 bool isAnnotationLabel() const {
1180 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1181 }
1182
1183 /// Returns true if the MachineInstr represents a label.
1184 bool isLabel() const {
1185 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1186 }
1187
1188 bool isCFIInstruction() const {
1189 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1190 }
1191
1192 bool isPseudoProbe() const {
1193 return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1194 }
1195
1196 // True if the instruction represents a position in the function.
1197 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1198
1199 bool isNonListDebugValue() const {
1200 return getOpcode() == TargetOpcode::DBG_VALUE;
1201 }
1202 bool isDebugValueList() const {
1203 return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1204 }
1205 bool isDebugValue() const {
1206 return isNonListDebugValue() || isDebugValueList();
1207 }
1208 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1209 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1210 bool isDebugInstr() const {
1211 return isDebugValue() || isDebugLabel() || isDebugRef();
1212 }
1213 bool isDebugOrPseudoInstr() const {
1214 return isDebugInstr() || isPseudoProbe();
1215 }
1216
1217 bool isDebugOffsetImm() const {
1218 return isNonListDebugValue() && getDebugOffset().isImm();
1219 }
1220
1221 /// A DBG_VALUE is indirect iff the location operand is a register and
1222 /// the offset operand is an immediate.
1223 bool isIndirectDebugValue() const {
1224 return isDebugOffsetImm() && getDebugOperand(0).isReg();
1225 }
1226
1227 /// A DBG_VALUE is an entry value iff its debug expression contains the
1228 /// DW_OP_LLVM_entry_value operation.
1229 bool isDebugEntryValue() const;
1230
1231 /// Return true if the instruction is a debug value which describes a part of
1232 /// a variable as unavailable.
1233 bool isUndefDebugValue() const {
1234 if (!isDebugValue())
1235 return false;
1236 // If any $noreg locations are given, this DV is undef.
1237 for (const MachineOperand &Op : debug_operands())
1238 if (Op.isReg() && !Op.getReg().isValid())
1239 return true;
1240 return false;
1241 }
1242
1243 bool isPHI() const {
1244 return getOpcode() == TargetOpcode::PHI ||
1245 getOpcode() == TargetOpcode::G_PHI;
1246 }
1247 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1248 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1249 bool isInlineAsm() const {
1250 return getOpcode() == TargetOpcode::INLINEASM ||
1251 getOpcode() == TargetOpcode::INLINEASM_BR;
1252 }
1253
1254 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1255 /// specific, be attached to a generic MachineInstr.
1256 bool isMSInlineAsm() const {
1257 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1258 }
1259
1260 bool isStackAligningInlineAsm() const;
1261 InlineAsm::AsmDialect getInlineAsmDialect() const;
1262
1263 bool isInsertSubreg() const {
1264 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1265 }
1266
1267 bool isSubregToReg() const {
1268 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1269 }
1270
1271 bool isRegSequence() const {
1272 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1273 }
1274
1275 bool isBundle() const {
1276 return getOpcode() == TargetOpcode::BUNDLE;
1277 }
1278
1279 bool isCopy() const {
1280 return getOpcode() == TargetOpcode::COPY;
1281 }
1282
1283 bool isFullCopy() const {
1284 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1285 }
1286
1287 bool isExtractSubreg() const {
1288 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1289 }
1290
1291 /// Return true if the instruction behaves like a copy.
1292 /// This does not include native copy instructions.
1293 bool isCopyLike() const {
1294 return isCopy() || isSubregToReg();
1295 }
1296
1297 /// Return true is the instruction is an identity copy.
1298 bool isIdentityCopy() const {
1299 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1300 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1301 }
1302
1303 /// Return true if this instruction doesn't produce any output in the form of
1304 /// executable instructions.
1305 bool isMetaInstruction() const {
1306 switch (getOpcode()) {
1307 default:
1308 return false;
1309 case TargetOpcode::IMPLICIT_DEF:
1310 case TargetOpcode::KILL:
1311 case TargetOpcode::CFI_INSTRUCTION:
1312 case TargetOpcode::EH_LABEL:
1313 case TargetOpcode::GC_LABEL:
1314 case TargetOpcode::DBG_VALUE:
1315 case TargetOpcode::DBG_VALUE_LIST:
1316 case TargetOpcode::DBG_INSTR_REF:
1317 case TargetOpcode::DBG_LABEL:
1318 case TargetOpcode::LIFETIME_START:
1319 case TargetOpcode::LIFETIME_END:
1320 case TargetOpcode::PSEUDO_PROBE:
1321 return true;
1322 }
1323 }
1324
1325 /// Return true if this is a transient instruction that is either very likely
1326 /// to be eliminated during register allocation (such as copy-like
1327 /// instructions), or if this instruction doesn't have an execution-time cost.
1328 bool isTransient() const {
1329 switch (getOpcode()) {
1330 default:
1331 return isMetaInstruction();
1332 // Copy-like instructions are usually eliminated during register allocation.
1333 case TargetOpcode::PHI:
1334 case TargetOpcode::G_PHI:
1335 case TargetOpcode::COPY:
1336 case TargetOpcode::INSERT_SUBREG:
1337 case TargetOpcode::SUBREG_TO_REG:
1338 case TargetOpcode::REG_SEQUENCE:
1339 return true;
1340 }
1341 }
1342
1343 /// Return the number of instructions inside the MI bundle, excluding the
1344 /// bundle header.
1345 ///
1346 /// This is the number of instructions that MachineBasicBlock::iterator
1347 /// skips, 0 for unbundled instructions.
1348 unsigned getBundleSize() const;
1349
1350 /// Return true if the MachineInstr reads the specified register.
1351 /// If TargetRegisterInfo is passed, then it also checks if there
1352 /// is a read of a super-register.
1353 /// This does not count partial redefines of virtual registers as reads:
1354 /// %reg1024:6 = OP.
1355 bool readsRegister(Register Reg,
1356 const TargetRegisterInfo *TRI = nullptr) const {
1357 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1358 }
1359
1360 /// Return true if the MachineInstr reads the specified virtual register.
1361 /// Take into account that a partial define is a
1362 /// read-modify-write operation.
1363 bool readsVirtualRegister(Register Reg) const {
1364 return readsWritesVirtualRegister(Reg).first;
1365 }
1366
1367 /// Return a pair of bools (reads, writes) indicating if this instruction
1368 /// reads or writes Reg. This also considers partial defines.
1369 /// If Ops is not null, all operand indices for Reg are added.
1370 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1371 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1372
1373 /// Return true if the MachineInstr kills the specified register.
1374 /// If TargetRegisterInfo is passed, then it also checks if there is
1375 /// a kill of a super-register.
1376 bool killsRegister(Register Reg,
1377 const TargetRegisterInfo *TRI = nullptr) const {
1378 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1379 }
1380
1381 /// Return true if the MachineInstr fully defines the specified register.
1382 /// If TargetRegisterInfo is passed, then it also checks
1383 /// if there is a def of a super-register.
1384 /// NOTE: It's ignoring subreg indices on virtual registers.
1385 bool definesRegister(Register Reg,
1386 const TargetRegisterInfo *TRI = nullptr) const {
1387 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1388 }
1389
1390 /// Return true if the MachineInstr modifies (fully define or partially
1391 /// define) the specified register.
1392 /// NOTE: It's ignoring subreg indices on virtual registers.
1393 bool modifiesRegister(Register Reg,
1394 const TargetRegisterInfo *TRI = nullptr) const {
1395 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1396 }
1397
1398 /// Returns true if the register is dead in this machine instruction.
1399 /// If TargetRegisterInfo is passed, then it also checks
1400 /// if there is a dead def of a super-register.
1401 bool registerDefIsDead(Register Reg,
1402 const TargetRegisterInfo *TRI = nullptr) const {
1403 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1404 }
1405
1406 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1407 /// the given register (not considering sub/super-registers).
1408 bool hasRegisterImplicitUseOperand(Register Reg) const;
1409
1410 /// Returns the operand index that is a use of the specific register or -1
1411 /// if it is not found. It further tightens the search criteria to a use
1412 /// that kills the register if isKill is true.
1413 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1414 const TargetRegisterInfo *TRI = nullptr) const;
1415
1416 /// Wrapper for findRegisterUseOperandIdx, it returns
1417 /// a pointer to the MachineOperand rather than an index.
1418 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1419 const TargetRegisterInfo *TRI = nullptr) {
1420 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1421 return (Idx == -1) ? nullptr : &getOperand(Idx);
1422 }
1423
1424 const MachineOperand *findRegisterUseOperand(
1425 Register Reg, bool isKill = false,
1426 const TargetRegisterInfo *TRI = nullptr) const {
1427 return const_cast<MachineInstr *>(this)->
1428 findRegisterUseOperand(Reg, isKill, TRI);
1429 }
1430
1431 /// Returns the operand index that is a def of the specified register or
1432 /// -1 if it is not found. If isDead is true, defs that are not dead are
1433 /// skipped. If Overlap is true, then it also looks for defs that merely
1434 /// overlap the specified register. If TargetRegisterInfo is non-null,
1435 /// then it also checks if there is a def of a super-register.
1436 /// This may also return a register mask operand when Overlap is true.
1437 int findRegisterDefOperandIdx(Register Reg,
1438 bool isDead = false, bool Overlap = false,
1439 const TargetRegisterInfo *TRI = nullptr) const;
1440
1441 /// Wrapper for findRegisterDefOperandIdx, it returns
1442 /// a pointer to the MachineOperand rather than an index.
1443 MachineOperand *
1444 findRegisterDefOperand(Register Reg, bool isDead = false,
1445 bool Overlap = false,
1446 const TargetRegisterInfo *TRI = nullptr) {
1447 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1448 return (Idx == -1) ? nullptr : &getOperand(Idx);
1449 }
1450
1451 const MachineOperand *
1452 findRegisterDefOperand(Register Reg, bool isDead = false,
1453 bool Overlap = false,
1454 const TargetRegisterInfo *TRI = nullptr) const {
1455 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1456 Reg, isDead, Overlap, TRI);
1457 }
1458
1459 /// Find the index of the first operand in the
1460 /// operand list that is used to represent the predicate. It returns -1 if
1461 /// none is found.
1462 int findFirstPredOperandIdx() const;
1463
1464 /// Find the index of the flag word operand that
1465 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1466 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1467 ///
1468 /// If GroupNo is not NULL, it will receive the number of the operand group
1469 /// containing OpIdx.
1470 ///
1471 /// The flag operand is an immediate that can be decoded with methods like
1472 /// InlineAsm::hasRegClassConstraint().
1473 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1474
1475 /// Compute the static register class constraint for operand OpIdx.
1476 /// For normal instructions, this is derived from the MCInstrDesc.
1477 /// For inline assembly it is derived from the flag words.
1478 ///
1479 /// Returns NULL if the static register class constraint cannot be
1480 /// determined.
1481 const TargetRegisterClass*
1482 getRegClassConstraint(unsigned OpIdx,
1483 const TargetInstrInfo *TII,
1484 const TargetRegisterInfo *TRI) const;
1485
1486 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1487 /// the given \p CurRC.
1488 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1489 /// instructions inside the bundle will be taken into account. In other words,
1490 /// this method accumulates all the constraints of the operand of this MI and
1491 /// the related bundle if MI is a bundle or inside a bundle.
1492 ///
1493 /// Returns the register class that satisfies both \p CurRC and the
1494 /// constraints set by MI. Returns NULL if such a register class does not
1495 /// exist.
1496 ///
1497 /// \pre CurRC must not be NULL.
1498 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1499 Register Reg, const TargetRegisterClass *CurRC,
1500 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1501 bool ExploreBundle = false) const;
1502
1503 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1504 /// to the given \p CurRC.
1505 ///
1506 /// Returns the register class that satisfies both \p CurRC and the
1507 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1508 /// does not exist.
1509 ///
1510 /// \pre CurRC must not be NULL.
1511 /// \pre The operand at \p OpIdx must be a register.
1512 const TargetRegisterClass *
1513 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1514 const TargetInstrInfo *TII,
1515 const TargetRegisterInfo *TRI) const;
1516
1517 /// Add a tie between the register operands at DefIdx and UseIdx.
1518 /// The tie will cause the register allocator to ensure that the two
1519 /// operands are assigned the same physical register.
1520 ///
1521 /// Tied operands are managed automatically for explicit operands in the
1522 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1523 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1524
1525 /// Given the index of a tied register operand, find the
1526 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1527 /// index of the tied operand which must exist.
1528 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1529
1530 /// Given the index of a register def operand,
1531 /// check if the register def is tied to a source operand, due to either
1532 /// two-address elimination or inline assembly constraints. Returns the
1533 /// first tied use operand index by reference if UseOpIdx is not null.
1534 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1535 unsigned *UseOpIdx = nullptr) const {
1536 const MachineOperand &MO = getOperand(DefOpIdx);
1537 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1538 return false;
1539 if (UseOpIdx)
1540 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1541 return true;
1542 }
1543
1544 /// Return true if the use operand of the specified index is tied to a def
1545 /// operand. It also returns the def operand index by reference if DefOpIdx
1546 /// is not null.
1547 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1548 unsigned *DefOpIdx = nullptr) const {
1549 const MachineOperand &MO = getOperand(UseOpIdx);
1550 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1551 return false;
1552 if (DefOpIdx)
1553 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1554 return true;
1555 }
1556
1557 /// Clears kill flags on all operands.
1558 void clearKillInfo();
1559
1560 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1561 /// properly composing subreg indices where necessary.
1562 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1563 const TargetRegisterInfo &RegInfo);
1564
1565 /// We have determined MI kills a register. Look for the
1566 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1567 /// add a implicit operand if it's not found. Returns true if the operand
1568 /// exists / is added.
1569 bool addRegisterKilled(Register IncomingReg,
1570 const TargetRegisterInfo *RegInfo,
1571 bool AddIfNotFound = false);
1572
1573 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1574 /// all aliasing registers.
1575 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1576
1577 /// We have determined MI defined a register without a use.
1578 /// Look for the operand that defines it and mark it as IsDead. If
1579 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1580 /// true if the operand exists / is added.
1581 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1582 bool AddIfNotFound = false);
1583
1584 /// Clear all dead flags on operands defining register @p Reg.
1585 void clearRegisterDeads(Register Reg);
1586
1587 /// Mark all subregister defs of register @p Reg with the undef flag.
1588 /// This function is used when we determined to have a subregister def in an
1589 /// otherwise undefined super register.
1590 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1591
1592 /// We have determined MI defines a register. Make sure there is an operand
1593 /// defining Reg.
1594 void addRegisterDefined(Register Reg,
1595 const TargetRegisterInfo *RegInfo = nullptr);
1596
1597 /// Mark every physreg used by this instruction as
1598 /// dead except those in the UsedRegs list.
1599 ///
1600 /// On instructions with register mask operands, also add implicit-def
1601 /// operands for all registers in UsedRegs.
1602 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1603 const TargetRegisterInfo &TRI);
1604
1605 /// Return true if it is safe to move this instruction. If
1606 /// SawStore is set to true, it means that there is a store (or call) between
1607 /// the instruction's location and its intended destination.
1608 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1609
1610 /// Returns true if this instruction's memory access aliases the memory
1611 /// access of Other.
1612 //
1613 /// Assumes any physical registers used to compute addresses
1614 /// have the same value for both instructions. Returns false if neither
1615 /// instruction writes to memory.
1616 ///
1617 /// @param AA Optional alias analysis, used to compare memory operands.
1618 /// @param Other MachineInstr to check aliasing against.
1619 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1620 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1621
1622 /// Return true if this instruction may have an ordered
1623 /// or volatile memory reference, or if the information describing the memory
1624 /// reference is not available. Return false if it is known to have no
1625 /// ordered or volatile memory references.
1626 bool hasOrderedMemoryRef() const;
1627
1628 /// Return true if this load instruction never traps and points to a memory
1629 /// location whose value doesn't change during the execution of this function.
1630 ///
1631 /// Examples include loading a value from the constant pool or from the
1632 /// argument area of a function (if it does not change). If the instruction
1633 /// does multiple loads, this returns true only if all of the loads are
1634 /// dereferenceable and invariant.
1635 bool isDereferenceableInvariantLoad(AAResults *AA) const;
1636
1637 /// If the specified instruction is a PHI that always merges together the
1638 /// same virtual register, return the register, otherwise return 0.
1639 unsigned isConstantValuePHI() const;
1640
1641 /// Return true if this instruction has side effects that are not modeled
1642 /// by mayLoad / mayStore, etc.
1643 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1644 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1645 /// INLINEASM instruction, in which case the side effect property is encoded
1646 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1647 ///
1648 bool hasUnmodeledSideEffects() const;
1649
1650 /// Returns true if it is illegal to fold a load across this instruction.
1651 bool isLoadFoldBarrier() const;
1652
1653 /// Return true if all the defs of this instruction are dead.
1654 bool allDefsAreDead() const;
1655
1656 /// Return a valid size if the instruction is a spill instruction.
1657 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1658
1659 /// Return a valid size if the instruction is a folded spill instruction.
1660 Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1661
1662 /// Return a valid size if the instruction is a restore instruction.
1663 Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1664
1665 /// Return a valid size if the instruction is a folded restore instruction.
1666 Optional<unsigned>
1667 getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1668
1669 /// Copy implicit register operands from specified
1670 /// instruction to this instruction.
1671 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1672
1673 /// Debugging support
1674 /// @{
1675 /// Determine the generic type to be printed (if needed) on uses and defs.
1676 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1677 const MachineRegisterInfo &MRI) const;
1678
1679 /// Return true when an instruction has tied register that can't be determined
1680 /// by the instruction's descriptor. This is useful for MIR printing, to
1681 /// determine whether we need to print the ties or not.
1682 bool hasComplexRegisterTies() const;
1683
1684 /// Print this MI to \p OS.
1685 /// Don't print information that can be inferred from other instructions if
1686 /// \p IsStandalone is false. It is usually true when only a fragment of the
1687 /// function is printed.
1688 /// Only print the defs and the opcode if \p SkipOpers is true.
1689 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1690 /// Otherwise, also print the debug loc, with a terminating newline.
1691 /// \p TII is used to print the opcode name. If it's not present, but the
1692 /// MI is in a function, the opcode will be printed using the function's TII.
1693 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1694 bool SkipDebugLoc = false, bool AddNewLine = true,
1695 const TargetInstrInfo *TII = nullptr) const;
1696 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1697 bool SkipOpers = false, bool SkipDebugLoc = false,
1698 bool AddNewLine = true,
1699 const TargetInstrInfo *TII = nullptr) const;
1700 void dump() const;
1701 /// Print on dbgs() the current instruction and the instructions defining its
1702 /// operands and so on until we reach \p MaxDepth.
1703 void dumpr(const MachineRegisterInfo &MRI,
1704 unsigned MaxDepth = UINT_MAX) const;
1705 /// @}
1706
1707 //===--------------------------------------------------------------------===//
1708 // Accessors used to build up machine instructions.
1709
1710 /// Add the specified operand to the instruction. If it is an implicit
1711 /// operand, it is added to the end of the operand list. If it is an
1712 /// explicit operand it is added at the end of the explicit operand list
1713 /// (before the first implicit operand).
1714 ///
1715 /// MF must be the machine function that was used to allocate this
1716 /// instruction.
1717 ///
1718 /// MachineInstrBuilder provides a more convenient interface for creating
1719 /// instructions and adding operands.
1720 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1721
1722 /// Add an operand without providing an MF reference. This only works for
1723 /// instructions that are inserted in a basic block.
1724 ///
1725 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1726 /// preferred.
1727 void addOperand(const MachineOperand &Op);
1728
1729 /// Replace the instruction descriptor (thus opcode) of
1730 /// the current instruction with a new one.
1731 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1732
1733 /// Replace current source information with new such.
1734 /// Avoid using this, the constructor argument is preferable.
1735 void setDebugLoc(DebugLoc dl) {
1736 debugLoc = std::move(dl);
1737 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1738 }
1739
1740 /// Erase an operand from an instruction, leaving it with one
1741 /// fewer operand than it started with.
1742 void RemoveOperand(unsigned OpNo);
1743
1744 /// Clear this MachineInstr's memory reference descriptor list. This resets
1745 /// the memrefs to their most conservative state. This should be used only
1746 /// as a last resort since it greatly pessimizes our knowledge of the memory
1747 /// access performed by the instruction.
1748 void dropMemRefs(MachineFunction &MF);
1749
1750 /// Assign this MachineInstr's memory reference descriptor list.
1751 ///
1752 /// Unlike other methods, this *will* allocate them into a new array
1753 /// associated with the provided `MachineFunction`.
1754 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1755
1756 /// Add a MachineMemOperand to the machine instruction.
1757 /// This function should be used only occasionally. The setMemRefs function
1758 /// is the primary method for setting up a MachineInstr's MemRefs list.
1759 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1760
1761 /// Clone another MachineInstr's memory reference descriptor list and replace
1762 /// ours with it.
1763 ///
1764 /// Note that `*this` may be the incoming MI!
1765 ///
1766 /// Prefer this API whenever possible as it can avoid allocations in common
1767 /// cases.
1768 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1769
1770 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1771 /// list and replace ours with it.
1772 ///
1773 /// Note that `*this` may be one of the incoming MIs!
1774 ///
1775 /// Prefer this API whenever possible as it can avoid allocations in common
1776 /// cases.
1777 void cloneMergedMemRefs(MachineFunction &MF,
1778 ArrayRef<const MachineInstr *> MIs);
1779
1780 /// Set a symbol that will be emitted just prior to the instruction itself.
1781 ///
1782 /// Setting this to a null pointer will remove any such symbol.
1783 ///
1784 /// FIXME: This is not fully implemented yet.
1785 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1786
1787 /// Set a symbol that will be emitted just after the instruction itself.
1788 ///
1789 /// Setting this to a null pointer will remove any such symbol.
1790 ///
1791 /// FIXME: This is not fully implemented yet.
1792 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1793
1794 /// Clone another MachineInstr's pre- and post- instruction symbols and
1795 /// replace ours with it.
1796 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1797
1798 /// Set a marker on instructions that denotes where we should create and emit
1799 /// heap alloc site labels. This waits until after instruction selection and
1800 /// optimizations to create the label, so it should still work if the
1801 /// instruction is removed or duplicated.
1802 void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1803
1804 /// Return the MIFlags which represent both MachineInstrs. This
1805 /// should be used when merging two MachineInstrs into one. This routine does
1806 /// not modify the MIFlags of this MachineInstr.
1807 uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1808
1809 static uint16_t copyFlagsFromInstruction(const Instruction &I);
1810
1811 /// Copy all flags to MachineInst MIFlags
1812 void copyIRFlags(const Instruction &I);
1813
1814 /// Break any tie involving OpIdx.
1815 void untieRegOperand(unsigned OpIdx) {
1816 MachineOperand &MO = getOperand(OpIdx);
1817 if (MO.isReg() && MO.isTied()) {
1818 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1819 MO.TiedTo = 0;
1820 }
1821 }
1822
1823 /// Add all implicit def and use operands to this instruction.
1824 void addImplicitDefUseOperands(MachineFunction &MF);
1825
1826 /// Scan instructions immediately following MI and collect any matching
1827 /// DBG_VALUEs.
1828 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1829
1830 /// Find all DBG_VALUEs that point to the register def in this instruction
1831 /// and point them to \p Reg instead.
1832 void changeDebugValuesDefReg(Register Reg);
1833
1834 /// Returns the Intrinsic::ID for this instruction.
1835 /// \pre Must have an intrinsic ID operand.
1836 unsigned getIntrinsicID() const {
1837 return getOperand(getNumExplicitDefs()).getIntrinsicID();
1838 }
1839
1840 /// Sets all register debug operands in this debug value instruction to be
1841 /// undef.
1842 void setDebugValueUndef() {
1843 assert(isDebugValue() && "Must be a debug value instruction.");
1844 for (MachineOperand &MO : debug_operands()) {
1845 if (MO.isReg()) {
1846 MO.setReg(0);
1847 MO.setSubReg(0);
1848 }
1849 }
1850 }
1851
1852 PseudoProbeAttributes getPseudoProbeAttribute() const {
1853 assert(isPseudoProbe() && "Must be a pseudo probe instruction");
1854 return (PseudoProbeAttributes)getOperand(3).getImm();
1855 }
1856
1857 void addPseudoProbeAttribute(PseudoProbeAttributes Attr) {
1858 assert(isPseudoProbe() && "Must be a pseudo probe instruction");
1859 MachineOperand &AttrOperand = getOperand(3);
1860 AttrOperand.setImm(AttrOperand.getImm() | (uint32_t)Attr);
1861 }
1862
1863private:
1864 /// If this instruction is embedded into a MachineFunction, return the
1865 /// MachineRegisterInfo object for the current function, otherwise
1866 /// return null.
1867 MachineRegisterInfo *getRegInfo();
1868
1869 /// Unlink all of the register operands in this instruction from their
1870 /// respective use lists. This requires that the operands already be on their
1871 /// use lists.
1872 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1873
1874 /// Add all of the register operands in this instruction from their
1875 /// respective use lists. This requires that the operands not be on their
1876 /// use lists yet.
1877 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1878
1879 /// Slow path for hasProperty when we're dealing with a bundle.
1880 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1881
1882 /// Implements the logic of getRegClassConstraintEffectForVReg for the
1883 /// this MI and the given operand index \p OpIdx.
1884 /// If the related operand does not constrained Reg, this returns CurRC.
1885 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1886 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1887 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1888
1889 /// Stores extra instruction information inline or allocates as ExtraInfo
1890 /// based on the number of pointers.
1891 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1892 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1893 MDNode *HeapAllocMarker);
1894};
1895
1896/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1897/// instruction rather than by pointer value.
1898/// The hashing and equality testing functions ignore definitions so this is
1899/// useful for CSE, etc.
1900struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1901 static inline MachineInstr *getEmptyKey() {
1902 return nullptr;
1903 }
1904
1905 static inline MachineInstr *getTombstoneKey() {
1906 return reinterpret_cast<MachineInstr*>(-1);
1907 }
1908
1909 static unsigned getHashValue(const MachineInstr* const &MI);
1910
1911 static bool isEqual(const MachineInstr* const &LHS,
1912 const MachineInstr* const &RHS) {
1913 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1914 LHS == getEmptyKey() || LHS == getTombstoneKey())
1915 return LHS == RHS;
1916 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1917 }
1918};
1919
1920//===----------------------------------------------------------------------===//
1921// Debugging Support
1922
1923inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1924 MI.print(OS);
1925 return OS;
1926}
1927
1928} // end namespace llvm
1929
1930#endif // LLVM_CODEGEN_MACHINEINSTR_H
1931