1 | //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the declaration of the MachineInstr class, which is the |
10 | // basic representation for all target dependent machine instructions used by |
11 | // the back end. |
12 | // |
13 | //===----------------------------------------------------------------------===// |
14 | |
15 | #ifndef LLVM_CODEGEN_MACHINEINSTR_H |
16 | #define LLVM_CODEGEN_MACHINEINSTR_H |
17 | |
18 | #include "llvm/ADT/DenseMapInfo.h" |
19 | #include "llvm/ADT/PointerSumType.h" |
20 | #include "llvm/ADT/ilist.h" |
21 | #include "llvm/ADT/ilist_node.h" |
22 | #include "llvm/ADT/iterator_range.h" |
23 | #include "llvm/CodeGen/MachineMemOperand.h" |
24 | #include "llvm/CodeGen/MachineOperand.h" |
25 | #include "llvm/CodeGen/TargetOpcodes.h" |
26 | #include "llvm/IR/DebugLoc.h" |
27 | #include "llvm/IR/InlineAsm.h" |
28 | #include "llvm/MC/MCInstrDesc.h" |
29 | #include "llvm/MC/MCSymbol.h" |
30 | #include "llvm/Support/ArrayRecycler.h" |
31 | #include "llvm/Support/MathExtras.h" |
32 | #include "llvm/Support/TrailingObjects.h" |
33 | #include <algorithm> |
34 | #include <cassert> |
35 | #include <cstdint> |
36 | #include <utility> |
37 | |
38 | namespace llvm { |
39 | |
40 | class DILabel; |
41 | class Instruction; |
42 | class MDNode; |
43 | class AAResults; |
44 | template <typename T> class ArrayRef; |
45 | class DIExpression; |
46 | class DILocalVariable; |
47 | class MachineBasicBlock; |
48 | class MachineFunction; |
49 | class MachineRegisterInfo; |
50 | class ModuleSlotTracker; |
51 | class raw_ostream; |
52 | template <typename T> class SmallVectorImpl; |
53 | class SmallBitVector; |
54 | class StringRef; |
55 | class TargetInstrInfo; |
56 | class TargetRegisterClass; |
57 | class TargetRegisterInfo; |
58 | |
59 | //===----------------------------------------------------------------------===// |
60 | /// Representation of each machine instruction. |
61 | /// |
62 | /// This class isn't a POD type, but it must have a trivial destructor. When a |
63 | /// MachineFunction is deleted, all the contained MachineInstrs are deallocated |
64 | /// without having their destructor called. |
65 | /// |
66 | class MachineInstr |
67 | : public ilist_node_with_parent<MachineInstr, MachineBasicBlock, |
68 | ilist_sentinel_tracking<true>> { |
69 | public: |
70 | using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator; |
71 | |
72 | /// Flags to specify different kinds of comments to output in |
73 | /// assembly code. These flags carry semantic information not |
74 | /// otherwise easily derivable from the IR text. |
75 | /// |
76 | enum { |
77 | ReloadReuse = 0x1, // higher bits are reserved for target dep comments. |
78 | = 0x2, |
79 | = 0x4 // Target Asm comments should start from this value. |
80 | }; |
81 | |
82 | enum MIFlag { |
83 | NoFlags = 0, |
84 | FrameSetup = 1 << 0, // Instruction is used as a part of |
85 | // function frame setup code. |
86 | FrameDestroy = 1 << 1, // Instruction is used as a part of |
87 | // function frame destruction code. |
88 | BundledPred = 1 << 2, // Instruction has bundled predecessors. |
89 | BundledSucc = 1 << 3, // Instruction has bundled successors. |
90 | FmNoNans = 1 << 4, // Instruction does not support Fast |
91 | // math nan values. |
92 | FmNoInfs = 1 << 5, // Instruction does not support Fast |
93 | // math infinity values. |
94 | FmNsz = 1 << 6, // Instruction is not required to retain |
95 | // signed zero values. |
96 | FmArcp = 1 << 7, // Instruction supports Fast math |
97 | // reciprocal approximations. |
98 | FmContract = 1 << 8, // Instruction supports Fast math |
99 | // contraction operations like fma. |
100 | FmAfn = 1 << 9, // Instruction may map to Fast math |
101 | // intrinsic approximation. |
102 | FmReassoc = 1 << 10, // Instruction supports Fast math |
103 | // reassociation of operand order. |
104 | NoUWrap = 1 << 11, // Instruction supports binary operator |
105 | // no unsigned wrap. |
106 | NoSWrap = 1 << 12, // Instruction supports binary operator |
107 | // no signed wrap. |
108 | IsExact = 1 << 13, // Instruction supports division is |
109 | // known to be exact. |
110 | NoFPExcept = 1 << 14, // Instruction does not raise |
111 | // floatint-point exceptions. |
112 | NoMerge = 1 << 15, // Passes that drop source location info |
113 | // (e.g. branch folding) should skip |
114 | // this instruction. |
115 | Unpredictable = 1 << 16, // Instruction with unpredictable condition. |
116 | NoConvergent = 1 << 17, // Call does not require convergence guarantees. |
117 | }; |
118 | |
119 | private: |
120 | const MCInstrDesc *MCID; // Instruction descriptor. |
121 | MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block. |
122 | |
123 | // Operands are allocated by an ArrayRecycler. |
124 | MachineOperand *Operands = nullptr; // Pointer to the first operand. |
125 | |
126 | #define LLVM_MI_NUMOPERANDS_BITS 24 |
127 | #define LLVM_MI_FLAGS_BITS 24 |
128 | #define LLVM_MI_ASMPRINTERFLAGS_BITS 8 |
129 | |
130 | /// Number of operands on instruction. |
131 | uint32_t NumOperands : LLVM_MI_NUMOPERANDS_BITS; |
132 | |
133 | // OperandCapacity has uint8_t size, so it should be next to NumOperands |
134 | // to properly pack. |
135 | using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity; |
136 | OperandCapacity CapOperands; // Capacity of the Operands array. |
137 | |
138 | /// Various bits of additional information about the machine instruction. |
139 | uint32_t Flags : LLVM_MI_FLAGS_BITS; |
140 | |
141 | /// Various bits of information used by the AsmPrinter to emit helpful |
142 | /// comments. This is *not* semantic information. Do not use this for |
143 | /// anything other than to convey comment information to AsmPrinter. |
144 | uint8_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS; |
145 | |
146 | /// Internal implementation detail class that provides out-of-line storage for |
147 | /// extra info used by the machine instruction when this info cannot be stored |
148 | /// in-line within the instruction itself. |
149 | /// |
150 | /// This has to be defined eagerly due to the implementation constraints of |
151 | /// `PointerSumType` where it is used. |
152 | class final : TrailingObjects<ExtraInfo, MachineMemOperand *, |
153 | MCSymbol *, MDNode *, uint32_t> { |
154 | public: |
155 | static ExtraInfo *create(BumpPtrAllocator &Allocator, |
156 | ArrayRef<MachineMemOperand *> MMOs, |
157 | MCSymbol *PreInstrSymbol = nullptr, |
158 | MCSymbol *PostInstrSymbol = nullptr, |
159 | MDNode *HeapAllocMarker = nullptr, |
160 | MDNode *PCSections = nullptr, |
161 | uint32_t CFIType = 0) { |
162 | bool HasPreInstrSymbol = PreInstrSymbol != nullptr; |
163 | bool HasPostInstrSymbol = PostInstrSymbol != nullptr; |
164 | bool HasHeapAllocMarker = HeapAllocMarker != nullptr; |
165 | bool HasCFIType = CFIType != 0; |
166 | bool HasPCSections = PCSections != nullptr; |
167 | auto *Result = new (Allocator.Allocate( |
168 | Size: totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>( |
169 | Counts: MMOs.size(), Counts: HasPreInstrSymbol + HasPostInstrSymbol, |
170 | Counts: HasHeapAllocMarker + HasPCSections, Counts: HasCFIType), |
171 | Alignment: alignof(ExtraInfo))) |
172 | ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol, |
173 | HasHeapAllocMarker, HasPCSections, HasCFIType); |
174 | |
175 | // Copy the actual data into the trailing objects. |
176 | std::copy(first: MMOs.begin(), last: MMOs.end(), |
177 | result: Result->getTrailingObjects<MachineMemOperand *>()); |
178 | |
179 | if (HasPreInstrSymbol) |
180 | Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol; |
181 | if (HasPostInstrSymbol) |
182 | Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] = |
183 | PostInstrSymbol; |
184 | if (HasHeapAllocMarker) |
185 | Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker; |
186 | if (HasPCSections) |
187 | Result->getTrailingObjects<MDNode *>()[HasHeapAllocMarker] = |
188 | PCSections; |
189 | if (HasCFIType) |
190 | Result->getTrailingObjects<uint32_t>()[0] = CFIType; |
191 | |
192 | return Result; |
193 | } |
194 | |
195 | ArrayRef<MachineMemOperand *> () const { |
196 | return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs); |
197 | } |
198 | |
199 | MCSymbol *() const { |
200 | return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr; |
201 | } |
202 | |
203 | MCSymbol *() const { |
204 | return HasPostInstrSymbol |
205 | ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] |
206 | : nullptr; |
207 | } |
208 | |
209 | MDNode *() const { |
210 | return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr; |
211 | } |
212 | |
213 | MDNode *() const { |
214 | return HasPCSections |
215 | ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker] |
216 | : nullptr; |
217 | } |
218 | |
219 | uint32_t () const { |
220 | return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0; |
221 | } |
222 | |
223 | private: |
224 | friend TrailingObjects; |
225 | |
226 | // Description of the extra info, used to interpret the actual optional |
227 | // data appended. |
228 | // |
229 | // Note that this is not terribly space optimized. This leaves a great deal |
230 | // of flexibility to fit more in here later. |
231 | const int ; |
232 | const bool ; |
233 | const bool ; |
234 | const bool ; |
235 | const bool ; |
236 | const bool ; |
237 | |
238 | // Implement the `TrailingObjects` internal API. |
239 | size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const { |
240 | return NumMMOs; |
241 | } |
242 | size_t (OverloadToken<MCSymbol *>) const { |
243 | return HasPreInstrSymbol + HasPostInstrSymbol; |
244 | } |
245 | size_t (OverloadToken<MDNode *>) const { |
246 | return HasHeapAllocMarker + HasPCSections; |
247 | } |
248 | size_t (OverloadToken<uint32_t>) const { |
249 | return HasCFIType; |
250 | } |
251 | |
252 | // Just a boring constructor to allow us to initialize the sizes. Always use |
253 | // the `create` routine above. |
254 | (int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol, |
255 | bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType) |
256 | : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol), |
257 | HasPostInstrSymbol(HasPostInstrSymbol), |
258 | HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections), |
259 | HasCFIType(HasCFIType) {} |
260 | }; |
261 | |
262 | /// Enumeration of the kinds of inline extra info available. It is important |
263 | /// that the `MachineMemOperand` inline kind has a tag value of zero to make |
264 | /// it accessible as an `ArrayRef`. |
265 | enum { |
266 | EIIK_MMO = 0, |
267 | EIIK_PreInstrSymbol, |
268 | EIIK_PostInstrSymbol, |
269 | EIIK_OutOfLine |
270 | }; |
271 | |
272 | // We store extra information about the instruction here. The common case is |
273 | // expected to be nothing or a single pointer (typically a MMO or a symbol). |
274 | // We work to optimize this common case by storing it inline here rather than |
275 | // requiring a separate allocation, but we fall back to an allocation when |
276 | // multiple pointers are needed. |
277 | PointerSumType<ExtraInfoInlineKinds, |
278 | PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>, |
279 | PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>, |
280 | PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>, |
281 | PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>> |
282 | Info; |
283 | |
284 | DebugLoc DbgLoc; // Source line information. |
285 | |
286 | /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values |
287 | /// defined by this instruction. |
288 | unsigned DebugInstrNum; |
289 | |
290 | // Intrusive list support |
291 | friend struct ilist_traits<MachineInstr>; |
292 | friend struct ilist_callback_traits<MachineBasicBlock>; |
293 | void setParent(MachineBasicBlock *P) { Parent = P; } |
294 | |
295 | /// This constructor creates a copy of the given |
296 | /// MachineInstr in the given MachineFunction. |
297 | MachineInstr(MachineFunction &, const MachineInstr &); |
298 | |
299 | /// This constructor create a MachineInstr and add the implicit operands. |
300 | /// It reserves space for number of operands specified by |
301 | /// MCInstrDesc. An explicit DebugLoc is supplied. |
302 | MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL, |
303 | bool NoImp = false); |
304 | |
305 | // MachineInstrs are pool-allocated and owned by MachineFunction. |
306 | friend class MachineFunction; |
307 | |
308 | void |
309 | dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth, |
310 | SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const; |
311 | |
312 | static bool opIsRegDef(const MachineOperand &Op) { |
313 | return Op.isReg() && Op.isDef(); |
314 | } |
315 | |
316 | static bool opIsRegUse(const MachineOperand &Op) { |
317 | return Op.isReg() && Op.isUse(); |
318 | } |
319 | |
320 | public: |
321 | MachineInstr(const MachineInstr &) = delete; |
322 | MachineInstr &operator=(const MachineInstr &) = delete; |
323 | // Use MachineFunction::DeleteMachineInstr() instead. |
324 | ~MachineInstr() = delete; |
325 | |
326 | const MachineBasicBlock* getParent() const { return Parent; } |
327 | MachineBasicBlock* getParent() { return Parent; } |
328 | |
329 | /// Move the instruction before \p MovePos. |
330 | void moveBefore(MachineInstr *MovePos); |
331 | |
332 | /// Return the function that contains the basic block that this instruction |
333 | /// belongs to. |
334 | /// |
335 | /// Note: this is undefined behaviour if the instruction does not have a |
336 | /// parent. |
337 | const MachineFunction *getMF() const; |
338 | MachineFunction *getMF() { |
339 | return const_cast<MachineFunction *>( |
340 | static_cast<const MachineInstr *>(this)->getMF()); |
341 | } |
342 | |
343 | /// Return the asm printer flags bitvector. |
344 | uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } |
345 | |
346 | /// Clear the AsmPrinter bitvector. |
347 | void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } |
348 | |
349 | /// Return whether an AsmPrinter flag is set. |
350 | bool (CommentFlag Flag) const { |
351 | assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) && |
352 | "Flag is out of range for the AsmPrinterFlags field" ); |
353 | return AsmPrinterFlags & Flag; |
354 | } |
355 | |
356 | /// Set a flag for the AsmPrinter. |
357 | void setAsmPrinterFlag(uint8_t Flag) { |
358 | assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) && |
359 | "Flag is out of range for the AsmPrinterFlags field" ); |
360 | AsmPrinterFlags |= Flag; |
361 | } |
362 | |
363 | /// Clear specific AsmPrinter flags. |
364 | void (CommentFlag Flag) { |
365 | assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) && |
366 | "Flag is out of range for the AsmPrinterFlags field" ); |
367 | AsmPrinterFlags &= ~Flag; |
368 | } |
369 | |
370 | /// Return the MI flags bitvector. |
371 | uint32_t getFlags() const { |
372 | return Flags; |
373 | } |
374 | |
375 | /// Return whether an MI flag is set. |
376 | bool getFlag(MIFlag Flag) const { |
377 | assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) && |
378 | "Flag is out of range for the Flags field" ); |
379 | return Flags & Flag; |
380 | } |
381 | |
382 | /// Set a MI flag. |
383 | void setFlag(MIFlag Flag) { |
384 | assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) && |
385 | "Flag is out of range for the Flags field" ); |
386 | Flags |= (uint32_t)Flag; |
387 | } |
388 | |
389 | void setFlags(unsigned flags) { |
390 | assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) && |
391 | "flags to be set are out of range for the Flags field" ); |
392 | // Filter out the automatically maintained flags. |
393 | unsigned Mask = BundledPred | BundledSucc; |
394 | Flags = (Flags & Mask) | (flags & ~Mask); |
395 | } |
396 | |
397 | /// clearFlag - Clear a MI flag. |
398 | void clearFlag(MIFlag Flag) { |
399 | assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) && |
400 | "Flag to clear is out of range for the Flags field" ); |
401 | Flags &= ~((uint32_t)Flag); |
402 | } |
403 | |
404 | /// Return true if MI is in a bundle (but not the first MI in a bundle). |
405 | /// |
406 | /// A bundle looks like this before it's finalized: |
407 | /// ---------------- |
408 | /// | MI | |
409 | /// ---------------- |
410 | /// | |
411 | /// ---------------- |
412 | /// | MI * | |
413 | /// ---------------- |
414 | /// | |
415 | /// ---------------- |
416 | /// | MI * | |
417 | /// ---------------- |
418 | /// In this case, the first MI starts a bundle but is not inside a bundle, the |
419 | /// next 2 MIs are considered "inside" the bundle. |
420 | /// |
421 | /// After a bundle is finalized, it looks like this: |
422 | /// ---------------- |
423 | /// | Bundle | |
424 | /// ---------------- |
425 | /// | |
426 | /// ---------------- |
427 | /// | MI * | |
428 | /// ---------------- |
429 | /// | |
430 | /// ---------------- |
431 | /// | MI * | |
432 | /// ---------------- |
433 | /// | |
434 | /// ---------------- |
435 | /// | MI * | |
436 | /// ---------------- |
437 | /// The first instruction has the special opcode "BUNDLE". It's not "inside" |
438 | /// a bundle, but the next three MIs are. |
439 | bool isInsideBundle() const { |
440 | return getFlag(Flag: BundledPred); |
441 | } |
442 | |
443 | /// Return true if this instruction part of a bundle. This is true |
444 | /// if either itself or its following instruction is marked "InsideBundle". |
445 | bool isBundled() const { |
446 | return isBundledWithPred() || isBundledWithSucc(); |
447 | } |
448 | |
449 | /// Return true if this instruction is part of a bundle, and it is not the |
450 | /// first instruction in the bundle. |
451 | bool isBundledWithPred() const { return getFlag(Flag: BundledPred); } |
452 | |
453 | /// Return true if this instruction is part of a bundle, and it is not the |
454 | /// last instruction in the bundle. |
455 | bool isBundledWithSucc() const { return getFlag(Flag: BundledSucc); } |
456 | |
457 | /// Bundle this instruction with its predecessor. This can be an unbundled |
458 | /// instruction, or it can be the first instruction in a bundle. |
459 | void bundleWithPred(); |
460 | |
461 | /// Bundle this instruction with its successor. This can be an unbundled |
462 | /// instruction, or it can be the last instruction in a bundle. |
463 | void bundleWithSucc(); |
464 | |
465 | /// Break bundle above this instruction. |
466 | void unbundleFromPred(); |
467 | |
468 | /// Break bundle below this instruction. |
469 | void unbundleFromSucc(); |
470 | |
471 | /// Returns the debug location id of this MachineInstr. |
472 | const DebugLoc &getDebugLoc() const { return DbgLoc; } |
473 | |
474 | /// Return the operand containing the offset to be used if this DBG_VALUE |
475 | /// instruction is indirect; will be an invalid register if this value is |
476 | /// not indirect, and an immediate with value 0 otherwise. |
477 | const MachineOperand &getDebugOffset() const { |
478 | assert(isNonListDebugValue() && "not a DBG_VALUE" ); |
479 | return getOperand(i: 1); |
480 | } |
481 | MachineOperand &getDebugOffset() { |
482 | assert(isNonListDebugValue() && "not a DBG_VALUE" ); |
483 | return getOperand(i: 1); |
484 | } |
485 | |
486 | /// Return the operand for the debug variable referenced by |
487 | /// this DBG_VALUE instruction. |
488 | const MachineOperand &getDebugVariableOp() const; |
489 | MachineOperand &getDebugVariableOp(); |
490 | |
491 | /// Return the debug variable referenced by |
492 | /// this DBG_VALUE instruction. |
493 | const DILocalVariable *getDebugVariable() const; |
494 | |
495 | /// Return the operand for the complex address expression referenced by |
496 | /// this DBG_VALUE instruction. |
497 | const MachineOperand &getDebugExpressionOp() const; |
498 | MachineOperand &getDebugExpressionOp(); |
499 | |
500 | /// Return the complex address expression referenced by |
501 | /// this DBG_VALUE instruction. |
502 | const DIExpression *getDebugExpression() const; |
503 | |
504 | /// Return the debug label referenced by |
505 | /// this DBG_LABEL instruction. |
506 | const DILabel *getDebugLabel() const; |
507 | |
508 | /// Fetch the instruction number of this MachineInstr. If it does not have |
509 | /// one already, a new and unique number will be assigned. |
510 | unsigned getDebugInstrNum(); |
511 | |
512 | /// Fetch instruction number of this MachineInstr -- but before it's inserted |
513 | /// into \p MF. Needed for transformations that create an instruction but |
514 | /// don't immediately insert them. |
515 | unsigned getDebugInstrNum(MachineFunction &MF); |
516 | |
517 | /// Examine the instruction number of this MachineInstr. May be zero if |
518 | /// it hasn't been assigned a number yet. |
519 | unsigned peekDebugInstrNum() const { return DebugInstrNum; } |
520 | |
521 | /// Set instruction number of this MachineInstr. Avoid using unless you're |
522 | /// deserializing this information. |
523 | void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; } |
524 | |
525 | /// Drop any variable location debugging information associated with this |
526 | /// instruction. Use when an instruction is modified in such a way that it no |
527 | /// longer defines the value it used to. Variable locations using that value |
528 | /// will be dropped. |
529 | void dropDebugNumber() { DebugInstrNum = 0; } |
530 | |
531 | /// Emit an error referring to the source location of this instruction. |
532 | /// This should only be used for inline assembly that is somehow |
533 | /// impossible to compile. Other errors should have been handled much |
534 | /// earlier. |
535 | /// |
536 | /// If this method returns, the caller should try to recover from the error. |
537 | void emitError(StringRef Msg) const; |
538 | |
539 | /// Returns the target instruction descriptor of this MachineInstr. |
540 | const MCInstrDesc &getDesc() const { return *MCID; } |
541 | |
542 | /// Returns the opcode of this MachineInstr. |
543 | unsigned getOpcode() const { return MCID->Opcode; } |
544 | |
545 | /// Retuns the total number of operands. |
546 | unsigned getNumOperands() const { return NumOperands; } |
547 | |
548 | /// Returns the total number of operands which are debug locations. |
549 | unsigned getNumDebugOperands() const { |
550 | return std::distance(first: debug_operands().begin(), last: debug_operands().end()); |
551 | } |
552 | |
553 | const MachineOperand& getOperand(unsigned i) const { |
554 | assert(i < getNumOperands() && "getOperand() out of range!" ); |
555 | return Operands[i]; |
556 | } |
557 | MachineOperand& getOperand(unsigned i) { |
558 | assert(i < getNumOperands() && "getOperand() out of range!" ); |
559 | return Operands[i]; |
560 | } |
561 | |
562 | MachineOperand &getDebugOperand(unsigned Index) { |
563 | assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!" ); |
564 | return *(debug_operands().begin() + Index); |
565 | } |
566 | const MachineOperand &getDebugOperand(unsigned Index) const { |
567 | assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!" ); |
568 | return *(debug_operands().begin() + Index); |
569 | } |
570 | |
571 | /// Returns whether this debug value has at least one debug operand with the |
572 | /// register \p Reg. |
573 | bool hasDebugOperandForReg(Register Reg) const { |
574 | return any_of(Range: debug_operands(), P: [Reg](const MachineOperand &Op) { |
575 | return Op.isReg() && Op.getReg() == Reg; |
576 | }); |
577 | } |
578 | |
579 | /// Returns a range of all of the operands that correspond to a debug use of |
580 | /// \p Reg. |
581 | template <typename Operand, typename Instruction> |
582 | static iterator_range< |
583 | filter_iterator<Operand *, std::function<bool(Operand &Op)>>> |
584 | getDebugOperandsForReg(Instruction *MI, Register Reg) { |
585 | std::function<bool(Operand & Op)> OpUsesReg( |
586 | [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; }); |
587 | return make_filter_range(MI->debug_operands(), OpUsesReg); |
588 | } |
589 | iterator_range<filter_iterator<const MachineOperand *, |
590 | std::function<bool(const MachineOperand &Op)>>> |
591 | getDebugOperandsForReg(Register Reg) const { |
592 | return MachineInstr::getDebugOperandsForReg<const MachineOperand, |
593 | const MachineInstr>(MI: this, Reg); |
594 | } |
595 | iterator_range<filter_iterator<MachineOperand *, |
596 | std::function<bool(MachineOperand &Op)>>> |
597 | getDebugOperandsForReg(Register Reg) { |
598 | return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>( |
599 | MI: this, Reg); |
600 | } |
601 | |
602 | bool isDebugOperand(const MachineOperand *Op) const { |
603 | return Op >= adl_begin(range: debug_operands()) && Op <= adl_end(range: debug_operands()); |
604 | } |
605 | |
606 | unsigned getDebugOperandIndex(const MachineOperand *Op) const { |
607 | assert(isDebugOperand(Op) && "Expected a debug operand." ); |
608 | return std::distance(first: adl_begin(range: debug_operands()), last: Op); |
609 | } |
610 | |
611 | /// Returns the total number of definitions. |
612 | unsigned getNumDefs() const { |
613 | return getNumExplicitDefs() + MCID->implicit_defs().size(); |
614 | } |
615 | |
616 | /// Returns true if the instruction has implicit definition. |
617 | bool hasImplicitDef() const { |
618 | for (const MachineOperand &MO : implicit_operands()) |
619 | if (MO.isDef() && MO.isImplicit()) |
620 | return true; |
621 | return false; |
622 | } |
623 | |
624 | /// Returns the implicit operands number. |
625 | unsigned getNumImplicitOperands() const { |
626 | return getNumOperands() - getNumExplicitOperands(); |
627 | } |
628 | |
629 | /// Return true if operand \p OpIdx is a subregister index. |
630 | bool isOperandSubregIdx(unsigned OpIdx) const { |
631 | assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type." ); |
632 | if (isExtractSubreg() && OpIdx == 2) |
633 | return true; |
634 | if (isInsertSubreg() && OpIdx == 3) |
635 | return true; |
636 | if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) |
637 | return true; |
638 | if (isSubregToReg() && OpIdx == 3) |
639 | return true; |
640 | return false; |
641 | } |
642 | |
643 | /// Returns the number of non-implicit operands. |
644 | unsigned getNumExplicitOperands() const; |
645 | |
646 | /// Returns the number of non-implicit definitions. |
647 | unsigned getNumExplicitDefs() const; |
648 | |
649 | /// iterator/begin/end - Iterate over all operands of a machine instruction. |
650 | using mop_iterator = MachineOperand *; |
651 | using const_mop_iterator = const MachineOperand *; |
652 | |
653 | mop_iterator operands_begin() { return Operands; } |
654 | mop_iterator operands_end() { return Operands + NumOperands; } |
655 | |
656 | const_mop_iterator operands_begin() const { return Operands; } |
657 | const_mop_iterator operands_end() const { return Operands + NumOperands; } |
658 | |
659 | iterator_range<mop_iterator> operands() { |
660 | return make_range(x: operands_begin(), y: operands_end()); |
661 | } |
662 | iterator_range<const_mop_iterator> operands() const { |
663 | return make_range(x: operands_begin(), y: operands_end()); |
664 | } |
665 | iterator_range<mop_iterator> explicit_operands() { |
666 | return make_range(x: operands_begin(), |
667 | y: operands_begin() + getNumExplicitOperands()); |
668 | } |
669 | iterator_range<const_mop_iterator> explicit_operands() const { |
670 | return make_range(x: operands_begin(), |
671 | y: operands_begin() + getNumExplicitOperands()); |
672 | } |
673 | iterator_range<mop_iterator> implicit_operands() { |
674 | return make_range(x: explicit_operands().end(), y: operands_end()); |
675 | } |
676 | iterator_range<const_mop_iterator> implicit_operands() const { |
677 | return make_range(x: explicit_operands().end(), y: operands_end()); |
678 | } |
679 | /// Returns a range over all operands that are used to determine the variable |
680 | /// location for this DBG_VALUE instruction. |
681 | iterator_range<mop_iterator> debug_operands() { |
682 | assert((isDebugValueLike()) && "Must be a debug value instruction." ); |
683 | return isNonListDebugValue() |
684 | ? make_range(x: operands_begin(), y: operands_begin() + 1) |
685 | : make_range(x: operands_begin() + 2, y: operands_end()); |
686 | } |
687 | /// \copydoc debug_operands() |
688 | iterator_range<const_mop_iterator> debug_operands() const { |
689 | assert((isDebugValueLike()) && "Must be a debug value instruction." ); |
690 | return isNonListDebugValue() |
691 | ? make_range(x: operands_begin(), y: operands_begin() + 1) |
692 | : make_range(x: operands_begin() + 2, y: operands_end()); |
693 | } |
694 | /// Returns a range over all explicit operands that are register definitions. |
695 | /// Implicit definition are not included! |
696 | iterator_range<mop_iterator> defs() { |
697 | return make_range(x: operands_begin(), |
698 | y: operands_begin() + getNumExplicitDefs()); |
699 | } |
700 | /// \copydoc defs() |
701 | iterator_range<const_mop_iterator> defs() const { |
702 | return make_range(x: operands_begin(), |
703 | y: operands_begin() + getNumExplicitDefs()); |
704 | } |
705 | /// Returns a range that includes all operands that are register uses. |
706 | /// This may include unrelated operands which are not register uses. |
707 | iterator_range<mop_iterator> uses() { |
708 | return make_range(x: operands_begin() + getNumExplicitDefs(), y: operands_end()); |
709 | } |
710 | /// \copydoc uses() |
711 | iterator_range<const_mop_iterator> uses() const { |
712 | return make_range(x: operands_begin() + getNumExplicitDefs(), y: operands_end()); |
713 | } |
714 | iterator_range<mop_iterator> explicit_uses() { |
715 | return make_range(x: operands_begin() + getNumExplicitDefs(), |
716 | y: operands_begin() + getNumExplicitOperands()); |
717 | } |
718 | iterator_range<const_mop_iterator> explicit_uses() const { |
719 | return make_range(x: operands_begin() + getNumExplicitDefs(), |
720 | y: operands_begin() + getNumExplicitOperands()); |
721 | } |
722 | |
723 | using filtered_mop_iterator = |
724 | filter_iterator<mop_iterator, bool (*)(const MachineOperand &)>; |
725 | using filtered_const_mop_iterator = |
726 | filter_iterator<const_mop_iterator, bool (*)(const MachineOperand &)>; |
727 | |
728 | /// Returns an iterator range over all operands that are (explicit or |
729 | /// implicit) register defs. |
730 | iterator_range<filtered_mop_iterator> all_defs() { |
731 | return make_filter_range(Range: operands(), Pred: opIsRegDef); |
732 | } |
733 | /// \copydoc all_defs() |
734 | iterator_range<filtered_const_mop_iterator> all_defs() const { |
735 | return make_filter_range(Range: operands(), Pred: opIsRegDef); |
736 | } |
737 | |
738 | /// Returns an iterator range over all operands that are (explicit or |
739 | /// implicit) register uses. |
740 | iterator_range<filtered_mop_iterator> all_uses() { |
741 | return make_filter_range(Range: uses(), Pred: opIsRegUse); |
742 | } |
743 | /// \copydoc all_uses() |
744 | iterator_range<filtered_const_mop_iterator> all_uses() const { |
745 | return make_filter_range(Range: uses(), Pred: opIsRegUse); |
746 | } |
747 | |
748 | /// Returns the number of the operand iterator \p I points to. |
749 | unsigned getOperandNo(const_mop_iterator I) const { |
750 | return I - operands_begin(); |
751 | } |
752 | |
753 | /// Access to memory operands of the instruction. If there are none, that does |
754 | /// not imply anything about whether the function accesses memory. Instead, |
755 | /// the caller must behave conservatively. |
756 | ArrayRef<MachineMemOperand *> memoperands() const { |
757 | if (!Info) |
758 | return {}; |
759 | |
760 | if (Info.is<EIIK_MMO>()) |
761 | return ArrayRef(Info.getAddrOfZeroTagPointer(), 1); |
762 | |
763 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
764 | return EI->getMMOs(); |
765 | |
766 | return {}; |
767 | } |
768 | |
769 | /// Access to memory operands of the instruction. |
770 | /// |
771 | /// If `memoperands_begin() == memoperands_end()`, that does not imply |
772 | /// anything about whether the function accesses memory. Instead, the caller |
773 | /// must behave conservatively. |
774 | mmo_iterator memoperands_begin() const { return memoperands().begin(); } |
775 | |
776 | /// Access to memory operands of the instruction. |
777 | /// |
778 | /// If `memoperands_begin() == memoperands_end()`, that does not imply |
779 | /// anything about whether the function accesses memory. Instead, the caller |
780 | /// must behave conservatively. |
781 | mmo_iterator memoperands_end() const { return memoperands().end(); } |
782 | |
783 | /// Return true if we don't have any memory operands which described the |
784 | /// memory access done by this instruction. If this is true, calling code |
785 | /// must be conservative. |
786 | bool memoperands_empty() const { return memoperands().empty(); } |
787 | |
788 | /// Return true if this instruction has exactly one MachineMemOperand. |
789 | bool hasOneMemOperand() const { return memoperands().size() == 1; } |
790 | |
791 | /// Return the number of memory operands. |
792 | unsigned getNumMemOperands() const { return memoperands().size(); } |
793 | |
794 | /// Helper to extract a pre-instruction symbol if one has been added. |
795 | MCSymbol *getPreInstrSymbol() const { |
796 | if (!Info) |
797 | return nullptr; |
798 | if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>()) |
799 | return S; |
800 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
801 | return EI->getPreInstrSymbol(); |
802 | |
803 | return nullptr; |
804 | } |
805 | |
806 | /// Helper to extract a post-instruction symbol if one has been added. |
807 | MCSymbol *getPostInstrSymbol() const { |
808 | if (!Info) |
809 | return nullptr; |
810 | if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>()) |
811 | return S; |
812 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
813 | return EI->getPostInstrSymbol(); |
814 | |
815 | return nullptr; |
816 | } |
817 | |
818 | /// Helper to extract a heap alloc marker if one has been added. |
819 | MDNode *getHeapAllocMarker() const { |
820 | if (!Info) |
821 | return nullptr; |
822 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
823 | return EI->getHeapAllocMarker(); |
824 | |
825 | return nullptr; |
826 | } |
827 | |
828 | /// Helper to extract PCSections metadata target sections. |
829 | MDNode *getPCSections() const { |
830 | if (!Info) |
831 | return nullptr; |
832 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
833 | return EI->getPCSections(); |
834 | |
835 | return nullptr; |
836 | } |
837 | |
838 | /// Helper to extract a CFI type hash if one has been added. |
839 | uint32_t getCFIType() const { |
840 | if (!Info) |
841 | return 0; |
842 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
843 | return EI->getCFIType(); |
844 | |
845 | return 0; |
846 | } |
847 | |
848 | /// API for querying MachineInstr properties. They are the same as MCInstrDesc |
849 | /// queries but they are bundle aware. |
850 | |
851 | enum QueryType { |
852 | IgnoreBundle, // Ignore bundles |
853 | AnyInBundle, // Return true if any instruction in bundle has property |
854 | AllInBundle // Return true if all instructions in bundle have property |
855 | }; |
856 | |
857 | /// Return true if the instruction (or in the case of a bundle, |
858 | /// the instructions inside the bundle) has the specified property. |
859 | /// The first argument is the property being queried. |
860 | /// The second argument indicates whether the query should look inside |
861 | /// instruction bundles. |
862 | bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { |
863 | assert(MCFlag < 64 && |
864 | "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle." ); |
865 | // Inline the fast path for unbundled or bundle-internal instructions. |
866 | if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) |
867 | return getDesc().getFlags() & (1ULL << MCFlag); |
868 | |
869 | // If this is the first instruction in a bundle, take the slow path. |
870 | return hasPropertyInBundle(Mask: 1ULL << MCFlag, Type); |
871 | } |
872 | |
873 | /// Return true if this is an instruction that should go through the usual |
874 | /// legalization steps. |
875 | bool isPreISelOpcode(QueryType Type = IgnoreBundle) const { |
876 | return hasProperty(MCFlag: MCID::PreISelOpcode, Type); |
877 | } |
878 | |
879 | /// Return true if this instruction can have a variable number of operands. |
880 | /// In this case, the variable operands will be after the normal |
881 | /// operands but before the implicit definitions and uses (if any are |
882 | /// present). |
883 | bool isVariadic(QueryType Type = IgnoreBundle) const { |
884 | return hasProperty(MCFlag: MCID::Variadic, Type); |
885 | } |
886 | |
887 | /// Set if this instruction has an optional definition, e.g. |
888 | /// ARM instructions which can set condition code if 's' bit is set. |
889 | bool hasOptionalDef(QueryType Type = IgnoreBundle) const { |
890 | return hasProperty(MCFlag: MCID::HasOptionalDef, Type); |
891 | } |
892 | |
893 | /// Return true if this is a pseudo instruction that doesn't |
894 | /// correspond to a real machine instruction. |
895 | bool isPseudo(QueryType Type = IgnoreBundle) const { |
896 | return hasProperty(MCFlag: MCID::Pseudo, Type); |
897 | } |
898 | |
899 | /// Return true if this instruction doesn't produce any output in the form of |
900 | /// executable instructions. |
901 | bool isMetaInstruction(QueryType Type = IgnoreBundle) const { |
902 | return hasProperty(MCFlag: MCID::Meta, Type); |
903 | } |
904 | |
905 | bool isReturn(QueryType Type = AnyInBundle) const { |
906 | return hasProperty(MCFlag: MCID::Return, Type); |
907 | } |
908 | |
909 | /// Return true if this is an instruction that marks the end of an EH scope, |
910 | /// i.e., a catchpad or a cleanuppad instruction. |
911 | bool isEHScopeReturn(QueryType Type = AnyInBundle) const { |
912 | return hasProperty(MCFlag: MCID::EHScopeReturn, Type); |
913 | } |
914 | |
915 | bool isCall(QueryType Type = AnyInBundle) const { |
916 | return hasProperty(MCFlag: MCID::Call, Type); |
917 | } |
918 | |
919 | /// Return true if this is a call instruction that may have an associated |
920 | /// call site entry in the debug info. |
921 | bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const; |
922 | /// Return true if copying, moving, or erasing this instruction requires |
923 | /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo, |
924 | /// \ref eraseCallSiteInfo). |
925 | bool shouldUpdateCallSiteInfo() const; |
926 | |
927 | /// Returns true if the specified instruction stops control flow |
928 | /// from executing the instruction immediately following it. Examples include |
929 | /// unconditional branches and return instructions. |
930 | bool isBarrier(QueryType Type = AnyInBundle) const { |
931 | return hasProperty(MCFlag: MCID::Barrier, Type); |
932 | } |
933 | |
934 | /// Returns true if this instruction part of the terminator for a basic block. |
935 | /// Typically this is things like return and branch instructions. |
936 | /// |
937 | /// Various passes use this to insert code into the bottom of a basic block, |
938 | /// but before control flow occurs. |
939 | bool isTerminator(QueryType Type = AnyInBundle) const { |
940 | return hasProperty(MCFlag: MCID::Terminator, Type); |
941 | } |
942 | |
943 | /// Returns true if this is a conditional, unconditional, or indirect branch. |
944 | /// Predicates below can be used to discriminate between |
945 | /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to |
946 | /// get more information. |
947 | bool isBranch(QueryType Type = AnyInBundle) const { |
948 | return hasProperty(MCFlag: MCID::Branch, Type); |
949 | } |
950 | |
951 | /// Return true if this is an indirect branch, such as a |
952 | /// branch through a register. |
953 | bool isIndirectBranch(QueryType Type = AnyInBundle) const { |
954 | return hasProperty(MCFlag: MCID::IndirectBranch, Type); |
955 | } |
956 | |
957 | /// Return true if this is a branch which may fall |
958 | /// through to the next instruction or may transfer control flow to some other |
959 | /// block. The TargetInstrInfo::analyzeBranch method can be used to get more |
960 | /// information about this branch. |
961 | bool isConditionalBranch(QueryType Type = AnyInBundle) const { |
962 | return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type); |
963 | } |
964 | |
965 | /// Return true if this is a branch which always |
966 | /// transfers control flow to some other block. The |
967 | /// TargetInstrInfo::analyzeBranch method can be used to get more information |
968 | /// about this branch. |
969 | bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { |
970 | return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type); |
971 | } |
972 | |
973 | /// Return true if this instruction has a predicate operand that |
974 | /// controls execution. It may be set to 'always', or may be set to other |
975 | /// values. There are various methods in TargetInstrInfo that can be used to |
976 | /// control and modify the predicate in this instruction. |
977 | bool isPredicable(QueryType Type = AllInBundle) const { |
978 | // If it's a bundle than all bundled instructions must be predicable for this |
979 | // to return true. |
980 | return hasProperty(MCFlag: MCID::Predicable, Type); |
981 | } |
982 | |
983 | /// Return true if this instruction is a comparison. |
984 | bool isCompare(QueryType Type = IgnoreBundle) const { |
985 | return hasProperty(MCFlag: MCID::Compare, Type); |
986 | } |
987 | |
988 | /// Return true if this instruction is a move immediate |
989 | /// (including conditional moves) instruction. |
990 | bool isMoveImmediate(QueryType Type = IgnoreBundle) const { |
991 | return hasProperty(MCFlag: MCID::MoveImm, Type); |
992 | } |
993 | |
994 | /// Return true if this instruction is a register move. |
995 | /// (including moving values from subreg to reg) |
996 | bool isMoveReg(QueryType Type = IgnoreBundle) const { |
997 | return hasProperty(MCFlag: MCID::MoveReg, Type); |
998 | } |
999 | |
1000 | /// Return true if this instruction is a bitcast instruction. |
1001 | bool isBitcast(QueryType Type = IgnoreBundle) const { |
1002 | return hasProperty(MCFlag: MCID::Bitcast, Type); |
1003 | } |
1004 | |
1005 | /// Return true if this instruction is a select instruction. |
1006 | bool isSelect(QueryType Type = IgnoreBundle) const { |
1007 | return hasProperty(MCFlag: MCID::Select, Type); |
1008 | } |
1009 | |
1010 | /// Return true if this instruction cannot be safely duplicated. |
1011 | /// For example, if the instruction has a unique labels attached |
1012 | /// to it, duplicating it would cause multiple definition errors. |
1013 | bool isNotDuplicable(QueryType Type = AnyInBundle) const { |
1014 | if (getPreInstrSymbol() || getPostInstrSymbol()) |
1015 | return true; |
1016 | return hasProperty(MCFlag: MCID::NotDuplicable, Type); |
1017 | } |
1018 | |
1019 | /// Return true if this instruction is convergent. |
1020 | /// Convergent instructions can not be made control-dependent on any |
1021 | /// additional values. |
1022 | bool isConvergent(QueryType Type = AnyInBundle) const { |
1023 | if (isInlineAsm()) { |
1024 | unsigned = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm(); |
1025 | if (ExtraInfo & InlineAsm::Extra_IsConvergent) |
1026 | return true; |
1027 | } |
1028 | if (getFlag(Flag: NoConvergent)) |
1029 | return false; |
1030 | return hasProperty(MCFlag: MCID::Convergent, Type); |
1031 | } |
1032 | |
1033 | /// Returns true if the specified instruction has a delay slot |
1034 | /// which must be filled by the code generator. |
1035 | bool hasDelaySlot(QueryType Type = AnyInBundle) const { |
1036 | return hasProperty(MCFlag: MCID::DelaySlot, Type); |
1037 | } |
1038 | |
1039 | /// Return true for instructions that can be folded as |
1040 | /// memory operands in other instructions. The most common use for this |
1041 | /// is instructions that are simple loads from memory that don't modify |
1042 | /// the loaded value in any way, but it can also be used for instructions |
1043 | /// that can be expressed as constant-pool loads, such as V_SETALLONES |
1044 | /// on x86, to allow them to be folded when it is beneficial. |
1045 | /// This should only be set on instructions that return a value in their |
1046 | /// only virtual register definition. |
1047 | bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { |
1048 | return hasProperty(MCFlag: MCID::FoldableAsLoad, Type); |
1049 | } |
1050 | |
1051 | /// Return true if this instruction behaves |
1052 | /// the same way as the generic REG_SEQUENCE instructions. |
1053 | /// E.g., on ARM, |
1054 | /// dX VMOVDRR rY, rZ |
1055 | /// is equivalent to |
1056 | /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. |
1057 | /// |
1058 | /// Note that for the optimizers to be able to take advantage of |
1059 | /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be |
1060 | /// override accordingly. |
1061 | bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { |
1062 | return hasProperty(MCFlag: MCID::RegSequence, Type); |
1063 | } |
1064 | |
1065 | /// Return true if this instruction behaves |
1066 | /// the same way as the generic EXTRACT_SUBREG instructions. |
1067 | /// E.g., on ARM, |
1068 | /// rX, rY VMOVRRD dZ |
1069 | /// is equivalent to two EXTRACT_SUBREG: |
1070 | /// rX = EXTRACT_SUBREG dZ, ssub_0 |
1071 | /// rY = EXTRACT_SUBREG dZ, ssub_1 |
1072 | /// |
1073 | /// Note that for the optimizers to be able to take advantage of |
1074 | /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be |
1075 | /// override accordingly. |
1076 | bool (QueryType Type = IgnoreBundle) const { |
1077 | return hasProperty(MCFlag: MCID::ExtractSubreg, Type); |
1078 | } |
1079 | |
1080 | /// Return true if this instruction behaves |
1081 | /// the same way as the generic INSERT_SUBREG instructions. |
1082 | /// E.g., on ARM, |
1083 | /// dX = VSETLNi32 dY, rZ, Imm |
1084 | /// is equivalent to a INSERT_SUBREG: |
1085 | /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) |
1086 | /// |
1087 | /// Note that for the optimizers to be able to take advantage of |
1088 | /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be |
1089 | /// override accordingly. |
1090 | bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { |
1091 | return hasProperty(MCFlag: MCID::InsertSubreg, Type); |
1092 | } |
1093 | |
1094 | //===--------------------------------------------------------------------===// |
1095 | // Side Effect Analysis |
1096 | //===--------------------------------------------------------------------===// |
1097 | |
1098 | /// Return true if this instruction could possibly read memory. |
1099 | /// Instructions with this flag set are not necessarily simple load |
1100 | /// instructions, they may load a value and modify it, for example. |
1101 | bool mayLoad(QueryType Type = AnyInBundle) const { |
1102 | if (isInlineAsm()) { |
1103 | unsigned = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm(); |
1104 | if (ExtraInfo & InlineAsm::Extra_MayLoad) |
1105 | return true; |
1106 | } |
1107 | return hasProperty(MCFlag: MCID::MayLoad, Type); |
1108 | } |
1109 | |
1110 | /// Return true if this instruction could possibly modify memory. |
1111 | /// Instructions with this flag set are not necessarily simple store |
1112 | /// instructions, they may store a modified value based on their operands, or |
1113 | /// may not actually modify anything, for example. |
1114 | bool mayStore(QueryType Type = AnyInBundle) const { |
1115 | if (isInlineAsm()) { |
1116 | unsigned = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm(); |
1117 | if (ExtraInfo & InlineAsm::Extra_MayStore) |
1118 | return true; |
1119 | } |
1120 | return hasProperty(MCFlag: MCID::MayStore, Type); |
1121 | } |
1122 | |
1123 | /// Return true if this instruction could possibly read or modify memory. |
1124 | bool mayLoadOrStore(QueryType Type = AnyInBundle) const { |
1125 | return mayLoad(Type) || mayStore(Type); |
1126 | } |
1127 | |
1128 | /// Return true if this instruction could possibly raise a floating-point |
1129 | /// exception. This is the case if the instruction is a floating-point |
1130 | /// instruction that can in principle raise an exception, as indicated |
1131 | /// by the MCID::MayRaiseFPException property, *and* at the same time, |
1132 | /// the instruction is used in a context where we expect floating-point |
1133 | /// exceptions are not disabled, as indicated by the NoFPExcept MI flag. |
1134 | bool mayRaiseFPException() const { |
1135 | return hasProperty(MCFlag: MCID::MayRaiseFPException) && |
1136 | !getFlag(Flag: MachineInstr::MIFlag::NoFPExcept); |
1137 | } |
1138 | |
1139 | //===--------------------------------------------------------------------===// |
1140 | // Flags that indicate whether an instruction can be modified by a method. |
1141 | //===--------------------------------------------------------------------===// |
1142 | |
1143 | /// Return true if this may be a 2- or 3-address |
1144 | /// instruction (of the form "X = op Y, Z, ..."), which produces the same |
1145 | /// result if Y and Z are exchanged. If this flag is set, then the |
1146 | /// TargetInstrInfo::commuteInstruction method may be used to hack on the |
1147 | /// instruction. |
1148 | /// |
1149 | /// Note that this flag may be set on instructions that are only commutable |
1150 | /// sometimes. In these cases, the call to commuteInstruction will fail. |
1151 | /// Also note that some instructions require non-trivial modification to |
1152 | /// commute them. |
1153 | bool isCommutable(QueryType Type = IgnoreBundle) const { |
1154 | return hasProperty(MCFlag: MCID::Commutable, Type); |
1155 | } |
1156 | |
1157 | /// Return true if this is a 2-address instruction |
1158 | /// which can be changed into a 3-address instruction if needed. Doing this |
1159 | /// transformation can be profitable in the register allocator, because it |
1160 | /// means that the instruction can use a 2-address form if possible, but |
1161 | /// degrade into a less efficient form if the source and dest register cannot |
1162 | /// be assigned to the same register. For example, this allows the x86 |
1163 | /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which |
1164 | /// is the same speed as the shift but has bigger code size. |
1165 | /// |
1166 | /// If this returns true, then the target must implement the |
1167 | /// TargetInstrInfo::convertToThreeAddress method for this instruction, which |
1168 | /// is allowed to fail if the transformation isn't valid for this specific |
1169 | /// instruction (e.g. shl reg, 4 on x86). |
1170 | /// |
1171 | bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { |
1172 | return hasProperty(MCFlag: MCID::ConvertibleTo3Addr, Type); |
1173 | } |
1174 | |
1175 | /// Return true if this instruction requires |
1176 | /// custom insertion support when the DAG scheduler is inserting it into a |
1177 | /// machine basic block. If this is true for the instruction, it basically |
1178 | /// means that it is a pseudo instruction used at SelectionDAG time that is |
1179 | /// expanded out into magic code by the target when MachineInstrs are formed. |
1180 | /// |
1181 | /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method |
1182 | /// is used to insert this into the MachineBasicBlock. |
1183 | bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { |
1184 | return hasProperty(MCFlag: MCID::UsesCustomInserter, Type); |
1185 | } |
1186 | |
1187 | /// Return true if this instruction requires *adjustment* |
1188 | /// after instruction selection by calling a target hook. For example, this |
1189 | /// can be used to fill in ARM 's' optional operand depending on whether |
1190 | /// the conditional flag register is used. |
1191 | bool hasPostISelHook(QueryType Type = IgnoreBundle) const { |
1192 | return hasProperty(MCFlag: MCID::HasPostISelHook, Type); |
1193 | } |
1194 | |
1195 | /// Returns true if this instruction is a candidate for remat. |
1196 | /// This flag is deprecated, please don't use it anymore. If this |
1197 | /// flag is set, the isReallyTriviallyReMaterializable() method is called to |
1198 | /// verify the instruction is really rematerializable. |
1199 | bool isRematerializable(QueryType Type = AllInBundle) const { |
1200 | // It's only possible to re-mat a bundle if all bundled instructions are |
1201 | // re-materializable. |
1202 | return hasProperty(MCFlag: MCID::Rematerializable, Type); |
1203 | } |
1204 | |
1205 | /// Returns true if this instruction has the same cost (or less) than a move |
1206 | /// instruction. This is useful during certain types of optimizations |
1207 | /// (e.g., remat during two-address conversion or machine licm) |
1208 | /// where we would like to remat or hoist the instruction, but not if it costs |
1209 | /// more than moving the instruction into the appropriate register. Note, we |
1210 | /// are not marking copies from and to the same register class with this flag. |
1211 | bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { |
1212 | // Only returns true for a bundle if all bundled instructions are cheap. |
1213 | return hasProperty(MCFlag: MCID::CheapAsAMove, Type); |
1214 | } |
1215 | |
1216 | /// Returns true if this instruction source operands |
1217 | /// have special register allocation requirements that are not captured by the |
1218 | /// operand register classes. e.g. ARM::STRD's two source registers must be an |
1219 | /// even / odd pair, ARM::STM registers have to be in ascending order. |
1220 | /// Post-register allocation passes should not attempt to change allocations |
1221 | /// for sources of instructions with this flag. |
1222 | bool (QueryType Type = AnyInBundle) const { |
1223 | return hasProperty(MCFlag: MCID::ExtraSrcRegAllocReq, Type); |
1224 | } |
1225 | |
1226 | /// Returns true if this instruction def operands |
1227 | /// have special register allocation requirements that are not captured by the |
1228 | /// operand register classes. e.g. ARM::LDRD's two def registers must be an |
1229 | /// even / odd pair, ARM::LDM registers have to be in ascending order. |
1230 | /// Post-register allocation passes should not attempt to change allocations |
1231 | /// for definitions of instructions with this flag. |
1232 | bool (QueryType Type = AnyInBundle) const { |
1233 | return hasProperty(MCFlag: MCID::ExtraDefRegAllocReq, Type); |
1234 | } |
1235 | |
1236 | enum MICheckType { |
1237 | CheckDefs, // Check all operands for equality |
1238 | CheckKillDead, // Check all operands including kill / dead markers |
1239 | IgnoreDefs, // Ignore all definitions |
1240 | IgnoreVRegDefs // Ignore virtual register definitions |
1241 | }; |
1242 | |
1243 | /// Return true if this instruction is identical to \p Other. |
1244 | /// Two instructions are identical if they have the same opcode and all their |
1245 | /// operands are identical (with respect to MachineOperand::isIdenticalTo()). |
1246 | /// Note that this means liveness related flags (dead, undef, kill) do not |
1247 | /// affect the notion of identical. |
1248 | bool isIdenticalTo(const MachineInstr &Other, |
1249 | MICheckType Check = CheckDefs) const; |
1250 | |
1251 | /// Returns true if this instruction is a debug instruction that represents an |
1252 | /// identical debug value to \p Other. |
1253 | /// This function considers these debug instructions equivalent if they have |
1254 | /// identical variables, debug locations, and debug operands, and if the |
1255 | /// DIExpressions combined with the directness flags are equivalent. |
1256 | bool isEquivalentDbgInstr(const MachineInstr &Other) const; |
1257 | |
1258 | /// Unlink 'this' from the containing basic block, and return it without |
1259 | /// deleting it. |
1260 | /// |
1261 | /// This function can not be used on bundled instructions, use |
1262 | /// removeFromBundle() to remove individual instructions from a bundle. |
1263 | MachineInstr *removeFromParent(); |
1264 | |
1265 | /// Unlink this instruction from its basic block and return it without |
1266 | /// deleting it. |
1267 | /// |
1268 | /// If the instruction is part of a bundle, the other instructions in the |
1269 | /// bundle remain bundled. |
1270 | MachineInstr *removeFromBundle(); |
1271 | |
1272 | /// Unlink 'this' from the containing basic block and delete it. |
1273 | /// |
1274 | /// If this instruction is the header of a bundle, the whole bundle is erased. |
1275 | /// This function can not be used for instructions inside a bundle, use |
1276 | /// eraseFromBundle() to erase individual bundled instructions. |
1277 | void eraseFromParent(); |
1278 | |
1279 | /// Unlink 'this' from its basic block and delete it. |
1280 | /// |
1281 | /// If the instruction is part of a bundle, the other instructions in the |
1282 | /// bundle remain bundled. |
1283 | void eraseFromBundle(); |
1284 | |
1285 | bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } |
1286 | bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } |
1287 | bool isAnnotationLabel() const { |
1288 | return getOpcode() == TargetOpcode::ANNOTATION_LABEL; |
1289 | } |
1290 | |
1291 | /// Returns true if the MachineInstr represents a label. |
1292 | bool isLabel() const { |
1293 | return isEHLabel() || isGCLabel() || isAnnotationLabel(); |
1294 | } |
1295 | |
1296 | bool isCFIInstruction() const { |
1297 | return getOpcode() == TargetOpcode::CFI_INSTRUCTION; |
1298 | } |
1299 | |
1300 | bool isPseudoProbe() const { |
1301 | return getOpcode() == TargetOpcode::PSEUDO_PROBE; |
1302 | } |
1303 | |
1304 | // True if the instruction represents a position in the function. |
1305 | bool isPosition() const { return isLabel() || isCFIInstruction(); } |
1306 | |
1307 | bool isNonListDebugValue() const { |
1308 | return getOpcode() == TargetOpcode::DBG_VALUE; |
1309 | } |
1310 | bool isDebugValueList() const { |
1311 | return getOpcode() == TargetOpcode::DBG_VALUE_LIST; |
1312 | } |
1313 | bool isDebugValue() const { |
1314 | return isNonListDebugValue() || isDebugValueList(); |
1315 | } |
1316 | bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } |
1317 | bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; } |
1318 | bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); } |
1319 | bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; } |
1320 | bool isDebugInstr() const { |
1321 | return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI(); |
1322 | } |
1323 | bool isDebugOrPseudoInstr() const { |
1324 | return isDebugInstr() || isPseudoProbe(); |
1325 | } |
1326 | |
1327 | bool isDebugOffsetImm() const { |
1328 | return isNonListDebugValue() && getDebugOffset().isImm(); |
1329 | } |
1330 | |
1331 | /// A DBG_VALUE is indirect iff the location operand is a register and |
1332 | /// the offset operand is an immediate. |
1333 | bool isIndirectDebugValue() const { |
1334 | return isDebugOffsetImm() && getDebugOperand(Index: 0).isReg(); |
1335 | } |
1336 | |
1337 | /// A DBG_VALUE is an entry value iff its debug expression contains the |
1338 | /// DW_OP_LLVM_entry_value operation. |
1339 | bool isDebugEntryValue() const; |
1340 | |
1341 | /// Return true if the instruction is a debug value which describes a part of |
1342 | /// a variable as unavailable. |
1343 | bool isUndefDebugValue() const { |
1344 | if (!isDebugValue()) |
1345 | return false; |
1346 | // If any $noreg locations are given, this DV is undef. |
1347 | for (const MachineOperand &Op : debug_operands()) |
1348 | if (Op.isReg() && !Op.getReg().isValid()) |
1349 | return true; |
1350 | return false; |
1351 | } |
1352 | |
1353 | bool isJumpTableDebugInfo() const { |
1354 | return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO; |
1355 | } |
1356 | |
1357 | bool isPHI() const { |
1358 | return getOpcode() == TargetOpcode::PHI || |
1359 | getOpcode() == TargetOpcode::G_PHI; |
1360 | } |
1361 | bool isKill() const { return getOpcode() == TargetOpcode::KILL; } |
1362 | bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } |
1363 | bool isInlineAsm() const { |
1364 | return getOpcode() == TargetOpcode::INLINEASM || |
1365 | getOpcode() == TargetOpcode::INLINEASM_BR; |
1366 | } |
1367 | /// Returns true if the register operand can be folded with a load or store |
1368 | /// into a frame index. Does so by checking the InlineAsm::Flag immediate |
1369 | /// operand at OpId - 1. |
1370 | bool mayFoldInlineAsmRegOp(unsigned OpId) const; |
1371 | |
1372 | bool isStackAligningInlineAsm() const; |
1373 | InlineAsm::AsmDialect getInlineAsmDialect() const; |
1374 | |
1375 | bool isInsertSubreg() const { |
1376 | return getOpcode() == TargetOpcode::INSERT_SUBREG; |
1377 | } |
1378 | |
1379 | bool isSubregToReg() const { |
1380 | return getOpcode() == TargetOpcode::SUBREG_TO_REG; |
1381 | } |
1382 | |
1383 | bool isRegSequence() const { |
1384 | return getOpcode() == TargetOpcode::REG_SEQUENCE; |
1385 | } |
1386 | |
1387 | bool isBundle() const { |
1388 | return getOpcode() == TargetOpcode::BUNDLE; |
1389 | } |
1390 | |
1391 | bool isCopy() const { |
1392 | return getOpcode() == TargetOpcode::COPY; |
1393 | } |
1394 | |
1395 | bool isFullCopy() const { |
1396 | return isCopy() && !getOperand(i: 0).getSubReg() && !getOperand(i: 1).getSubReg(); |
1397 | } |
1398 | |
1399 | bool () const { |
1400 | return getOpcode() == TargetOpcode::EXTRACT_SUBREG; |
1401 | } |
1402 | |
1403 | /// Return true if the instruction behaves like a copy. |
1404 | /// This does not include native copy instructions. |
1405 | bool isCopyLike() const { |
1406 | return isCopy() || isSubregToReg(); |
1407 | } |
1408 | |
1409 | /// Return true is the instruction is an identity copy. |
1410 | bool isIdentityCopy() const { |
1411 | return isCopy() && getOperand(i: 0).getReg() == getOperand(i: 1).getReg() && |
1412 | getOperand(i: 0).getSubReg() == getOperand(i: 1).getSubReg(); |
1413 | } |
1414 | |
1415 | /// Return true if this is a transient instruction that is either very likely |
1416 | /// to be eliminated during register allocation (such as copy-like |
1417 | /// instructions), or if this instruction doesn't have an execution-time cost. |
1418 | bool isTransient() const { |
1419 | switch (getOpcode()) { |
1420 | default: |
1421 | return isMetaInstruction(); |
1422 | // Copy-like instructions are usually eliminated during register allocation. |
1423 | case TargetOpcode::PHI: |
1424 | case TargetOpcode::G_PHI: |
1425 | case TargetOpcode::COPY: |
1426 | case TargetOpcode::INSERT_SUBREG: |
1427 | case TargetOpcode::SUBREG_TO_REG: |
1428 | case TargetOpcode::REG_SEQUENCE: |
1429 | return true; |
1430 | } |
1431 | } |
1432 | |
1433 | /// Return the number of instructions inside the MI bundle, excluding the |
1434 | /// bundle header. |
1435 | /// |
1436 | /// This is the number of instructions that MachineBasicBlock::iterator |
1437 | /// skips, 0 for unbundled instructions. |
1438 | unsigned getBundleSize() const; |
1439 | |
1440 | /// Return true if the MachineInstr reads the specified register. |
1441 | /// If TargetRegisterInfo is passed, then it also checks if there |
1442 | /// is a read of a super-register. |
1443 | /// This does not count partial redefines of virtual registers as reads: |
1444 | /// %reg1024:6 = OP. |
1445 | bool readsRegister(Register Reg, |
1446 | const TargetRegisterInfo *TRI = nullptr) const { |
1447 | return findRegisterUseOperandIdx(Reg, isKill: false, TRI) != -1; |
1448 | } |
1449 | |
1450 | /// Return true if the MachineInstr reads the specified virtual register. |
1451 | /// Take into account that a partial define is a |
1452 | /// read-modify-write operation. |
1453 | bool readsVirtualRegister(Register Reg) const { |
1454 | return readsWritesVirtualRegister(Reg).first; |
1455 | } |
1456 | |
1457 | /// Return a pair of bools (reads, writes) indicating if this instruction |
1458 | /// reads or writes Reg. This also considers partial defines. |
1459 | /// If Ops is not null, all operand indices for Reg are added. |
1460 | std::pair<bool,bool> readsWritesVirtualRegister(Register Reg, |
1461 | SmallVectorImpl<unsigned> *Ops = nullptr) const; |
1462 | |
1463 | /// Return true if the MachineInstr kills the specified register. |
1464 | /// If TargetRegisterInfo is passed, then it also checks if there is |
1465 | /// a kill of a super-register. |
1466 | bool killsRegister(Register Reg, |
1467 | const TargetRegisterInfo *TRI = nullptr) const { |
1468 | return findRegisterUseOperandIdx(Reg, isKill: true, TRI) != -1; |
1469 | } |
1470 | |
1471 | /// Return true if the MachineInstr fully defines the specified register. |
1472 | /// If TargetRegisterInfo is passed, then it also checks |
1473 | /// if there is a def of a super-register. |
1474 | /// NOTE: It's ignoring subreg indices on virtual registers. |
1475 | bool definesRegister(Register Reg, |
1476 | const TargetRegisterInfo *TRI = nullptr) const { |
1477 | return findRegisterDefOperandIdx(Reg, isDead: false, Overlap: false, TRI) != -1; |
1478 | } |
1479 | |
1480 | /// Return true if the MachineInstr modifies (fully define or partially |
1481 | /// define) the specified register. |
1482 | /// NOTE: It's ignoring subreg indices on virtual registers. |
1483 | bool modifiesRegister(Register Reg, |
1484 | const TargetRegisterInfo *TRI = nullptr) const { |
1485 | return findRegisterDefOperandIdx(Reg, isDead: false, Overlap: true, TRI) != -1; |
1486 | } |
1487 | |
1488 | /// Returns true if the register is dead in this machine instruction. |
1489 | /// If TargetRegisterInfo is passed, then it also checks |
1490 | /// if there is a dead def of a super-register. |
1491 | bool registerDefIsDead(Register Reg, |
1492 | const TargetRegisterInfo *TRI = nullptr) const { |
1493 | return findRegisterDefOperandIdx(Reg, isDead: true, Overlap: false, TRI) != -1; |
1494 | } |
1495 | |
1496 | /// Returns true if the MachineInstr has an implicit-use operand of exactly |
1497 | /// the given register (not considering sub/super-registers). |
1498 | bool hasRegisterImplicitUseOperand(Register Reg) const; |
1499 | |
1500 | /// Returns the operand index that is a use of the specific register or -1 |
1501 | /// if it is not found. It further tightens the search criteria to a use |
1502 | /// that kills the register if isKill is true. |
1503 | int findRegisterUseOperandIdx(Register Reg, bool isKill = false, |
1504 | const TargetRegisterInfo *TRI = nullptr) const; |
1505 | |
1506 | /// Wrapper for findRegisterUseOperandIdx, it returns |
1507 | /// a pointer to the MachineOperand rather than an index. |
1508 | MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false, |
1509 | const TargetRegisterInfo *TRI = nullptr) { |
1510 | int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); |
1511 | return (Idx == -1) ? nullptr : &getOperand(i: Idx); |
1512 | } |
1513 | |
1514 | const MachineOperand *findRegisterUseOperand( |
1515 | Register Reg, bool isKill = false, |
1516 | const TargetRegisterInfo *TRI = nullptr) const { |
1517 | return const_cast<MachineInstr *>(this)-> |
1518 | findRegisterUseOperand(Reg, isKill, TRI); |
1519 | } |
1520 | |
1521 | /// Returns the operand index that is a def of the specified register or |
1522 | /// -1 if it is not found. If isDead is true, defs that are not dead are |
1523 | /// skipped. If Overlap is true, then it also looks for defs that merely |
1524 | /// overlap the specified register. If TargetRegisterInfo is non-null, |
1525 | /// then it also checks if there is a def of a super-register. |
1526 | /// This may also return a register mask operand when Overlap is true. |
1527 | int findRegisterDefOperandIdx(Register Reg, |
1528 | bool isDead = false, bool Overlap = false, |
1529 | const TargetRegisterInfo *TRI = nullptr) const; |
1530 | |
1531 | /// Wrapper for findRegisterDefOperandIdx, it returns |
1532 | /// a pointer to the MachineOperand rather than an index. |
1533 | MachineOperand * |
1534 | findRegisterDefOperand(Register Reg, bool isDead = false, |
1535 | bool Overlap = false, |
1536 | const TargetRegisterInfo *TRI = nullptr) { |
1537 | int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI); |
1538 | return (Idx == -1) ? nullptr : &getOperand(i: Idx); |
1539 | } |
1540 | |
1541 | const MachineOperand * |
1542 | findRegisterDefOperand(Register Reg, bool isDead = false, |
1543 | bool Overlap = false, |
1544 | const TargetRegisterInfo *TRI = nullptr) const { |
1545 | return const_cast<MachineInstr *>(this)->findRegisterDefOperand( |
1546 | Reg, isDead, Overlap, TRI); |
1547 | } |
1548 | |
1549 | /// Find the index of the first operand in the |
1550 | /// operand list that is used to represent the predicate. It returns -1 if |
1551 | /// none is found. |
1552 | int findFirstPredOperandIdx() const; |
1553 | |
1554 | /// Find the index of the flag word operand that |
1555 | /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if |
1556 | /// getOperand(OpIdx) does not belong to an inline asm operand group. |
1557 | /// |
1558 | /// If GroupNo is not NULL, it will receive the number of the operand group |
1559 | /// containing OpIdx. |
1560 | int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; |
1561 | |
1562 | /// Compute the static register class constraint for operand OpIdx. |
1563 | /// For normal instructions, this is derived from the MCInstrDesc. |
1564 | /// For inline assembly it is derived from the flag words. |
1565 | /// |
1566 | /// Returns NULL if the static register class constraint cannot be |
1567 | /// determined. |
1568 | const TargetRegisterClass* |
1569 | getRegClassConstraint(unsigned OpIdx, |
1570 | const TargetInstrInfo *TII, |
1571 | const TargetRegisterInfo *TRI) const; |
1572 | |
1573 | /// Applies the constraints (def/use) implied by this MI on \p Reg to |
1574 | /// the given \p CurRC. |
1575 | /// If \p ExploreBundle is set and MI is part of a bundle, all the |
1576 | /// instructions inside the bundle will be taken into account. In other words, |
1577 | /// this method accumulates all the constraints of the operand of this MI and |
1578 | /// the related bundle if MI is a bundle or inside a bundle. |
1579 | /// |
1580 | /// Returns the register class that satisfies both \p CurRC and the |
1581 | /// constraints set by MI. Returns NULL if such a register class does not |
1582 | /// exist. |
1583 | /// |
1584 | /// \pre CurRC must not be NULL. |
1585 | const TargetRegisterClass *getRegClassConstraintEffectForVReg( |
1586 | Register Reg, const TargetRegisterClass *CurRC, |
1587 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, |
1588 | bool ExploreBundle = false) const; |
1589 | |
1590 | /// Applies the constraints (def/use) implied by the \p OpIdx operand |
1591 | /// to the given \p CurRC. |
1592 | /// |
1593 | /// Returns the register class that satisfies both \p CurRC and the |
1594 | /// constraints set by \p OpIdx MI. Returns NULL if such a register class |
1595 | /// does not exist. |
1596 | /// |
1597 | /// \pre CurRC must not be NULL. |
1598 | /// \pre The operand at \p OpIdx must be a register. |
1599 | const TargetRegisterClass * |
1600 | getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, |
1601 | const TargetInstrInfo *TII, |
1602 | const TargetRegisterInfo *TRI) const; |
1603 | |
1604 | /// Add a tie between the register operands at DefIdx and UseIdx. |
1605 | /// The tie will cause the register allocator to ensure that the two |
1606 | /// operands are assigned the same physical register. |
1607 | /// |
1608 | /// Tied operands are managed automatically for explicit operands in the |
1609 | /// MCInstrDesc. This method is for exceptional cases like inline asm. |
1610 | void tieOperands(unsigned DefIdx, unsigned UseIdx); |
1611 | |
1612 | /// Given the index of a tied register operand, find the |
1613 | /// operand it is tied to. Defs are tied to uses and vice versa. Returns the |
1614 | /// index of the tied operand which must exist. |
1615 | unsigned findTiedOperandIdx(unsigned OpIdx) const; |
1616 | |
1617 | /// Given the index of a register def operand, |
1618 | /// check if the register def is tied to a source operand, due to either |
1619 | /// two-address elimination or inline assembly constraints. Returns the |
1620 | /// first tied use operand index by reference if UseOpIdx is not null. |
1621 | bool isRegTiedToUseOperand(unsigned DefOpIdx, |
1622 | unsigned *UseOpIdx = nullptr) const { |
1623 | const MachineOperand &MO = getOperand(i: DefOpIdx); |
1624 | if (!MO.isReg() || !MO.isDef() || !MO.isTied()) |
1625 | return false; |
1626 | if (UseOpIdx) |
1627 | *UseOpIdx = findTiedOperandIdx(OpIdx: DefOpIdx); |
1628 | return true; |
1629 | } |
1630 | |
1631 | /// Return true if the use operand of the specified index is tied to a def |
1632 | /// operand. It also returns the def operand index by reference if DefOpIdx |
1633 | /// is not null. |
1634 | bool isRegTiedToDefOperand(unsigned UseOpIdx, |
1635 | unsigned *DefOpIdx = nullptr) const { |
1636 | const MachineOperand &MO = getOperand(i: UseOpIdx); |
1637 | if (!MO.isReg() || !MO.isUse() || !MO.isTied()) |
1638 | return false; |
1639 | if (DefOpIdx) |
1640 | *DefOpIdx = findTiedOperandIdx(OpIdx: UseOpIdx); |
1641 | return true; |
1642 | } |
1643 | |
1644 | /// Clears kill flags on all operands. |
1645 | void clearKillInfo(); |
1646 | |
1647 | /// Replace all occurrences of FromReg with ToReg:SubIdx, |
1648 | /// properly composing subreg indices where necessary. |
1649 | void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, |
1650 | const TargetRegisterInfo &RegInfo); |
1651 | |
1652 | /// We have determined MI kills a register. Look for the |
1653 | /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, |
1654 | /// add a implicit operand if it's not found. Returns true if the operand |
1655 | /// exists / is added. |
1656 | bool addRegisterKilled(Register IncomingReg, |
1657 | const TargetRegisterInfo *RegInfo, |
1658 | bool AddIfNotFound = false); |
1659 | |
1660 | /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes |
1661 | /// all aliasing registers. |
1662 | void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo); |
1663 | |
1664 | /// We have determined MI defined a register without a use. |
1665 | /// Look for the operand that defines it and mark it as IsDead. If |
1666 | /// AddIfNotFound is true, add a implicit operand if it's not found. Returns |
1667 | /// true if the operand exists / is added. |
1668 | bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, |
1669 | bool AddIfNotFound = false); |
1670 | |
1671 | /// Clear all dead flags on operands defining register @p Reg. |
1672 | void clearRegisterDeads(Register Reg); |
1673 | |
1674 | /// Mark all subregister defs of register @p Reg with the undef flag. |
1675 | /// This function is used when we determined to have a subregister def in an |
1676 | /// otherwise undefined super register. |
1677 | void setRegisterDefReadUndef(Register Reg, bool IsUndef = true); |
1678 | |
1679 | /// We have determined MI defines a register. Make sure there is an operand |
1680 | /// defining Reg. |
1681 | void addRegisterDefined(Register Reg, |
1682 | const TargetRegisterInfo *RegInfo = nullptr); |
1683 | |
1684 | /// Mark every physreg used by this instruction as |
1685 | /// dead except those in the UsedRegs list. |
1686 | /// |
1687 | /// On instructions with register mask operands, also add implicit-def |
1688 | /// operands for all registers in UsedRegs. |
1689 | void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, |
1690 | const TargetRegisterInfo &TRI); |
1691 | |
1692 | /// Return true if it is safe to move this instruction. If |
1693 | /// SawStore is set to true, it means that there is a store (or call) between |
1694 | /// the instruction's location and its intended destination. |
1695 | bool isSafeToMove(AAResults *AA, bool &SawStore) const; |
1696 | |
1697 | /// Returns true if this instruction's memory access aliases the memory |
1698 | /// access of Other. |
1699 | // |
1700 | /// Assumes any physical registers used to compute addresses |
1701 | /// have the same value for both instructions. Returns false if neither |
1702 | /// instruction writes to memory. |
1703 | /// |
1704 | /// @param AA Optional alias analysis, used to compare memory operands. |
1705 | /// @param Other MachineInstr to check aliasing against. |
1706 | /// @param UseTBAA Whether to pass TBAA information to alias analysis. |
1707 | bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const; |
1708 | |
1709 | /// Return true if this instruction may have an ordered |
1710 | /// or volatile memory reference, or if the information describing the memory |
1711 | /// reference is not available. Return false if it is known to have no |
1712 | /// ordered or volatile memory references. |
1713 | bool hasOrderedMemoryRef() const; |
1714 | |
1715 | /// Return true if this load instruction never traps and points to a memory |
1716 | /// location whose value doesn't change during the execution of this function. |
1717 | /// |
1718 | /// Examples include loading a value from the constant pool or from the |
1719 | /// argument area of a function (if it does not change). If the instruction |
1720 | /// does multiple loads, this returns true only if all of the loads are |
1721 | /// dereferenceable and invariant. |
1722 | bool isDereferenceableInvariantLoad() const; |
1723 | |
1724 | /// If the specified instruction is a PHI that always merges together the |
1725 | /// same virtual register, return the register, otherwise return 0. |
1726 | unsigned isConstantValuePHI() const; |
1727 | |
1728 | /// Return true if this instruction has side effects that are not modeled |
1729 | /// by mayLoad / mayStore, etc. |
1730 | /// For all instructions, the property is encoded in MCInstrDesc::Flags |
1731 | /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is |
1732 | /// INLINEASM instruction, in which case the side effect property is encoded |
1733 | /// in one of its operands (see InlineAsm::Extra_HasSideEffect). |
1734 | /// |
1735 | bool hasUnmodeledSideEffects() const; |
1736 | |
1737 | /// Returns true if it is illegal to fold a load across this instruction. |
1738 | bool isLoadFoldBarrier() const; |
1739 | |
1740 | /// Return true if all the defs of this instruction are dead. |
1741 | bool allDefsAreDead() const; |
1742 | |
1743 | /// Return true if all the implicit defs of this instruction are dead. |
1744 | bool allImplicitDefsAreDead() const; |
1745 | |
1746 | /// Return a valid size if the instruction is a spill instruction. |
1747 | std::optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const; |
1748 | |
1749 | /// Return a valid size if the instruction is a folded spill instruction. |
1750 | std::optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const; |
1751 | |
1752 | /// Return a valid size if the instruction is a restore instruction. |
1753 | std::optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const; |
1754 | |
1755 | /// Return a valid size if the instruction is a folded restore instruction. |
1756 | std::optional<unsigned> |
1757 | getFoldedRestoreSize(const TargetInstrInfo *TII) const; |
1758 | |
1759 | /// Copy implicit register operands from specified |
1760 | /// instruction to this instruction. |
1761 | void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI); |
1762 | |
1763 | /// Debugging support |
1764 | /// @{ |
1765 | /// Determine the generic type to be printed (if needed) on uses and defs. |
1766 | LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, |
1767 | const MachineRegisterInfo &MRI) const; |
1768 | |
1769 | /// Return true when an instruction has tied register that can't be determined |
1770 | /// by the instruction's descriptor. This is useful for MIR printing, to |
1771 | /// determine whether we need to print the ties or not. |
1772 | bool hasComplexRegisterTies() const; |
1773 | |
1774 | /// Print this MI to \p OS. |
1775 | /// Don't print information that can be inferred from other instructions if |
1776 | /// \p IsStandalone is false. It is usually true when only a fragment of the |
1777 | /// function is printed. |
1778 | /// Only print the defs and the opcode if \p SkipOpers is true. |
1779 | /// Otherwise, also print operands if \p SkipDebugLoc is true. |
1780 | /// Otherwise, also print the debug loc, with a terminating newline. |
1781 | /// \p TII is used to print the opcode name. If it's not present, but the |
1782 | /// MI is in a function, the opcode will be printed using the function's TII. |
1783 | void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false, |
1784 | bool SkipDebugLoc = false, bool AddNewLine = true, |
1785 | const TargetInstrInfo *TII = nullptr) const; |
1786 | void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true, |
1787 | bool SkipOpers = false, bool SkipDebugLoc = false, |
1788 | bool AddNewLine = true, |
1789 | const TargetInstrInfo *TII = nullptr) const; |
1790 | void dump() const; |
1791 | /// Print on dbgs() the current instruction and the instructions defining its |
1792 | /// operands and so on until we reach \p MaxDepth. |
1793 | void dumpr(const MachineRegisterInfo &MRI, |
1794 | unsigned MaxDepth = UINT_MAX) const; |
1795 | /// @} |
1796 | |
1797 | //===--------------------------------------------------------------------===// |
1798 | // Accessors used to build up machine instructions. |
1799 | |
1800 | /// Add the specified operand to the instruction. If it is an implicit |
1801 | /// operand, it is added to the end of the operand list. If it is an |
1802 | /// explicit operand it is added at the end of the explicit operand list |
1803 | /// (before the first implicit operand). |
1804 | /// |
1805 | /// MF must be the machine function that was used to allocate this |
1806 | /// instruction. |
1807 | /// |
1808 | /// MachineInstrBuilder provides a more convenient interface for creating |
1809 | /// instructions and adding operands. |
1810 | void addOperand(MachineFunction &MF, const MachineOperand &Op); |
1811 | |
1812 | /// Add an operand without providing an MF reference. This only works for |
1813 | /// instructions that are inserted in a basic block. |
1814 | /// |
1815 | /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be |
1816 | /// preferred. |
1817 | void addOperand(const MachineOperand &Op); |
1818 | |
1819 | /// Inserts Ops BEFORE It. Can untie/retie tied operands. |
1820 | void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops); |
1821 | |
1822 | /// Replace the instruction descriptor (thus opcode) of |
1823 | /// the current instruction with a new one. |
1824 | void setDesc(const MCInstrDesc &TID); |
1825 | |
1826 | /// Replace current source information with new such. |
1827 | /// Avoid using this, the constructor argument is preferable. |
1828 | void setDebugLoc(DebugLoc DL) { |
1829 | DbgLoc = std::move(DL); |
1830 | assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor" ); |
1831 | } |
1832 | |
1833 | /// Erase an operand from an instruction, leaving it with one |
1834 | /// fewer operand than it started with. |
1835 | void removeOperand(unsigned OpNo); |
1836 | |
1837 | /// Clear this MachineInstr's memory reference descriptor list. This resets |
1838 | /// the memrefs to their most conservative state. This should be used only |
1839 | /// as a last resort since it greatly pessimizes our knowledge of the memory |
1840 | /// access performed by the instruction. |
1841 | void dropMemRefs(MachineFunction &MF); |
1842 | |
1843 | /// Assign this MachineInstr's memory reference descriptor list. |
1844 | /// |
1845 | /// Unlike other methods, this *will* allocate them into a new array |
1846 | /// associated with the provided `MachineFunction`. |
1847 | void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs); |
1848 | |
1849 | /// Add a MachineMemOperand to the machine instruction. |
1850 | /// This function should be used only occasionally. The setMemRefs function |
1851 | /// is the primary method for setting up a MachineInstr's MemRefs list. |
1852 | void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); |
1853 | |
1854 | /// Clone another MachineInstr's memory reference descriptor list and replace |
1855 | /// ours with it. |
1856 | /// |
1857 | /// Note that `*this` may be the incoming MI! |
1858 | /// |
1859 | /// Prefer this API whenever possible as it can avoid allocations in common |
1860 | /// cases. |
1861 | void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI); |
1862 | |
1863 | /// Clone the merge of multiple MachineInstrs' memory reference descriptors |
1864 | /// list and replace ours with it. |
1865 | /// |
1866 | /// Note that `*this` may be one of the incoming MIs! |
1867 | /// |
1868 | /// Prefer this API whenever possible as it can avoid allocations in common |
1869 | /// cases. |
1870 | void cloneMergedMemRefs(MachineFunction &MF, |
1871 | ArrayRef<const MachineInstr *> MIs); |
1872 | |
1873 | /// Set a symbol that will be emitted just prior to the instruction itself. |
1874 | /// |
1875 | /// Setting this to a null pointer will remove any such symbol. |
1876 | /// |
1877 | /// FIXME: This is not fully implemented yet. |
1878 | void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); |
1879 | |
1880 | /// Set a symbol that will be emitted just after the instruction itself. |
1881 | /// |
1882 | /// Setting this to a null pointer will remove any such symbol. |
1883 | /// |
1884 | /// FIXME: This is not fully implemented yet. |
1885 | void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); |
1886 | |
1887 | /// Clone another MachineInstr's pre- and post- instruction symbols and |
1888 | /// replace ours with it. |
1889 | void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI); |
1890 | |
1891 | /// Set a marker on instructions that denotes where we should create and emit |
1892 | /// heap alloc site labels. This waits until after instruction selection and |
1893 | /// optimizations to create the label, so it should still work if the |
1894 | /// instruction is removed or duplicated. |
1895 | void setHeapAllocMarker(MachineFunction &MF, MDNode *MD); |
1896 | |
1897 | // Set metadata on instructions that say which sections to emit instruction |
1898 | // addresses into. |
1899 | void setPCSections(MachineFunction &MF, MDNode *MD); |
1900 | |
1901 | /// Set the CFI type for the instruction. |
1902 | void setCFIType(MachineFunction &MF, uint32_t Type); |
1903 | |
1904 | /// Return the MIFlags which represent both MachineInstrs. This |
1905 | /// should be used when merging two MachineInstrs into one. This routine does |
1906 | /// not modify the MIFlags of this MachineInstr. |
1907 | uint32_t mergeFlagsWith(const MachineInstr& Other) const; |
1908 | |
1909 | static uint32_t copyFlagsFromInstruction(const Instruction &I); |
1910 | |
1911 | /// Copy all flags to MachineInst MIFlags |
1912 | void copyIRFlags(const Instruction &I); |
1913 | |
1914 | /// Break any tie involving OpIdx. |
1915 | void untieRegOperand(unsigned OpIdx) { |
1916 | MachineOperand &MO = getOperand(i: OpIdx); |
1917 | if (MO.isReg() && MO.isTied()) { |
1918 | getOperand(i: findTiedOperandIdx(OpIdx)).TiedTo = 0; |
1919 | MO.TiedTo = 0; |
1920 | } |
1921 | } |
1922 | |
1923 | /// Add all implicit def and use operands to this instruction. |
1924 | void addImplicitDefUseOperands(MachineFunction &MF); |
1925 | |
1926 | /// Scan instructions immediately following MI and collect any matching |
1927 | /// DBG_VALUEs. |
1928 | void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues); |
1929 | |
1930 | /// Find all DBG_VALUEs that point to the register def in this instruction |
1931 | /// and point them to \p Reg instead. |
1932 | void changeDebugValuesDefReg(Register Reg); |
1933 | |
1934 | /// Sets all register debug operands in this debug value instruction to be |
1935 | /// undef. |
1936 | void setDebugValueUndef() { |
1937 | assert(isDebugValue() && "Must be a debug value instruction." ); |
1938 | for (MachineOperand &MO : debug_operands()) { |
1939 | if (MO.isReg()) { |
1940 | MO.setReg(0); |
1941 | MO.setSubReg(0); |
1942 | } |
1943 | } |
1944 | } |
1945 | |
1946 | std::tuple<Register, Register> getFirst2Regs() const { |
1947 | return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg()); |
1948 | } |
1949 | |
1950 | std::tuple<Register, Register, Register> getFirst3Regs() const { |
1951 | return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(), |
1952 | getOperand(i: 2).getReg()); |
1953 | } |
1954 | |
1955 | std::tuple<Register, Register, Register, Register> getFirst4Regs() const { |
1956 | return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(), |
1957 | getOperand(i: 2).getReg(), getOperand(i: 3).getReg()); |
1958 | } |
1959 | |
1960 | std::tuple<Register, Register, Register, Register, Register> |
1961 | getFirst5Regs() const { |
1962 | return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(), |
1963 | getOperand(i: 2).getReg(), getOperand(i: 3).getReg(), |
1964 | getOperand(i: 4).getReg()); |
1965 | } |
1966 | |
1967 | std::tuple<LLT, LLT> getFirst2LLTs() const; |
1968 | std::tuple<LLT, LLT, LLT> getFirst3LLTs() const; |
1969 | std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const; |
1970 | std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const; |
1971 | |
1972 | std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const; |
1973 | std::tuple<Register, LLT, Register, LLT, Register, LLT> |
1974 | getFirst3RegLLTs() const; |
1975 | std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT> |
1976 | getFirst4RegLLTs() const; |
1977 | std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT, |
1978 | Register, LLT> |
1979 | getFirst5RegLLTs() const; |
1980 | |
1981 | private: |
1982 | /// If this instruction is embedded into a MachineFunction, return the |
1983 | /// MachineRegisterInfo object for the current function, otherwise |
1984 | /// return null. |
1985 | MachineRegisterInfo *getRegInfo(); |
1986 | const MachineRegisterInfo *getRegInfo() const; |
1987 | |
1988 | /// Unlink all of the register operands in this instruction from their |
1989 | /// respective use lists. This requires that the operands already be on their |
1990 | /// use lists. |
1991 | void removeRegOperandsFromUseLists(MachineRegisterInfo&); |
1992 | |
1993 | /// Add all of the register operands in this instruction from their |
1994 | /// respective use lists. This requires that the operands not be on their |
1995 | /// use lists yet. |
1996 | void addRegOperandsToUseLists(MachineRegisterInfo&); |
1997 | |
1998 | /// Slow path for hasProperty when we're dealing with a bundle. |
1999 | bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const; |
2000 | |
2001 | /// Implements the logic of getRegClassConstraintEffectForVReg for the |
2002 | /// this MI and the given operand index \p OpIdx. |
2003 | /// If the related operand does not constrained Reg, this returns CurRC. |
2004 | const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( |
2005 | unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, |
2006 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; |
2007 | |
2008 | /// Stores extra instruction information inline or allocates as ExtraInfo |
2009 | /// based on the number of pointers. |
2010 | void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs, |
2011 | MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, |
2012 | MDNode *HeapAllocMarker, MDNode *PCSections, |
2013 | uint32_t CFIType); |
2014 | }; |
2015 | |
2016 | /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the |
2017 | /// instruction rather than by pointer value. |
2018 | /// The hashing and equality testing functions ignore definitions so this is |
2019 | /// useful for CSE, etc. |
2020 | struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { |
2021 | static inline MachineInstr *getEmptyKey() { |
2022 | return nullptr; |
2023 | } |
2024 | |
2025 | static inline MachineInstr *getTombstoneKey() { |
2026 | return reinterpret_cast<MachineInstr*>(-1); |
2027 | } |
2028 | |
2029 | static unsigned getHashValue(const MachineInstr* const &MI); |
2030 | |
2031 | static bool isEqual(const MachineInstr* const &LHS, |
2032 | const MachineInstr* const &RHS) { |
2033 | if (RHS == getEmptyKey() || RHS == getTombstoneKey() || |
2034 | LHS == getEmptyKey() || LHS == getTombstoneKey()) |
2035 | return LHS == RHS; |
2036 | return LHS->isIdenticalTo(Other: *RHS, Check: MachineInstr::IgnoreVRegDefs); |
2037 | } |
2038 | }; |
2039 | |
2040 | //===----------------------------------------------------------------------===// |
2041 | // Debugging Support |
2042 | |
2043 | inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { |
2044 | MI.print(OS); |
2045 | return OS; |
2046 | } |
2047 | |
2048 | } // end namespace llvm |
2049 | |
2050 | #endif // LLVM_CODEGEN_MACHINEINSTR_H |
2051 | |