1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file exposes a function named BuildMI, which is useful for dramatically
10// simplifying how MachineInstr's are created. It allows use of code like this:
11//
12// MIMetadata MIMD(MI); // Propagates DebugLoc and other metadata
13// M = BuildMI(MBB, MI, MIMD, TII.get(X86::ADD8rr), Dst)
14// .addReg(argVal1)
15// .addReg(argVal2);
16//
17//===----------------------------------------------------------------------===//
18
19#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
21
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/CodeGen/GlobalISel/Utils.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBundle.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/IR/InstrTypes.h"
31#include "llvm/IR/Intrinsics.h"
32#include "llvm/Support/ErrorHandling.h"
33#include <cassert>
34#include <cstdint>
35
36namespace llvm {
37
38class MCInstrDesc;
39class MDNode;
40
41namespace RegState {
42
43enum {
44 /// Register definition.
45 Define = 0x2,
46 /// Not emitted register (e.g. carry, or temporary result).
47 Implicit = 0x4,
48 /// The last use of a register.
49 Kill = 0x8,
50 /// Unused definition.
51 Dead = 0x10,
52 /// Value of the register doesn't matter.
53 Undef = 0x20,
54 /// Register definition happens before uses.
55 EarlyClobber = 0x40,
56 /// Register 'use' is for debugging purpose.
57 Debug = 0x80,
58 /// Register reads a value that is defined inside the same instruction or
59 /// bundle.
60 InternalRead = 0x100,
61 /// Register that may be renamed.
62 Renamable = 0x200,
63 DefineNoRead = Define | Undef,
64 ImplicitDefine = Implicit | Define,
65 ImplicitKill = Implicit | Kill
66};
67
68} // end namespace RegState
69
70class MachineInstrBuilder {
71 MachineFunction *MF = nullptr;
72 MachineInstr *MI = nullptr;
73
74public:
75 MachineInstrBuilder() = default;
76
77 /// Create a MachineInstrBuilder for manipulating an existing instruction.
78 /// F must be the machine function that was used to allocate I.
79 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
80 MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
81 : MF(&F), MI(&*I) {}
82
83 /// Allow automatic conversion to the machine instruction we are working on.
84 operator MachineInstr*() const { return MI; }
85 MachineInstr *operator->() const { return MI; }
86 operator MachineBasicBlock::iterator() const { return MI; }
87
88 /// If conversion operators fail, use this method to get the MachineInstr
89 /// explicitly.
90 MachineInstr *getInstr() const { return MI; }
91
92 /// Get the register for the operand index.
93 /// The operand at the index should be a register (asserted by
94 /// MachineOperand).
95 Register getReg(unsigned Idx) const { return MI->getOperand(i: Idx).getReg(); }
96
97 /// Add a new virtual register operand.
98 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
99 unsigned SubReg = 0) const {
100 assert((flags & 0x1) == 0 &&
101 "Passing in 'true' to addReg is forbidden! Use enums instead.");
102 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateReg(Reg: RegNo,
103 isDef: flags & RegState::Define,
104 isImp: flags & RegState::Implicit,
105 isKill: flags & RegState::Kill,
106 isDead: flags & RegState::Dead,
107 isUndef: flags & RegState::Undef,
108 isEarlyClobber: flags & RegState::EarlyClobber,
109 SubReg,
110 isDebug: flags & RegState::Debug,
111 isInternalRead: flags & RegState::InternalRead,
112 isRenamable: flags & RegState::Renamable));
113 return *this;
114 }
115
116 /// Add a virtual register definition operand.
117 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
118 unsigned SubReg = 0) const {
119 return addReg(RegNo, flags: Flags | RegState::Define, SubReg);
120 }
121
122 /// Add a virtual register use operand. It is an error for Flags to contain
123 /// `RegState::Define` when calling this function.
124 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
125 unsigned SubReg = 0) const {
126 assert(!(Flags & RegState::Define) &&
127 "Misleading addUse defines register, use addReg instead.");
128 return addReg(RegNo, flags: Flags, SubReg);
129 }
130
131 /// Add a new immediate operand.
132 const MachineInstrBuilder &addImm(int64_t Val) const {
133 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateImm(Val));
134 return *this;
135 }
136
137 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
138 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCImm(CI: Val));
139 return *this;
140 }
141
142 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
143 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateFPImm(CFP: Val));
144 return *this;
145 }
146
147 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
148 unsigned TargetFlags = 0) const {
149 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMBB(MBB, TargetFlags));
150 return *this;
151 }
152
153 const MachineInstrBuilder &addFrameIndex(int Idx) const {
154 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateFI(Idx));
155 return *this;
156 }
157
158 const MachineInstrBuilder &
159 addConstantPoolIndex(unsigned Idx, int Offset = 0,
160 unsigned TargetFlags = 0) const {
161 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
162 return *this;
163 }
164
165 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
166 unsigned TargetFlags = 0) const {
167 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateTargetIndex(Idx, Offset,
168 TargetFlags));
169 return *this;
170 }
171
172 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
173 unsigned TargetFlags = 0) const {
174 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateJTI(Idx, TargetFlags));
175 return *this;
176 }
177
178 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
179 int64_t Offset = 0,
180 unsigned TargetFlags = 0) const {
181 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateGA(GV, Offset, TargetFlags));
182 return *this;
183 }
184
185 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
186 unsigned TargetFlags = 0) const {
187 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateES(SymName: FnName, TargetFlags));
188 return *this;
189 }
190
191 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
192 int64_t Offset = 0,
193 unsigned TargetFlags = 0) const {
194 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateBA(BA, Offset, TargetFlags));
195 return *this;
196 }
197
198 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
199 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateRegMask(Mask));
200 return *this;
201 }
202
203 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
204 MI->addMemOperand(MF&: *MF, MO: MMO);
205 return *this;
206 }
207
208 const MachineInstrBuilder &
209 setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const {
210 MI->setMemRefs(MF&: *MF, MemRefs: MMOs);
211 return *this;
212 }
213
214 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
215 MI->cloneMemRefs(MF&: *MF, MI: OtherMI);
216 return *this;
217 }
218
219 const MachineInstrBuilder &
220 cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const {
221 MI->cloneMergedMemRefs(MF&: *MF, MIs: OtherMIs);
222 return *this;
223 }
224
225 const MachineInstrBuilder &add(const MachineOperand &MO) const {
226 MI->addOperand(MF&: *MF, Op: MO);
227 return *this;
228 }
229
230 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
231 for (const MachineOperand &MO : MOs) {
232 MI->addOperand(MF&: *MF, Op: MO);
233 }
234 return *this;
235 }
236
237 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
238 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMetadata(Meta: MD));
239 assert((MI->isDebugValueLike() ? static_cast<bool>(MI->getDebugVariable())
240 : true) &&
241 "first MDNode argument of a DBG_VALUE not a variable");
242 assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
243 : true) &&
244 "first MDNode argument of a DBG_LABEL not a label");
245 return *this;
246 }
247
248 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
249 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCFIIndex(CFIIndex));
250 return *this;
251 }
252
253 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
254 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateIntrinsicID(ID));
255 return *this;
256 }
257
258 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
259 MI->addOperand(MF&: *MF, Op: MachineOperand::CreatePredicate(Pred));
260 return *this;
261 }
262
263 const MachineInstrBuilder &addShuffleMask(ArrayRef<int> Val) const {
264 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateShuffleMask(Mask: Val));
265 return *this;
266 }
267
268 const MachineInstrBuilder &addSym(MCSymbol *Sym,
269 unsigned char TargetFlags = 0) const {
270 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMCSymbol(Sym, TargetFlags));
271 return *this;
272 }
273
274 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
275 MI->setFlags(Flags);
276 return *this;
277 }
278
279 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
280 MI->setFlag(Flag);
281 return *this;
282 }
283
284 const MachineInstrBuilder &setOperandDead(unsigned OpIdx) const {
285 MI->getOperand(i: OpIdx).setIsDead();
286 return *this;
287 }
288
289 // Add a displacement from an existing MachineOperand with an added offset.
290 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
291 unsigned char TargetFlags = 0) const {
292 // If caller specifies new TargetFlags then use it, otherwise the
293 // default behavior is to copy the target flags from the existing
294 // MachineOperand. This means if the caller wants to clear the
295 // target flags it needs to do so explicitly.
296 if (0 == TargetFlags)
297 TargetFlags = Disp.getTargetFlags();
298
299 switch (Disp.getType()) {
300 default:
301 llvm_unreachable("Unhandled operand type in addDisp()");
302 case MachineOperand::MO_Immediate:
303 return addImm(Val: Disp.getImm() + off);
304 case MachineOperand::MO_ConstantPoolIndex:
305 return addConstantPoolIndex(Idx: Disp.getIndex(), Offset: Disp.getOffset() + off,
306 TargetFlags);
307 case MachineOperand::MO_GlobalAddress:
308 return addGlobalAddress(GV: Disp.getGlobal(), Offset: Disp.getOffset() + off,
309 TargetFlags);
310 case MachineOperand::MO_BlockAddress:
311 return addBlockAddress(BA: Disp.getBlockAddress(), Offset: Disp.getOffset() + off,
312 TargetFlags);
313 case MachineOperand::MO_JumpTableIndex:
314 assert(off == 0 && "cannot create offset into jump tables");
315 return addJumpTableIndex(Idx: Disp.getIndex(), TargetFlags);
316 }
317 }
318
319 const MachineInstrBuilder &setPCSections(MDNode *MD) const {
320 if (MD)
321 MI->setPCSections(MF&: *MF, MD);
322 return *this;
323 }
324
325 /// Copy all the implicit operands from OtherMI onto this one.
326 const MachineInstrBuilder &
327 copyImplicitOps(const MachineInstr &OtherMI) const {
328 MI->copyImplicitOps(MF&: *MF, MI: OtherMI);
329 return *this;
330 }
331
332 bool constrainAllUses(const TargetInstrInfo &TII,
333 const TargetRegisterInfo &TRI,
334 const RegisterBankInfo &RBI) const {
335 return constrainSelectedInstRegOperands(I&: *MI, TII, TRI, RBI);
336 }
337};
338
339/// Set of metadata that should be preserved when using BuildMI(). This provides
340/// a more convenient way of preserving DebugLoc and PCSections.
341class MIMetadata {
342public:
343 MIMetadata() = default;
344 MIMetadata(DebugLoc DL, MDNode *PCSections = nullptr)
345 : DL(std::move(DL)), PCSections(PCSections) {}
346 MIMetadata(const DILocation *DI, MDNode *PCSections = nullptr)
347 : DL(DI), PCSections(PCSections) {}
348 explicit MIMetadata(const Instruction &From)
349 : DL(From.getDebugLoc()),
350 PCSections(From.getMetadata(KindID: LLVMContext::MD_pcsections)) {}
351 explicit MIMetadata(const MachineInstr &From)
352 : DL(From.getDebugLoc()), PCSections(From.getPCSections()) {}
353
354 const DebugLoc &getDL() const { return DL; }
355 MDNode *getPCSections() const { return PCSections; }
356
357private:
358 DebugLoc DL;
359 MDNode *PCSections = nullptr;
360};
361
362/// Builder interface. Specify how to create the initial instruction itself.
363inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD,
364 const MCInstrDesc &MCID) {
365 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL: MIMD.getDL()))
366 .setPCSections(MIMD.getPCSections());
367}
368
369/// This version of the builder sets up the first operand as a
370/// destination virtual register.
371inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD,
372 const MCInstrDesc &MCID, Register DestReg) {
373 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL: MIMD.getDL()))
374 .setPCSections(MIMD.getPCSections())
375 .addReg(RegNo: DestReg, flags: RegState::Define);
376}
377
378/// This version of the builder inserts the newly-built instruction before
379/// the given position in the given MachineBasicBlock, and sets up the first
380/// operand as a destination virtual register.
381inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
382 MachineBasicBlock::iterator I,
383 const MIMetadata &MIMD,
384 const MCInstrDesc &MCID, Register DestReg) {
385 MachineFunction &MF = *BB.getParent();
386 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
387 BB.insert(I, MI);
388 return MachineInstrBuilder(MF, MI)
389 .setPCSections(MIMD.getPCSections())
390 .addReg(RegNo: DestReg, flags: RegState::Define);
391}
392
393/// This version of the builder inserts the newly-built instruction before
394/// the given position in the given MachineBasicBlock, and sets up the first
395/// operand as a destination virtual register.
396///
397/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
398/// added to the same bundle.
399inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
400 MachineBasicBlock::instr_iterator I,
401 const MIMetadata &MIMD,
402 const MCInstrDesc &MCID, Register DestReg) {
403 MachineFunction &MF = *BB.getParent();
404 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
405 BB.insert(I, M: MI);
406 return MachineInstrBuilder(MF, MI)
407 .setPCSections(MIMD.getPCSections())
408 .addReg(RegNo: DestReg, flags: RegState::Define);
409}
410
411inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
412 const MIMetadata &MIMD,
413 const MCInstrDesc &MCID, Register DestReg) {
414 // Calling the overload for instr_iterator is always correct. However, the
415 // definition is not available in headers, so inline the check.
416 if (I.isInsideBundle())
417 return BuildMI(BB, I: MachineBasicBlock::instr_iterator(I), MIMD, MCID,
418 DestReg);
419 return BuildMI(BB, I: MachineBasicBlock::iterator(I), MIMD, MCID, DestReg);
420}
421
422inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
423 const MIMetadata &MIMD,
424 const MCInstrDesc &MCID, Register DestReg) {
425 return BuildMI(BB, I&: *I, MIMD, MCID, DestReg);
426}
427
428/// This version of the builder inserts the newly-built instruction before the
429/// given position in the given MachineBasicBlock, and does NOT take a
430/// destination register.
431inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
432 MachineBasicBlock::iterator I,
433 const MIMetadata &MIMD,
434 const MCInstrDesc &MCID) {
435 MachineFunction &MF = *BB.getParent();
436 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
437 BB.insert(I, MI);
438 return MachineInstrBuilder(MF, MI).setPCSections(MIMD.getPCSections());
439}
440
441inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
442 MachineBasicBlock::instr_iterator I,
443 const MIMetadata &MIMD,
444 const MCInstrDesc &MCID) {
445 MachineFunction &MF = *BB.getParent();
446 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
447 BB.insert(I, M: MI);
448 return MachineInstrBuilder(MF, MI).setPCSections(MIMD.getPCSections());
449}
450
451inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
452 const MIMetadata &MIMD,
453 const MCInstrDesc &MCID) {
454 // Calling the overload for instr_iterator is always correct. However, the
455 // definition is not available in headers, so inline the check.
456 if (I.isInsideBundle())
457 return BuildMI(BB, I: MachineBasicBlock::instr_iterator(I), MIMD, MCID);
458 return BuildMI(BB, I: MachineBasicBlock::iterator(I), MIMD, MCID);
459}
460
461inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
462 const MIMetadata &MIMD,
463 const MCInstrDesc &MCID) {
464 return BuildMI(BB, I&: *I, MIMD, MCID);
465}
466
467/// This version of the builder inserts the newly-built instruction at the end
468/// of the given MachineBasicBlock, and does NOT take a destination register.
469inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
470 const MIMetadata &MIMD,
471 const MCInstrDesc &MCID) {
472 return BuildMI(BB&: *BB, I: BB->end(), MIMD, MCID);
473}
474
475/// This version of the builder inserts the newly-built instruction at the
476/// end of the given MachineBasicBlock, and sets up the first operand as a
477/// destination virtual register.
478inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
479 const MIMetadata &MIMD,
480 const MCInstrDesc &MCID, Register DestReg) {
481 return BuildMI(BB&: *BB, I: BB->end(), MIMD, MCID, DestReg);
482}
483
484/// This version of the builder builds a DBG_VALUE intrinsic
485/// for either a value in a register or a register-indirect
486/// address. The convention is that a DBG_VALUE is indirect iff the
487/// second operand is an immediate.
488MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
489 const MCInstrDesc &MCID, bool IsIndirect,
490 Register Reg, const MDNode *Variable,
491 const MDNode *Expr);
492
493/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
494/// for a MachineOperand.
495MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
496 const MCInstrDesc &MCID, bool IsIndirect,
497 ArrayRef<MachineOperand> MOs,
498 const MDNode *Variable, const MDNode *Expr);
499
500/// This version of the builder builds a DBG_VALUE intrinsic
501/// for either a value in a register or a register-indirect
502/// address and inserts it at position I.
503MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
504 MachineBasicBlock::iterator I, const DebugLoc &DL,
505 const MCInstrDesc &MCID, bool IsIndirect,
506 Register Reg, const MDNode *Variable,
507 const MDNode *Expr);
508
509/// This version of the builder builds a DBG_VALUE, DBG_INSTR_REF, or
510/// DBG_VALUE_LIST intrinsic for a machine operand and inserts it at position I.
511MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
512 MachineBasicBlock::iterator I, const DebugLoc &DL,
513 const MCInstrDesc &MCID, bool IsIndirect,
514 ArrayRef<MachineOperand> MOs,
515 const MDNode *Variable, const MDNode *Expr);
516
517/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
518MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
519 MachineBasicBlock::iterator I,
520 const MachineInstr &Orig, int FrameIndex,
521 Register SpillReg);
522MachineInstr *
523buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I,
524 const MachineInstr &Orig, int FrameIndex,
525 SmallVectorImpl<const MachineOperand *> &SpilledOperands);
526
527/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
528/// modifying an instruction in place while iterating over a basic block.
529void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);
530
531inline unsigned getDefRegState(bool B) {
532 return B ? RegState::Define : 0;
533}
534inline unsigned getImplRegState(bool B) {
535 return B ? RegState::Implicit : 0;
536}
537inline unsigned getKillRegState(bool B) {
538 return B ? RegState::Kill : 0;
539}
540inline unsigned getDeadRegState(bool B) {
541 return B ? RegState::Dead : 0;
542}
543inline unsigned getUndefRegState(bool B) {
544 return B ? RegState::Undef : 0;
545}
546inline unsigned getInternalReadRegState(bool B) {
547 return B ? RegState::InternalRead : 0;
548}
549inline unsigned getDebugRegState(bool B) {
550 return B ? RegState::Debug : 0;
551}
552inline unsigned getRenamableRegState(bool B) {
553 return B ? RegState::Renamable : 0;
554}
555
556/// Get all register state flags from machine operand \p RegOp.
557inline unsigned getRegState(const MachineOperand &RegOp) {
558 assert(RegOp.isReg() && "Not a register operand");
559 return getDefRegState(B: RegOp.isDef()) | getImplRegState(B: RegOp.isImplicit()) |
560 getKillRegState(B: RegOp.isKill()) | getDeadRegState(B: RegOp.isDead()) |
561 getUndefRegState(B: RegOp.isUndef()) |
562 getInternalReadRegState(B: RegOp.isInternalRead()) |
563 getDebugRegState(B: RegOp.isDebug()) |
564 getRenamableRegState(B: RegOp.getReg().isPhysical() &&
565 RegOp.isRenamable());
566}
567
568/// Helper class for constructing bundles of MachineInstrs.
569///
570/// MIBundleBuilder can create a bundle from scratch by inserting new
571/// MachineInstrs one at a time, or it can create a bundle from a sequence of
572/// existing MachineInstrs in a basic block.
573class MIBundleBuilder {
574 MachineBasicBlock &MBB;
575 MachineBasicBlock::instr_iterator Begin;
576 MachineBasicBlock::instr_iterator End;
577
578public:
579 /// Create an MIBundleBuilder that inserts instructions into a new bundle in
580 /// BB above the bundle or instruction at Pos.
581 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
582 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
583
584 /// Create a bundle from the sequence of instructions between B and E.
585 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
586 MachineBasicBlock::iterator E)
587 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
588 assert(B != E && "No instructions to bundle");
589 ++B;
590 while (B != E) {
591 MachineInstr &MI = *B;
592 ++B;
593 MI.bundleWithPred();
594 }
595 }
596
597 /// Create an MIBundleBuilder representing an existing instruction or bundle
598 /// that has MI as its head.
599 explicit MIBundleBuilder(MachineInstr *MI)
600 : MBB(*MI->getParent()), Begin(MI),
601 End(getBundleEnd(I: MI->getIterator())) {}
602
603 /// Return a reference to the basic block containing this bundle.
604 MachineBasicBlock &getMBB() const { return MBB; }
605
606 /// Return true if no instructions have been inserted in this bundle yet.
607 /// Empty bundles aren't representable in a MachineBasicBlock.
608 bool empty() const { return Begin == End; }
609
610 /// Return an iterator to the first bundled instruction.
611 MachineBasicBlock::instr_iterator begin() const { return Begin; }
612
613 /// Return an iterator beyond the last bundled instruction.
614 MachineBasicBlock::instr_iterator end() const { return End; }
615
616 /// Insert MI into this bundle before I which must point to an instruction in
617 /// the bundle, or end().
618 MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
619 MachineInstr *MI) {
620 MBB.insert(I, M: MI);
621 if (I == Begin) {
622 if (!empty())
623 MI->bundleWithSucc();
624 Begin = MI->getIterator();
625 return *this;
626 }
627 if (I == End) {
628 MI->bundleWithPred();
629 return *this;
630 }
631 // MI was inserted in the middle of the bundle, so its neighbors' flags are
632 // already fine. Update MI's bundle flags manually.
633 MI->setFlag(MachineInstr::BundledPred);
634 MI->setFlag(MachineInstr::BundledSucc);
635 return *this;
636 }
637
638 /// Insert MI into MBB by prepending it to the instructions in the bundle.
639 /// MI will become the first instruction in the bundle.
640 MIBundleBuilder &prepend(MachineInstr *MI) {
641 return insert(I: begin(), MI);
642 }
643
644 /// Insert MI into MBB by appending it to the instructions in the bundle.
645 /// MI will become the last instruction in the bundle.
646 MIBundleBuilder &append(MachineInstr *MI) {
647 return insert(I: end(), MI);
648 }
649};
650
651} // end namespace llvm
652
653#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
654

source code of llvm/include/llvm/CodeGen/MachineInstrBuilder.h