1//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MachineRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/IndexedMap.h"
20#include "llvm/ADT/PointerUnion.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/StringSet.h"
23#include "llvm/ADT/iterator_range.h"
24#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
25#include "llvm/CodeGen/LowLevelType.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBundle.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/TargetRegisterInfo.h"
31#include "llvm/CodeGen/TargetSubtargetInfo.h"
32#include "llvm/MC/LaneBitmask.h"
33#include <cassert>
34#include <cstddef>
35#include <cstdint>
36#include <iterator>
37#include <memory>
38#include <utility>
39#include <vector>
40
41namespace llvm {
42
43class PSetIterator;
44
45/// Convenient type to represent either a register class or a register bank.
46using RegClassOrRegBank =
47 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
48
49/// MachineRegisterInfo - Keep track of information for virtual and physical
50/// registers, including vreg register classes, use/def chains for registers,
51/// etc.
52class MachineRegisterInfo {
53public:
54 class Delegate {
55 virtual void anchor();
56
57 public:
58 virtual ~Delegate() = default;
59
60 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
61 };
62
63private:
64 MachineFunction *MF;
65 Delegate *TheDelegate = nullptr;
66
67 /// True if subregister liveness is tracked.
68 const bool TracksSubRegLiveness;
69
70 /// VRegInfo - Information we keep for each virtual register.
71 ///
72 /// Each element in this list contains the register class of the vreg and the
73 /// start of the use/def list for the register.
74 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
75 VirtReg2IndexFunctor>
76 VRegInfo;
77
78 /// Map for recovering vreg name from vreg number.
79 /// This map is used by the MIR Printer.
80 IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
81
82 /// StringSet that is used to unique vreg names.
83 StringSet<> VRegNames;
84
85 /// The flag is true upon \p UpdatedCSRs initialization
86 /// and false otherwise.
87 bool IsUpdatedCSRsInitialized;
88
89 /// Contains the updated callee saved register list.
90 /// As opposed to the static list defined in register info,
91 /// all registers that were disabled are removed from the list.
92 SmallVector<MCPhysReg, 16> UpdatedCSRs;
93
94 /// RegAllocHints - This vector records register allocation hints for
95 /// virtual registers. For each virtual register, it keeps a pair of hint
96 /// type and hints vector making up the allocation hints. Only the first
97 /// hint may be target specific, and in that case this is reflected by the
98 /// first member of the pair being non-zero. If the hinted register is
99 /// virtual, it means the allocator should prefer the physical register
100 /// allocated to it if any.
101 IndexedMap<std::pair<Register, SmallVector<Register, 4>>,
102 VirtReg2IndexFunctor> RegAllocHints;
103
104 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
105 /// physical registers.
106 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
107
108 /// getRegUseDefListHead - Return the head pointer for the register use/def
109 /// list for the specified virtual or physical register.
110 MachineOperand *&getRegUseDefListHead(Register RegNo) {
111 if (RegNo.isVirtual())
112 return VRegInfo[RegNo.id()].second;
113 return PhysRegUseDefLists[RegNo.id()];
114 }
115
116 MachineOperand *getRegUseDefListHead(Register RegNo) const {
117 if (RegNo.isVirtual())
118 return VRegInfo[RegNo.id()].second;
119 return PhysRegUseDefLists[RegNo.id()];
120 }
121
122 /// Get the next element in the use-def chain.
123 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
124 assert(MO && MO->isReg() && "This is not a register operand!");
125 return MO->Contents.Reg.Next;
126 }
127
128 /// UsedPhysRegMask - Additional used physregs including aliases.
129 /// This bit vector represents all the registers clobbered by function calls.
130 BitVector UsedPhysRegMask;
131
132 /// ReservedRegs - This is a bit vector of reserved registers. The target
133 /// may change its mind about which registers should be reserved. This
134 /// vector is the frozen set of reserved registers when register allocation
135 /// started.
136 BitVector ReservedRegs;
137
138 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
139 /// Map generic virtual registers to their low-level type.
140 VRegToTypeMap VRegToType;
141
142 /// Keep track of the physical registers that are live in to the function.
143 /// Live in values are typically arguments in registers. LiveIn values are
144 /// allowed to have virtual registers associated with them, stored in the
145 /// second element.
146 std::vector<std::pair<MCRegister, Register>> LiveIns;
147
148public:
149 explicit MachineRegisterInfo(MachineFunction *MF);
150 MachineRegisterInfo(const MachineRegisterInfo &) = delete;
151 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
152
153 const TargetRegisterInfo *getTargetRegisterInfo() const {
154 return MF->getSubtarget().getRegisterInfo();
155 }
156
157 void resetDelegate(Delegate *delegate) {
158 // Ensure another delegate does not take over unless the current
159 // delegate first unattaches itself. If we ever need to multicast
160 // notifications, we will need to change to using a list.
161 assert(TheDelegate == delegate &&
162 "Only the current delegate can perform reset!");
163 TheDelegate = nullptr;
164 }
165
166 void setDelegate(Delegate *delegate) {
167 assert(delegate && !TheDelegate &&
168 "Attempted to set delegate to null, or to change it without "
169 "first resetting it!");
170
171 TheDelegate = delegate;
172 }
173
174 //===--------------------------------------------------------------------===//
175 // Function State
176 //===--------------------------------------------------------------------===//
177
178 // isSSA - Returns true when the machine function is in SSA form. Early
179 // passes require the machine function to be in SSA form where every virtual
180 // register has a single defining instruction.
181 //
182 // The TwoAddressInstructionPass and PHIElimination passes take the machine
183 // function out of SSA form when they introduce multiple defs per virtual
184 // register.
185 bool isSSA() const {
186 return MF->getProperties().hasProperty(
187 MachineFunctionProperties::Property::IsSSA);
188 }
189
190 // leaveSSA - Indicates that the machine function is no longer in SSA form.
191 void leaveSSA() {
192 MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
193 }
194
195 /// tracksLiveness - Returns true when tracking register liveness accurately.
196 /// (see MachineFUnctionProperties::Property description for details)
197 bool tracksLiveness() const {
198 return MF->getProperties().hasProperty(
199 MachineFunctionProperties::Property::TracksLiveness);
200 }
201
202 /// invalidateLiveness - Indicates that register liveness is no longer being
203 /// tracked accurately.
204 ///
205 /// This should be called by late passes that invalidate the liveness
206 /// information.
207 void invalidateLiveness() {
208 MF->getProperties().reset(
209 MachineFunctionProperties::Property::TracksLiveness);
210 }
211
212 /// Returns true if liveness for register class @p RC should be tracked at
213 /// the subregister level.
214 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
215 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
216 }
217 bool shouldTrackSubRegLiveness(Register VReg) const {
218 assert(VReg.isVirtual() && "Must pass a VReg");
219 return shouldTrackSubRegLiveness(*getRegClass(VReg));
220 }
221 bool subRegLivenessEnabled() const {
222 return TracksSubRegLiveness;
223 }
224
225 //===--------------------------------------------------------------------===//
226 // Register Info
227 //===--------------------------------------------------------------------===//
228
229 /// Returns true if the updated CSR list was initialized and false otherwise.
230 bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
231
232 /// Disables the register from the list of CSRs.
233 /// I.e. the register will not appear as part of the CSR mask.
234 /// \see UpdatedCalleeSavedRegs.
235 void disableCalleeSavedRegister(MCRegister Reg);
236
237 /// Returns list of callee saved registers.
238 /// The function returns the updated CSR list (after taking into account
239 /// registers that are disabled from the CSR list).
240 const MCPhysReg *getCalleeSavedRegs() const;
241
242 /// Sets the updated Callee Saved Registers list.
243 /// Notice that it will override ant previously disabled/saved CSRs.
244 void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
245
246 // Strictly for use by MachineInstr.cpp.
247 void addRegOperandToUseList(MachineOperand *MO);
248
249 // Strictly for use by MachineInstr.cpp.
250 void removeRegOperandFromUseList(MachineOperand *MO);
251
252 // Strictly for use by MachineInstr.cpp.
253 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
254
255 /// Verify the sanity of the use list for Reg.
256 void verifyUseList(Register Reg) const;
257
258 /// Verify the use list of all registers.
259 void verifyUseLists() const;
260
261 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
262 /// and uses of a register within the MachineFunction that corresponds to this
263 /// MachineRegisterInfo object.
264 template<bool Uses, bool Defs, bool SkipDebug,
265 bool ByOperand, bool ByInstr, bool ByBundle>
266 class defusechain_iterator;
267 template<bool Uses, bool Defs, bool SkipDebug,
268 bool ByOperand, bool ByInstr, bool ByBundle>
269 class defusechain_instr_iterator;
270
271 // Make it a friend so it can access getNextOperandForReg().
272 template<bool, bool, bool, bool, bool, bool>
273 friend class defusechain_iterator;
274 template<bool, bool, bool, bool, bool, bool>
275 friend class defusechain_instr_iterator;
276
277 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
278 /// register.
279 using reg_iterator =
280 defusechain_iterator<true, true, false, true, false, false>;
281 reg_iterator reg_begin(Register RegNo) const {
282 return reg_iterator(getRegUseDefListHead(RegNo));
283 }
284 static reg_iterator reg_end() { return reg_iterator(nullptr); }
285
286 inline iterator_range<reg_iterator> reg_operands(Register Reg) const {
287 return make_range(reg_begin(Reg), reg_end());
288 }
289
290 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
291 /// of the specified register, stepping by MachineInstr.
292 using reg_instr_iterator =
293 defusechain_instr_iterator<true, true, false, false, true, false>;
294 reg_instr_iterator reg_instr_begin(Register RegNo) const {
295 return reg_instr_iterator(getRegUseDefListHead(RegNo));
296 }
297 static reg_instr_iterator reg_instr_end() {
298 return reg_instr_iterator(nullptr);
299 }
300
301 inline iterator_range<reg_instr_iterator>
302 reg_instructions(Register Reg) const {
303 return make_range(reg_instr_begin(Reg), reg_instr_end());
304 }
305
306 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
307 /// of the specified register, stepping by bundle.
308 using reg_bundle_iterator =
309 defusechain_instr_iterator<true, true, false, false, false, true>;
310 reg_bundle_iterator reg_bundle_begin(Register RegNo) const {
311 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
312 }
313 static reg_bundle_iterator reg_bundle_end() {
314 return reg_bundle_iterator(nullptr);
315 }
316
317 inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const {
318 return make_range(reg_bundle_begin(Reg), reg_bundle_end());
319 }
320
321 /// reg_empty - Return true if there are no instructions using or defining the
322 /// specified register (it may be live-in).
323 bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
324
325 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
326 /// of the specified register, skipping those marked as Debug.
327 using reg_nodbg_iterator =
328 defusechain_iterator<true, true, true, true, false, false>;
329 reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const {
330 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
331 }
332 static reg_nodbg_iterator reg_nodbg_end() {
333 return reg_nodbg_iterator(nullptr);
334 }
335
336 inline iterator_range<reg_nodbg_iterator>
337 reg_nodbg_operands(Register Reg) const {
338 return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
339 }
340
341 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
342 /// all defs and uses of the specified register, stepping by MachineInstr,
343 /// skipping those marked as Debug.
344 using reg_instr_nodbg_iterator =
345 defusechain_instr_iterator<true, true, true, false, true, false>;
346 reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const {
347 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
348 }
349 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
350 return reg_instr_nodbg_iterator(nullptr);
351 }
352
353 inline iterator_range<reg_instr_nodbg_iterator>
354 reg_nodbg_instructions(Register Reg) const {
355 return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
356 }
357
358 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
359 /// all defs and uses of the specified register, stepping by bundle,
360 /// skipping those marked as Debug.
361 using reg_bundle_nodbg_iterator =
362 defusechain_instr_iterator<true, true, true, false, false, true>;
363 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const {
364 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
365 }
366 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
367 return reg_bundle_nodbg_iterator(nullptr);
368 }
369
370 inline iterator_range<reg_bundle_nodbg_iterator>
371 reg_nodbg_bundles(Register Reg) const {
372 return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
373 }
374
375 /// reg_nodbg_empty - Return true if the only instructions using or defining
376 /// Reg are Debug instructions.
377 bool reg_nodbg_empty(Register RegNo) const {
378 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
379 }
380
381 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
382 using def_iterator =
383 defusechain_iterator<false, true, false, true, false, false>;
384 def_iterator def_begin(Register RegNo) const {
385 return def_iterator(getRegUseDefListHead(RegNo));
386 }
387 static def_iterator def_end() { return def_iterator(nullptr); }
388
389 inline iterator_range<def_iterator> def_operands(Register Reg) const {
390 return make_range(def_begin(Reg), def_end());
391 }
392
393 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
394 /// specified register, stepping by MachineInst.
395 using def_instr_iterator =
396 defusechain_instr_iterator<false, true, false, false, true, false>;
397 def_instr_iterator def_instr_begin(Register RegNo) const {
398 return def_instr_iterator(getRegUseDefListHead(RegNo));
399 }
400 static def_instr_iterator def_instr_end() {
401 return def_instr_iterator(nullptr);
402 }
403
404 inline iterator_range<def_instr_iterator>
405 def_instructions(Register Reg) const {
406 return make_range(def_instr_begin(Reg), def_instr_end());
407 }
408
409 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
410 /// specified register, stepping by bundle.
411 using def_bundle_iterator =
412 defusechain_instr_iterator<false, true, false, false, false, true>;
413 def_bundle_iterator def_bundle_begin(Register RegNo) const {
414 return def_bundle_iterator(getRegUseDefListHead(RegNo));
415 }
416 static def_bundle_iterator def_bundle_end() {
417 return def_bundle_iterator(nullptr);
418 }
419
420 inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const {
421 return make_range(def_bundle_begin(Reg), def_bundle_end());
422 }
423
424 /// def_empty - Return true if there are no instructions defining the
425 /// specified register (it may be live-in).
426 bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
427
428 StringRef getVRegName(Register Reg) const {
429 return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
430 }
431
432 void insertVRegByName(StringRef Name, Register Reg) {
433 assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
434 "Named VRegs Must be Unique.");
435 if (!Name.empty()) {
436 VRegNames.insert(Name);
437 VReg2Name.grow(Reg);
438 VReg2Name[Reg] = Name.str();
439 }
440 }
441
442 /// Return true if there is exactly one operand defining the specified
443 /// register.
444 bool hasOneDef(Register RegNo) const {
445 return hasSingleElement(def_operands(RegNo));
446 }
447
448 /// Returns the defining operand if there is exactly one operand defining the
449 /// specified register, otherwise nullptr.
450 MachineOperand *getOneDef(Register Reg) const {
451 def_iterator DI = def_begin(Reg);
452 if (DI == def_end()) // No defs.
453 return nullptr;
454
455 def_iterator OneDef = DI;
456 if (++DI == def_end())
457 return &*OneDef;
458 return nullptr; // Multiple defs.
459 }
460
461 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
462 using use_iterator =
463 defusechain_iterator<true, false, false, true, false, false>;
464 use_iterator use_begin(Register RegNo) const {
465 return use_iterator(getRegUseDefListHead(RegNo));
466 }
467 static use_iterator use_end() { return use_iterator(nullptr); }
468
469 inline iterator_range<use_iterator> use_operands(Register Reg) const {
470 return make_range(use_begin(Reg), use_end());
471 }
472
473 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
474 /// specified register, stepping by MachineInstr.
475 using use_instr_iterator =
476 defusechain_instr_iterator<true, false, false, false, true, false>;
477 use_instr_iterator use_instr_begin(Register RegNo) const {
478 return use_instr_iterator(getRegUseDefListHead(RegNo));
479 }
480 static use_instr_iterator use_instr_end() {
481 return use_instr_iterator(nullptr);
482 }
483
484 inline iterator_range<use_instr_iterator>
485 use_instructions(Register Reg) const {
486 return make_range(use_instr_begin(Reg), use_instr_end());
487 }
488
489 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
490 /// specified register, stepping by bundle.
491 using use_bundle_iterator =
492 defusechain_instr_iterator<true, false, false, false, false, true>;
493 use_bundle_iterator use_bundle_begin(Register RegNo) const {
494 return use_bundle_iterator(getRegUseDefListHead(RegNo));
495 }
496 static use_bundle_iterator use_bundle_end() {
497 return use_bundle_iterator(nullptr);
498 }
499
500 inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const {
501 return make_range(use_bundle_begin(Reg), use_bundle_end());
502 }
503
504 /// use_empty - Return true if there are no instructions using the specified
505 /// register.
506 bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
507
508 /// hasOneUse - Return true if there is exactly one instruction using the
509 /// specified register.
510 bool hasOneUse(Register RegNo) const {
511 return hasSingleElement(use_operands(RegNo));
512 }
513
514 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
515 /// specified register, skipping those marked as Debug.
516 using use_nodbg_iterator =
517 defusechain_iterator<true, false, true, true, false, false>;
518 use_nodbg_iterator use_nodbg_begin(Register RegNo) const {
519 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
520 }
521 static use_nodbg_iterator use_nodbg_end() {
522 return use_nodbg_iterator(nullptr);
523 }
524
525 inline iterator_range<use_nodbg_iterator>
526 use_nodbg_operands(Register Reg) const {
527 return make_range(use_nodbg_begin(Reg), use_nodbg_end());
528 }
529
530 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
531 /// all uses of the specified register, stepping by MachineInstr, skipping
532 /// those marked as Debug.
533 using use_instr_nodbg_iterator =
534 defusechain_instr_iterator<true, false, true, false, true, false>;
535 use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const {
536 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
537 }
538 static use_instr_nodbg_iterator use_instr_nodbg_end() {
539 return use_instr_nodbg_iterator(nullptr);
540 }
541
542 inline iterator_range<use_instr_nodbg_iterator>
543 use_nodbg_instructions(Register Reg) const {
544 return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
545 }
546
547 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
548 /// all uses of the specified register, stepping by bundle, skipping
549 /// those marked as Debug.
550 using use_bundle_nodbg_iterator =
551 defusechain_instr_iterator<true, false, true, false, false, true>;
552 use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const {
553 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
554 }
555 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
556 return use_bundle_nodbg_iterator(nullptr);
557 }
558
559 inline iterator_range<use_bundle_nodbg_iterator>
560 use_nodbg_bundles(Register Reg) const {
561 return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
562 }
563
564 /// use_nodbg_empty - Return true if there are no non-Debug instructions
565 /// using the specified register.
566 bool use_nodbg_empty(Register RegNo) const {
567 return use_nodbg_begin(RegNo) == use_nodbg_end();
568 }
569
570 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
571 /// use of the specified register.
572 bool hasOneNonDBGUse(Register RegNo) const;
573
574 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
575 /// instruction using the specified register. Said instruction may have
576 /// multiple uses.
577 bool hasOneNonDBGUser(Register RegNo) const;
578
579 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
580 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
581 /// except that it also changes any definitions of the register as well.
582 ///
583 /// Note that it is usually necessary to first constrain ToReg's register
584 /// class and register bank to match the FromReg constraints using one of the
585 /// methods:
586 ///
587 /// constrainRegClass(ToReg, getRegClass(FromReg))
588 /// constrainRegAttrs(ToReg, FromReg)
589 /// RegisterBankInfo::constrainGenericRegister(ToReg,
590 /// *MRI.getRegClass(FromReg), MRI)
591 ///
592 /// These functions will return a falsy result if the virtual registers have
593 /// incompatible constraints.
594 ///
595 /// Note that if ToReg is a physical register the function will replace and
596 /// apply sub registers to ToReg in order to obtain a final/proper physical
597 /// register.
598 void replaceRegWith(Register FromReg, Register ToReg);
599
600 /// getVRegDef - Return the machine instr that defines the specified virtual
601 /// register or null if none is found. This assumes that the code is in SSA
602 /// form, so there should only be one definition.
603 MachineInstr *getVRegDef(Register Reg) const;
604
605 /// getUniqueVRegDef - Return the unique machine instr that defines the
606 /// specified virtual register or null if none is found. If there are
607 /// multiple definitions or no definition, return null.
608 MachineInstr *getUniqueVRegDef(Register Reg) const;
609
610 /// clearKillFlags - Iterate over all the uses of the given register and
611 /// clear the kill flag from the MachineOperand. This function is used by
612 /// optimization passes which extend register lifetimes and need only
613 /// preserve conservative kill flag information.
614 void clearKillFlags(Register Reg) const;
615
616 void dumpUses(Register RegNo) const;
617
618 /// Returns true if PhysReg is unallocatable and constant throughout the
619 /// function. Writing to a constant register has no effect.
620 bool isConstantPhysReg(MCRegister PhysReg) const;
621
622 /// Get an iterator over the pressure sets affected by the given physical or
623 /// virtual register. If RegUnit is physical, it must be a register unit (from
624 /// MCRegUnitIterator).
625 PSetIterator getPressureSets(Register RegUnit) const;
626
627 //===--------------------------------------------------------------------===//
628 // Virtual Register Info
629 //===--------------------------------------------------------------------===//
630
631 /// Return the register class of the specified virtual register.
632 /// This shouldn't be used directly unless \p Reg has a register class.
633 /// \see getRegClassOrNull when this might happen.
634 const TargetRegisterClass *getRegClass(Register Reg) const {
635 assert(VRegInfo[Reg.id()].first.is<const TargetRegisterClass *>() &&
636 "Register class not set, wrong accessor");
637 return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>();
638 }
639
640 /// Return the register class of \p Reg, or null if Reg has not been assigned
641 /// a register class yet.
642 ///
643 /// \note A null register class can only happen when these two
644 /// conditions are met:
645 /// 1. Generic virtual registers are created.
646 /// 2. The machine function has not completely been through the
647 /// instruction selection process.
648 /// None of this condition is possible without GlobalISel for now.
649 /// In other words, if GlobalISel is not used or if the query happens after
650 /// the select pass, using getRegClass is safe.
651 const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
652 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
653 return Val.dyn_cast<const TargetRegisterClass *>();
654 }
655
656 /// Return the register bank of \p Reg, or null if Reg has not been assigned
657 /// a register bank or has been assigned a register class.
658 /// \note It is possible to get the register bank from the register class via
659 /// RegisterBankInfo::getRegBankFromRegClass.
660 const RegisterBank *getRegBankOrNull(Register Reg) const {
661 const RegClassOrRegBank &Val = VRegInfo[Reg].first;
662 return Val.dyn_cast<const RegisterBank *>();
663 }
664
665 /// Return the register bank or register class of \p Reg.
666 /// \note Before the register bank gets assigned (i.e., before the
667 /// RegBankSelect pass) \p Reg may not have either.
668 const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const {
669 return VRegInfo[Reg].first;
670 }
671
672 /// setRegClass - Set the register class of the specified virtual register.
673 void setRegClass(Register Reg, const TargetRegisterClass *RC);
674
675 /// Set the register bank to \p RegBank for \p Reg.
676 void setRegBank(Register Reg, const RegisterBank &RegBank);
677
678 void setRegClassOrRegBank(Register Reg,
679 const RegClassOrRegBank &RCOrRB){
680 VRegInfo[Reg].first = RCOrRB;
681 }
682
683 /// constrainRegClass - Constrain the register class of the specified virtual
684 /// register to be a common subclass of RC and the current register class,
685 /// but only if the new class has at least MinNumRegs registers. Return the
686 /// new register class, or NULL if no such class exists.
687 /// This should only be used when the constraint is known to be trivial, like
688 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
689 ///
690 /// \note Assumes that the register has a register class assigned.
691 /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
692 /// InstructionSelect pass and constrainRegAttrs in every other pass,
693 /// including non-select passes of GlobalISel, instead.
694 const TargetRegisterClass *constrainRegClass(Register Reg,
695 const TargetRegisterClass *RC,
696 unsigned MinNumRegs = 0);
697
698 /// Constrain the register class or the register bank of the virtual register
699 /// \p Reg (and low-level type) to be a common subclass or a common bank of
700 /// both registers provided respectively (and a common low-level type). Do
701 /// nothing if any of the attributes (classes, banks, or low-level types) of
702 /// the registers are deemed incompatible, or if the resulting register will
703 /// have a class smaller than before and of size less than \p MinNumRegs.
704 /// Return true if such register attributes exist, false otherwise.
705 ///
706 /// \note Use this method instead of constrainRegClass and
707 /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
708 /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
709 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
710 unsigned MinNumRegs = 0);
711
712 /// recomputeRegClass - Try to find a legal super-class of Reg's register
713 /// class that still satisfies the constraints from the instructions using
714 /// Reg. Returns true if Reg was upgraded.
715 ///
716 /// This method can be used after constraints have been removed from a
717 /// virtual register, for example after removing instructions or splitting
718 /// the live range.
719 bool recomputeRegClass(Register Reg);
720
721 /// createVirtualRegister - Create and return a new virtual register in the
722 /// function with the specified register class.
723 Register createVirtualRegister(const TargetRegisterClass *RegClass,
724 StringRef Name = "");
725
726 /// Create and return a new virtual register in the function with the same
727 /// attributes as the given register.
728 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
729
730 /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
731 /// (target independent) virtual register.
732 LLT getType(Register Reg) const {
733 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
734 return VRegToType[Reg];
735 return LLT{};
736 }
737
738 /// Set the low-level type of \p VReg to \p Ty.
739 void setType(Register VReg, LLT Ty);
740
741 /// Create and return a new generic virtual register with low-level
742 /// type \p Ty.
743 Register createGenericVirtualRegister(LLT Ty, StringRef Name = "");
744
745 /// Remove all types associated to virtual registers (after instruction
746 /// selection and constraining of all generic virtual registers).
747 void clearVirtRegTypes();
748
749 /// Creates a new virtual register that has no register class, register bank
750 /// or size assigned yet. This is only allowed to be used
751 /// temporarily while constructing machine instructions. Most operations are
752 /// undefined on an incomplete register until one of setRegClass(),
753 /// setRegBank() or setSize() has been called on it.
754 Register createIncompleteVirtualRegister(StringRef Name = "");
755
756 /// getNumVirtRegs - Return the number of virtual registers created.
757 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
758
759 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
760 void clearVirtRegs();
761
762 /// setRegAllocationHint - Specify a register allocation hint for the
763 /// specified virtual register. This is typically used by target, and in case
764 /// of an earlier hint it will be overwritten.
765 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
766 assert(VReg.isVirtual());
767 RegAllocHints[VReg].first = Type;
768 RegAllocHints[VReg].second.clear();
769 RegAllocHints[VReg].second.push_back(PrefReg);
770 }
771
772 /// addRegAllocationHint - Add a register allocation hint to the hints
773 /// vector for VReg.
774 void addRegAllocationHint(Register VReg, Register PrefReg) {
775 assert(Register::isVirtualRegister(VReg));
776 RegAllocHints[VReg].second.push_back(PrefReg);
777 }
778
779 /// Specify the preferred (target independent) register allocation hint for
780 /// the specified virtual register.
781 void setSimpleHint(Register VReg, Register PrefReg) {
782 setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
783 }
784
785 void clearSimpleHint(Register VReg) {
786 assert (!RegAllocHints[VReg].first &&
787 "Expected to clear a non-target hint!");
788 RegAllocHints[VReg].second.clear();
789 }
790
791 /// getRegAllocationHint - Return the register allocation hint for the
792 /// specified virtual register. If there are many hints, this returns the
793 /// one with the greatest weight.
794 std::pair<Register, Register>
795 getRegAllocationHint(Register VReg) const {
796 assert(VReg.isVirtual());
797 Register BestHint = (RegAllocHints[VReg.id()].second.size() ?
798 RegAllocHints[VReg.id()].second[0] : Register());
799 return std::pair<Register, Register>(RegAllocHints[VReg.id()].first,
800 BestHint);
801 }
802
803 /// getSimpleHint - same as getRegAllocationHint except it will only return
804 /// a target independent hint.
805 Register getSimpleHint(Register VReg) const {
806 assert(VReg.isVirtual());
807 std::pair<Register, Register> Hint = getRegAllocationHint(VReg);
808 return Hint.first ? Register() : Hint.second;
809 }
810
811 /// getRegAllocationHints - Return a reference to the vector of all
812 /// register allocation hints for VReg.
813 const std::pair<Register, SmallVector<Register, 4>>
814 &getRegAllocationHints(Register VReg) const {
815 assert(VReg.isVirtual());
816 return RegAllocHints[VReg];
817 }
818
819 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
820 /// specified register as undefined which causes the DBG_VALUE to be
821 /// deleted during LiveDebugVariables analysis.
822 void markUsesInDebugValueAsUndef(Register Reg) const;
823
824 /// updateDbgUsersToReg - Update a collection of DBG_VALUE instructions
825 /// to refer to the designated register.
826 void updateDbgUsersToReg(Register Reg,
827 ArrayRef<MachineInstr*> Users) const {
828 for (MachineInstr *MI : Users) {
829 assert(MI->isDebugInstr());
830 assert(MI->getOperand(0).isReg());
831 MI->getOperand(0).setReg(Reg);
832 }
833 }
834
835 /// Return true if the specified register is modified in this function.
836 /// This checks that no defining machine operands exist for the register or
837 /// any of its aliases. Definitions found on functions marked noreturn are
838 /// ignored, to consider them pass 'true' for optional parameter
839 /// SkipNoReturnDef. The register is also considered modified when it is set
840 /// in the UsedPhysRegMask.
841 bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
842
843 /// Return true if the specified register is modified or read in this
844 /// function. This checks that no machine operands exist for the register or
845 /// any of its aliases. The register is also considered used when it is set
846 /// in the UsedPhysRegMask.
847 bool isPhysRegUsed(MCRegister PhysReg) const;
848
849 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
850 /// This corresponds to the bit mask attached to register mask operands.
851 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
852 UsedPhysRegMask.setBitsNotInMask(RegMask);
853 }
854
855 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
856
857 //===--------------------------------------------------------------------===//
858 // Reserved Register Info
859 //===--------------------------------------------------------------------===//
860 //
861 // The set of reserved registers must be invariant during register
862 // allocation. For example, the target cannot suddenly decide it needs a
863 // frame pointer when the register allocator has already used the frame
864 // pointer register for something else.
865 //
866 // These methods can be used by target hooks like hasFP() to avoid changing
867 // the reserved register set during register allocation.
868
869 /// freezeReservedRegs - Called by the register allocator to freeze the set
870 /// of reserved registers before allocation begins.
871 void freezeReservedRegs(const MachineFunction&);
872
873 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
874 /// to ensure the set of reserved registers stays constant.
875 bool reservedRegsFrozen() const {
876 return !ReservedRegs.empty();
877 }
878
879 /// canReserveReg - Returns true if PhysReg can be used as a reserved
880 /// register. Any register can be reserved before freezeReservedRegs() is
881 /// called.
882 bool canReserveReg(MCRegister PhysReg) const {
883 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
884 }
885
886 /// getReservedRegs - Returns a reference to the frozen set of reserved
887 /// registers. This method should always be preferred to calling
888 /// TRI::getReservedRegs() when possible.
889 const BitVector &getReservedRegs() const {
890 assert(reservedRegsFrozen() &&
891 "Reserved registers haven't been frozen yet. "
892 "Use TRI::getReservedRegs().");
893 return ReservedRegs;
894 }
895
896 /// isReserved - Returns true when PhysReg is a reserved register.
897 ///
898 /// Reserved registers may belong to an allocatable register class, but the
899 /// target has explicitly requested that they are not used.
900 bool isReserved(MCRegister PhysReg) const {
901 return getReservedRegs().test(PhysReg.id());
902 }
903
904 /// Returns true when the given register unit is considered reserved.
905 ///
906 /// Register units are considered reserved when for at least one of their
907 /// root registers, the root register and all super registers are reserved.
908 /// This currently iterates the register hierarchy and may be slower than
909 /// expected.
910 bool isReservedRegUnit(unsigned Unit) const;
911
912 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
913 /// register class and it hasn't been reserved.
914 ///
915 /// Allocatable registers may show up in the allocation order of some virtual
916 /// register, so a register allocator needs to track its liveness and
917 /// availability.
918 bool isAllocatable(MCRegister PhysReg) const {
919 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
920 !isReserved(PhysReg);
921 }
922
923 //===--------------------------------------------------------------------===//
924 // LiveIn Management
925 //===--------------------------------------------------------------------===//
926
927 /// addLiveIn - Add the specified register as a live-in. Note that it
928 /// is an error to add the same register to the same set more than once.
929 void addLiveIn(MCRegister Reg, Register vreg = Register()) {
930 LiveIns.push_back(std::make_pair(Reg, vreg));
931 }
932
933 // Iteration support for the live-ins set. It's kept in sorted order
934 // by register number.
935 using livein_iterator =
936 std::vector<std::pair<MCRegister,Register>>::const_iterator;
937 livein_iterator livein_begin() const { return LiveIns.begin(); }
938 livein_iterator livein_end() const { return LiveIns.end(); }
939 bool livein_empty() const { return LiveIns.empty(); }
940
941 ArrayRef<std::pair<MCRegister, Register>> liveins() const {
942 return LiveIns;
943 }
944
945 bool isLiveIn(Register Reg) const;
946
947 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
948 /// corresponding live-in physical register.
949 MCRegister getLiveInPhysReg(Register VReg) const;
950
951 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
952 /// corresponding live-in physical register.
953 Register getLiveInVirtReg(MCRegister PReg) const;
954
955 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
956 /// into the given entry block.
957 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
958 const TargetRegisterInfo &TRI,
959 const TargetInstrInfo &TII);
960
961 /// Returns a mask covering all bits that can appear in lane masks of
962 /// subregisters of the virtual register @p Reg.
963 LaneBitmask getMaxLaneMaskForVReg(Register Reg) const;
964
965 /// defusechain_iterator - This class provides iterator support for machine
966 /// operands in the function that use or define a specific register. If
967 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
968 /// returns defs. If neither are true then you are silly and it always
969 /// returns end(). If SkipDebug is true it skips uses marked Debug
970 /// when incrementing.
971 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
972 bool ByInstr, bool ByBundle>
973 class defusechain_iterator {
974 friend class MachineRegisterInfo;
975
976 public:
977 using iterator_category = std::forward_iterator_tag;
978 using value_type = MachineOperand;
979 using difference_type = std::ptrdiff_t;
980 using pointer = value_type *;
981 using reference = value_type &;
982
983 private:
984 MachineOperand *Op = nullptr;
985
986 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
987 // If the first node isn't one we're interested in, advance to one that
988 // we are interested in.
989 if (op) {
990 if ((!ReturnUses && op->isUse()) ||
991 (!ReturnDefs && op->isDef()) ||
992 (SkipDebug && op->isDebug()))
993 advance();
994 }
995 }
996
997 void advance() {
998 assert(Op && "Cannot increment end iterator!");
999 Op = getNextOperandForReg(Op);
1000
1001 // All defs come before the uses, so stop def_iterator early.
1002 if (!ReturnUses) {
1003 if (Op) {
1004 if (Op->isUse())
1005 Op = nullptr;
1006 else
1007 assert(!Op->isDebug() && "Can't have debug defs");
1008 }
1009 } else {
1010 // If this is an operand we don't care about, skip it.
1011 while (Op && ((!ReturnDefs && Op->isDef()) ||
1012 (SkipDebug && Op->isDebug())))
1013 Op = getNextOperandForReg(Op);
1014 }
1015 }
1016
1017 public:
1018 defusechain_iterator() = default;
1019
1020 bool operator==(const defusechain_iterator &x) const {
1021 return Op == x.Op;
1022 }
1023 bool operator!=(const defusechain_iterator &x) const {
1024 return !operator==(x);
1025 }
1026
1027 /// atEnd - return true if this iterator is equal to reg_end() on the value.
1028 bool atEnd() const { return Op == nullptr; }
1029
1030 // Iterator traversal: forward iteration only
1031 defusechain_iterator &operator++() { // Preincrement
1032 assert(Op && "Cannot increment end iterator!");
1033 if (ByOperand)
1034 advance();
1035 else if (ByInstr) {
1036 MachineInstr *P = Op->getParent();
1037 do {
1038 advance();
1039 } while (Op && Op->getParent() == P);
1040 } else if (ByBundle) {
1041 MachineBasicBlock::instr_iterator P =
1042 getBundleStart(Op->getParent()->getIterator());
1043 do {
1044 advance();
1045 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1046 }
1047
1048 return *this;
1049 }
1050 defusechain_iterator operator++(int) { // Postincrement
1051 defusechain_iterator tmp = *this; ++*this; return tmp;
1052 }
1053
1054 /// getOperandNo - Return the operand # of this MachineOperand in its
1055 /// MachineInstr.
1056 unsigned getOperandNo() const {
1057 assert(Op && "Cannot dereference end iterator!");
1058 return Op - &Op->getParent()->getOperand(0);
1059 }
1060
1061 // Retrieve a reference to the current operand.
1062 MachineOperand &operator*() const {
1063 assert(Op && "Cannot dereference end iterator!");
1064 return *Op;
1065 }
1066
1067 MachineOperand *operator->() const {
1068 assert(Op && "Cannot dereference end iterator!");
1069 return Op;
1070 }
1071 };
1072
1073 /// defusechain_iterator - This class provides iterator support for machine
1074 /// operands in the function that use or define a specific register. If
1075 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
1076 /// returns defs. If neither are true then you are silly and it always
1077 /// returns end(). If SkipDebug is true it skips uses marked Debug
1078 /// when incrementing.
1079 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,
1080 bool ByInstr, bool ByBundle>
1081 class defusechain_instr_iterator {
1082 friend class MachineRegisterInfo;
1083
1084 public:
1085 using iterator_category = std::forward_iterator_tag;
1086 using value_type = MachineInstr;
1087 using difference_type = std::ptrdiff_t;
1088 using pointer = value_type *;
1089 using reference = value_type &;
1090
1091 private:
1092 MachineOperand *Op = nullptr;
1093
1094 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
1095 // If the first node isn't one we're interested in, advance to one that
1096 // we are interested in.
1097 if (op) {
1098 if ((!ReturnUses && op->isUse()) ||
1099 (!ReturnDefs && op->isDef()) ||
1100 (SkipDebug && op->isDebug()))
1101 advance();
1102 }
1103 }
1104
1105 void advance() {
1106 assert(Op && "Cannot increment end iterator!");
1107 Op = getNextOperandForReg(Op);
1108
1109 // All defs come before the uses, so stop def_iterator early.
1110 if (!ReturnUses) {
1111 if (Op) {
1112 if (Op->isUse())
1113 Op = nullptr;
1114 else
1115 assert(!Op->isDebug() && "Can't have debug defs");
1116 }
1117 } else {
1118 // If this is an operand we don't care about, skip it.
1119 while (Op && ((!ReturnDefs && Op->isDef()) ||
1120 (SkipDebug && Op->isDebug())))
1121 Op = getNextOperandForReg(Op);
1122 }
1123 }
1124
1125 public:
1126 defusechain_instr_iterator() = default;
1127
1128 bool operator==(const defusechain_instr_iterator &x) const {
1129 return Op == x.Op;
1130 }
1131 bool operator!=(const defusechain_instr_iterator &x) const {
1132 return !operator==(x);
1133 }
1134
1135 /// atEnd - return true if this iterator is equal to reg_end() on the value.
1136 bool atEnd() const { return Op == nullptr; }
1137
1138 // Iterator traversal: forward iteration only
1139 defusechain_instr_iterator &operator++() { // Preincrement
1140 assert(Op && "Cannot increment end iterator!");
1141 if (ByOperand)
1142 advance();
1143 else if (ByInstr) {
1144 MachineInstr *P = Op->getParent();
1145 do {
1146 advance();
1147 } while (Op && Op->getParent() == P);
1148 } else if (ByBundle) {
1149 MachineBasicBlock::instr_iterator P =
1150 getBundleStart(Op->getParent()->getIterator());
1151 do {
1152 advance();
1153 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1154 }
1155
1156 return *this;
1157 }
1158 defusechain_instr_iterator operator++(int) { // Postincrement
1159 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1160 }
1161
1162 // Retrieve a reference to the current operand.
1163 MachineInstr &operator*() const {
1164 assert(Op && "Cannot dereference end iterator!");
1165 if (ByBundle)
1166 return *getBundleStart(Op->getParent()->getIterator());
1167 return *Op->getParent();
1168 }
1169
1170 MachineInstr *operator->() const { return &operator*(); }
1171 };
1172};
1173
1174/// Iterate over the pressure sets affected by the given physical or virtual
1175/// register. If Reg is physical, it must be a register unit (from
1176/// MCRegUnitIterator).
1177class PSetIterator {
1178 const int *PSet = nullptr;
1179 unsigned Weight = 0;
1180
1181public:
1182 PSetIterator() = default;
1183
1184 PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) {
1185 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1186 if (RegUnit.isVirtual()) {
1187 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1188 PSet = TRI->getRegClassPressureSets(RC);
1189 Weight = TRI->getRegClassWeight(RC).RegWeight;
1190 } else {
1191 PSet = TRI->getRegUnitPressureSets(RegUnit);
1192 Weight = TRI->getRegUnitWeight(RegUnit);
1193 }
1194 if (*PSet == -1)
1195 PSet = nullptr;
1196 }
1197
1198 bool isValid() const { return PSet; }
1199
1200 unsigned getWeight() const { return Weight; }
1201
1202 unsigned operator*() const { return *PSet; }
1203
1204 void operator++() {
1205 assert(isValid() && "Invalid PSetIterator.");
1206 ++PSet;
1207 if (*PSet == -1)
1208 PSet = nullptr;
1209 }
1210};
1211
1212inline PSetIterator
1213MachineRegisterInfo::getPressureSets(Register RegUnit) const {
1214 return PSetIterator(RegUnit, this);
1215}
1216
1217} // end namespace llvm
1218
1219#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
1220