1 | //===- TargetPassConfig.h - Code Generation pass options --------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | /// \file |
9 | /// Target-Independent Code Generator Pass Configuration Options pass. |
10 | /// |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H |
14 | #define LLVM_CODEGEN_TARGETPASSCONFIG_H |
15 | |
16 | #include "llvm/Pass.h" |
17 | #include "llvm/Support/CodeGen.h" |
18 | #include "llvm/Support/Error.h" |
19 | #include <cassert> |
20 | #include <string> |
21 | |
22 | namespace llvm { |
23 | |
24 | class LLVMTargetMachine; |
25 | struct MachineSchedContext; |
26 | class PassConfigImpl; |
27 | class ScheduleDAGInstrs; |
28 | class CSEConfigBase; |
29 | class PassInstrumentationCallbacks; |
30 | |
31 | // The old pass manager infrastructure is hidden in a legacy namespace now. |
32 | namespace legacy { |
33 | |
34 | class PassManagerBase; |
35 | |
36 | } // end namespace legacy |
37 | |
38 | using legacy::PassManagerBase; |
39 | |
40 | /// Discriminated union of Pass ID types. |
41 | /// |
42 | /// The PassConfig API prefers dealing with IDs because they are safer and more |
43 | /// efficient. IDs decouple configuration from instantiation. This way, when a |
44 | /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to |
45 | /// refer to a Pass pointer after adding it to a pass manager, which deletes |
46 | /// redundant pass instances. |
47 | /// |
48 | /// However, it is convient to directly instantiate target passes with |
49 | /// non-default ctors. These often don't have a registered PassInfo. Rather than |
50 | /// force all target passes to implement the pass registry boilerplate, allow |
51 | /// the PassConfig API to handle either type. |
52 | /// |
53 | /// AnalysisID is sadly char*, so PointerIntPair won't work. |
54 | class IdentifyingPassPtr { |
55 | union { |
56 | AnalysisID ID; |
57 | Pass *P; |
58 | }; |
59 | bool IsInstance = false; |
60 | |
61 | public: |
62 | IdentifyingPassPtr() : P(nullptr) {} |
63 | IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr) {} |
64 | IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {} |
65 | |
66 | bool isValid() const { return P; } |
67 | bool isInstance() const { return IsInstance; } |
68 | |
69 | AnalysisID getID() const { |
70 | assert(!IsInstance && "Not a Pass ID" ); |
71 | return ID; |
72 | } |
73 | |
74 | Pass *getInstance() const { |
75 | assert(IsInstance && "Not a Pass Instance" ); |
76 | return P; |
77 | } |
78 | }; |
79 | |
80 | |
81 | /// Target-Independent Code Generator Pass Configuration Options. |
82 | /// |
83 | /// This is an ImmutablePass solely for the purpose of exposing CodeGen options |
84 | /// to the internals of other CodeGen passes. |
85 | class TargetPassConfig : public ImmutablePass { |
86 | private: |
87 | PassManagerBase *PM = nullptr; |
88 | AnalysisID StartBefore = nullptr; |
89 | AnalysisID StartAfter = nullptr; |
90 | AnalysisID StopBefore = nullptr; |
91 | AnalysisID StopAfter = nullptr; |
92 | |
93 | unsigned StartBeforeInstanceNum = 0; |
94 | unsigned StartBeforeCount = 0; |
95 | |
96 | unsigned StartAfterInstanceNum = 0; |
97 | unsigned StartAfterCount = 0; |
98 | |
99 | unsigned StopBeforeInstanceNum = 0; |
100 | unsigned StopBeforeCount = 0; |
101 | |
102 | unsigned StopAfterInstanceNum = 0; |
103 | unsigned StopAfterCount = 0; |
104 | |
105 | bool Started = true; |
106 | bool Stopped = false; |
107 | bool AddingMachinePasses = false; |
108 | bool DebugifyIsSafe = true; |
109 | |
110 | /// Set the StartAfter, StartBefore and StopAfter passes to allow running only |
111 | /// a portion of the normal code-gen pass sequence. |
112 | /// |
113 | /// If the StartAfter and StartBefore pass ID is zero, then compilation will |
114 | /// begin at the normal point; otherwise, clear the Started flag to indicate |
115 | /// that passes should not be added until the starting pass is seen. If the |
116 | /// Stop pass ID is zero, then compilation will continue to the end. |
117 | /// |
118 | /// This function expects that at least one of the StartAfter or the |
119 | /// StartBefore pass IDs is null. |
120 | void setStartStopPasses(); |
121 | |
122 | protected: |
123 | LLVMTargetMachine *TM; |
124 | PassConfigImpl *Impl = nullptr; // Internal data structures |
125 | bool Initialized = false; // Flagged after all passes are configured. |
126 | |
127 | // Target Pass Options |
128 | // Targets provide a default setting, user flags override. |
129 | bool DisableVerify = false; |
130 | |
131 | /// Default setting for -enable-tail-merge on this target. |
132 | bool EnableTailMerge = true; |
133 | |
134 | /// Enable sinking of instructions in MachineSink where a computation can be |
135 | /// folded into the addressing mode of a memory load/store instruction or |
136 | /// replace a copy. |
137 | bool EnableSinkAndFold = false; |
138 | |
139 | /// Require processing of functions such that callees are generated before |
140 | /// callers. |
141 | bool RequireCodeGenSCCOrder = false; |
142 | |
143 | /// Add the actual instruction selection passes. This does not include |
144 | /// preparation passes on IR. |
145 | bool addCoreISelPasses(); |
146 | |
147 | public: |
148 | TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm); |
149 | // Dummy constructor. |
150 | TargetPassConfig(); |
151 | |
152 | ~TargetPassConfig() override; |
153 | |
154 | static char ID; |
155 | |
156 | /// Get the right type of TargetMachine for this target. |
157 | template<typename TMC> TMC &getTM() const { |
158 | return *static_cast<TMC*>(TM); |
159 | } |
160 | |
161 | // |
162 | void setInitialized() { Initialized = true; } |
163 | |
164 | CodeGenOptLevel getOptLevel() const; |
165 | |
166 | /// Returns true if one of the `-start-after`, `-start-before`, `-stop-after` |
167 | /// or `-stop-before` options is set. |
168 | static bool hasLimitedCodeGenPipeline(); |
169 | |
170 | /// Returns true if none of the `-stop-before` and `-stop-after` options is |
171 | /// set. |
172 | static bool willCompleteCodeGenPipeline(); |
173 | |
174 | /// If hasLimitedCodeGenPipeline is true, this method returns |
175 | /// a string with the name of the options that caused this |
176 | /// pipeline to be limited. |
177 | static std::string getLimitedCodeGenPipelineReason(); |
178 | |
179 | struct StartStopInfo { |
180 | bool StartAfter; |
181 | bool StopAfter; |
182 | unsigned StartInstanceNum; |
183 | unsigned StopInstanceNum; |
184 | StringRef StartPass; |
185 | StringRef StopPass; |
186 | }; |
187 | |
188 | /// Returns pass name in `-stop-before` or `-stop-after` |
189 | /// NOTE: New pass manager migration only |
190 | static Expected<StartStopInfo> |
191 | getStartStopInfo(PassInstrumentationCallbacks &PIC); |
192 | |
193 | void setDisableVerify(bool Disable) { setOpt(Opt&: DisableVerify, Val: Disable); } |
194 | |
195 | bool getEnableTailMerge() const { return EnableTailMerge; } |
196 | void setEnableTailMerge(bool Enable) { setOpt(Opt&: EnableTailMerge, Val: Enable); } |
197 | |
198 | bool getEnableSinkAndFold() const { return EnableSinkAndFold; } |
199 | void setEnableSinkAndFold(bool Enable) { setOpt(Opt&: EnableSinkAndFold, Val: Enable); } |
200 | |
201 | bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; } |
202 | void setRequiresCodeGenSCCOrder(bool Enable = true) { |
203 | setOpt(Opt&: RequireCodeGenSCCOrder, Val: Enable); |
204 | } |
205 | |
206 | /// Allow the target to override a specific pass without overriding the pass |
207 | /// pipeline. When passes are added to the standard pipeline at the |
208 | /// point where StandardID is expected, add TargetID in its place. |
209 | void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID); |
210 | |
211 | /// Insert InsertedPassID pass after TargetPassID pass. |
212 | void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID); |
213 | |
214 | /// Allow the target to enable a specific standard pass by default. |
215 | void enablePass(AnalysisID PassID) { substitutePass(StandardID: PassID, TargetID: PassID); } |
216 | |
217 | /// Allow the target to disable a specific standard pass by default. |
218 | void disablePass(AnalysisID PassID) { |
219 | substitutePass(StandardID: PassID, TargetID: IdentifyingPassPtr()); |
220 | } |
221 | |
222 | /// Return the pass substituted for StandardID by the target. |
223 | /// If no substitution exists, return StandardID. |
224 | IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const; |
225 | |
226 | /// Return true if the pass has been substituted by the target or |
227 | /// overridden on the command line. |
228 | bool isPassSubstitutedOrOverridden(AnalysisID ID) const; |
229 | |
230 | /// Return true if the optimized regalloc pipeline is enabled. |
231 | bool getOptimizeRegAlloc() const; |
232 | |
233 | /// Return true if the default global register allocator is in use and |
234 | /// has not be overriden on the command line with '-regalloc=...' |
235 | bool usingDefaultRegAlloc() const; |
236 | |
237 | /// High level function that adds all passes necessary to go from llvm IR |
238 | /// representation to the MI representation. |
239 | /// Adds IR based lowering and target specific optimization passes and finally |
240 | /// the core instruction selection passes. |
241 | /// \returns true if an error occurred, false otherwise. |
242 | bool addISelPasses(); |
243 | |
244 | /// Add common target configurable passes that perform LLVM IR to IR |
245 | /// transforms following machine independent optimization. |
246 | virtual void addIRPasses(); |
247 | |
248 | /// Add passes to lower exception handling for the code generator. |
249 | void addPassesToHandleExceptions(); |
250 | |
251 | /// Add pass to prepare the LLVM IR for code generation. This should be done |
252 | /// before exception handling preparation passes. |
253 | virtual void addCodeGenPrepare(); |
254 | |
255 | /// Add common passes that perform LLVM IR to IR transforms in preparation for |
256 | /// instruction selection. |
257 | virtual void addISelPrepare(); |
258 | |
259 | /// addInstSelector - This method should install an instruction selector pass, |
260 | /// which converts from LLVM code to machine instructions. |
261 | virtual bool addInstSelector() { |
262 | return true; |
263 | } |
264 | |
265 | /// This method should install an IR translator pass, which converts from |
266 | /// LLVM code to machine instructions with possibly generic opcodes. |
267 | virtual bool addIRTranslator() { return true; } |
268 | |
269 | /// This method may be implemented by targets that want to run passes |
270 | /// immediately before legalization. |
271 | virtual void addPreLegalizeMachineIR() {} |
272 | |
273 | /// This method should install a legalize pass, which converts the instruction |
274 | /// sequence into one that can be selected by the target. |
275 | virtual bool addLegalizeMachineIR() { return true; } |
276 | |
277 | /// This method may be implemented by targets that want to run passes |
278 | /// immediately before the register bank selection. |
279 | virtual void addPreRegBankSelect() {} |
280 | |
281 | /// This method should install a register bank selector pass, which |
282 | /// assigns register banks to virtual registers without a register |
283 | /// class or register banks. |
284 | virtual bool addRegBankSelect() { return true; } |
285 | |
286 | /// This method may be implemented by targets that want to run passes |
287 | /// immediately before the (global) instruction selection. |
288 | virtual void addPreGlobalInstructionSelect() {} |
289 | |
290 | /// This method should install a (global) instruction selector pass, which |
291 | /// converts possibly generic instructions to fully target-specific |
292 | /// instructions, thereby constraining all generic virtual registers to |
293 | /// register classes. |
294 | virtual bool addGlobalInstructionSelect() { return true; } |
295 | |
296 | /// Add the complete, standard set of LLVM CodeGen passes. |
297 | /// Fully developed targets will not generally override this. |
298 | virtual void addMachinePasses(); |
299 | |
300 | /// Create an instance of ScheduleDAGInstrs to be run within the standard |
301 | /// MachineScheduler pass for this function and target at the current |
302 | /// optimization level. |
303 | /// |
304 | /// This can also be used to plug a new MachineSchedStrategy into an instance |
305 | /// of the standard ScheduleDAGMI: |
306 | /// return new ScheduleDAGMI(C, std::make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false) |
307 | /// |
308 | /// Return NULL to select the default (generic) machine scheduler. |
309 | virtual ScheduleDAGInstrs * |
310 | createMachineScheduler(MachineSchedContext *C) const { |
311 | return nullptr; |
312 | } |
313 | |
314 | /// Similar to createMachineScheduler but used when postRA machine scheduling |
315 | /// is enabled. |
316 | virtual ScheduleDAGInstrs * |
317 | createPostMachineScheduler(MachineSchedContext *C) const { |
318 | return nullptr; |
319 | } |
320 | |
321 | /// printAndVerify - Add a pass to dump then verify the machine function, if |
322 | /// those steps are enabled. |
323 | void printAndVerify(const std::string &Banner); |
324 | |
325 | /// Add a pass to print the machine function if printing is enabled. |
326 | void addPrintPass(const std::string &Banner); |
327 | |
328 | /// Add a pass to perform basic verification of the machine function if |
329 | /// verification is enabled. |
330 | void addVerifyPass(const std::string &Banner); |
331 | |
332 | /// Add a pass to add synthesized debug info to the MIR. |
333 | void addDebugifyPass(); |
334 | |
335 | /// Add a pass to remove debug info from the MIR. |
336 | void addStripDebugPass(); |
337 | |
338 | /// Add a pass to check synthesized debug info for MIR. |
339 | void addCheckDebugPass(); |
340 | |
341 | /// Add standard passes before a pass that's about to be added. For example, |
342 | /// the DebugifyMachineModulePass if it is enabled. |
343 | void addMachinePrePasses(bool AllowDebugify = true); |
344 | |
345 | /// Add standard passes after a pass that has just been added. For example, |
346 | /// the MachineVerifier if it is enabled. |
347 | void addMachinePostPasses(const std::string &Banner); |
348 | |
349 | /// Check whether or not GlobalISel should abort on error. |
350 | /// When this is disabled, GlobalISel will fall back on SDISel instead of |
351 | /// erroring out. |
352 | bool isGlobalISelAbortEnabled() const; |
353 | |
354 | /// Check whether or not a diagnostic should be emitted when GlobalISel |
355 | /// uses the fallback path. In other words, it will emit a diagnostic |
356 | /// when GlobalISel failed and isGlobalISelAbortEnabled is false. |
357 | virtual bool reportDiagnosticWhenGlobalISelFallback() const; |
358 | |
359 | /// Check whether continuous CSE should be enabled in GISel passes. |
360 | /// By default, it's enabled for non O0 levels. |
361 | virtual bool isGISelCSEEnabled() const; |
362 | |
363 | /// Returns the CSEConfig object to use for the current optimization level. |
364 | virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const; |
365 | |
366 | protected: |
367 | // Helper to verify the analysis is really immutable. |
368 | void setOpt(bool &Opt, bool Val); |
369 | |
370 | /// Return true if register allocator is specified by -regalloc=override. |
371 | bool isCustomizedRegAlloc(); |
372 | |
373 | /// Methods with trivial inline returns are convenient points in the common |
374 | /// codegen pass pipeline where targets may insert passes. Methods with |
375 | /// out-of-line standard implementations are major CodeGen stages called by |
376 | /// addMachinePasses. Some targets may override major stages when inserting |
377 | /// passes is insufficient, but maintaining overriden stages is more work. |
378 | /// |
379 | |
380 | /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM |
381 | /// passes (which are run just before instruction selector). |
382 | virtual bool addPreISel() { |
383 | return true; |
384 | } |
385 | |
386 | /// addMachineSSAOptimization - Add standard passes that optimize machine |
387 | /// instructions in SSA form. |
388 | virtual void addMachineSSAOptimization(); |
389 | |
390 | /// Add passes that optimize instruction level parallelism for out-of-order |
391 | /// targets. These passes are run while the machine code is still in SSA |
392 | /// form, so they can use MachineTraceMetrics to control their heuristics. |
393 | /// |
394 | /// All passes added here should preserve the MachineDominatorTree, |
395 | /// MachineLoopInfo, and MachineTraceMetrics analyses. |
396 | virtual bool addILPOpts() { |
397 | return false; |
398 | } |
399 | |
400 | /// This method may be implemented by targets that want to run passes |
401 | /// immediately before register allocation. |
402 | virtual void addPreRegAlloc() { } |
403 | |
404 | /// createTargetRegisterAllocator - Create the register allocator pass for |
405 | /// this target at the current optimization level. |
406 | virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); |
407 | |
408 | /// addFastRegAlloc - Add the minimum set of target-independent passes that |
409 | /// are required for fast register allocation. |
410 | virtual void addFastRegAlloc(); |
411 | |
412 | /// addOptimizedRegAlloc - Add passes related to register allocation. |
413 | /// LLVMTargetMachine provides standard regalloc passes for most targets. |
414 | virtual void addOptimizedRegAlloc(); |
415 | |
416 | /// addPreRewrite - Add passes to the optimized register allocation pipeline |
417 | /// after register allocation is complete, but before virtual registers are |
418 | /// rewritten to physical registers. |
419 | /// |
420 | /// These passes must preserve VirtRegMap and LiveIntervals, and when running |
421 | /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. |
422 | /// When these passes run, VirtRegMap contains legal physreg assignments for |
423 | /// all virtual registers. |
424 | /// |
425 | /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not |
426 | /// be honored. This is also not generally used for the fast variant, |
427 | /// where the allocation and rewriting are done in one pass. |
428 | virtual bool addPreRewrite() { |
429 | return false; |
430 | } |
431 | |
432 | /// addPostFastRegAllocRewrite - Add passes to the optimized register |
433 | /// allocation pipeline after fast register allocation is complete. |
434 | virtual bool addPostFastRegAllocRewrite() { return false; } |
435 | |
436 | /// Add passes to be run immediately after virtual registers are rewritten |
437 | /// to physical registers. |
438 | virtual void addPostRewrite() { } |
439 | |
440 | /// This method may be implemented by targets that want to run passes after |
441 | /// register allocation pass pipeline but before prolog-epilog insertion. |
442 | virtual void addPostRegAlloc() { } |
443 | |
444 | /// Add passes that optimize machine instructions after register allocation. |
445 | virtual void addMachineLateOptimization(); |
446 | |
447 | /// This method may be implemented by targets that want to run passes after |
448 | /// prolog-epilog insertion and before the second instruction scheduling pass. |
449 | virtual void addPreSched2() { } |
450 | |
451 | /// addGCPasses - Add late codegen passes that analyze code for garbage |
452 | /// collection. This should return true if GC info should be printed after |
453 | /// these passes. |
454 | virtual bool addGCPasses(); |
455 | |
456 | /// Add standard basic block placement passes. |
457 | virtual void addBlockPlacement(); |
458 | |
459 | /// This pass may be implemented by targets that want to run passes |
460 | /// immediately before machine code is emitted. |
461 | virtual void addPreEmitPass() { } |
462 | |
463 | /// This pass may be implemented by targets that want to run passes |
464 | /// immediately after basic block sections are assigned. |
465 | virtual void addPostBBSections() {} |
466 | |
467 | /// Targets may add passes immediately before machine code is emitted in this |
468 | /// callback. This is called even later than `addPreEmitPass`. |
469 | // FIXME: Rename `addPreEmitPass` to something more sensible given its actual |
470 | // position and remove the `2` suffix here as this callback is what |
471 | // `addPreEmitPass` *should* be but in reality isn't. |
472 | virtual void addPreEmitPass2() {} |
473 | |
474 | /// Utilities for targets to add passes to the pass manager. |
475 | /// |
476 | |
477 | /// Add a CodeGen pass at this point in the pipeline after checking overrides. |
478 | /// Return the pass that was added, or zero if no pass was added. |
479 | AnalysisID addPass(AnalysisID PassID); |
480 | |
481 | /// Add a pass to the PassManager if that pass is supposed to be run, as |
482 | /// determined by the StartAfter and StopAfter options. Takes ownership of the |
483 | /// pass. |
484 | void addPass(Pass *P); |
485 | |
486 | /// addMachinePasses helper to create the target-selected or overriden |
487 | /// regalloc pass. |
488 | virtual FunctionPass *createRegAllocPass(bool Optimized); |
489 | |
490 | /// Add core register allocator passes which do the actual register assignment |
491 | /// and rewriting. \returns true if any passes were added. |
492 | virtual bool addRegAssignAndRewriteFast(); |
493 | virtual bool addRegAssignAndRewriteOptimized(); |
494 | }; |
495 | |
496 | void registerCodeGenCallback(PassInstrumentationCallbacks &PIC, |
497 | LLVMTargetMachine &); |
498 | |
499 | } // end namespace llvm |
500 | |
501 | #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H |
502 | |