1//==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16#define LLVM_CODEGEN_TARGETREGISTERINFO_H
17
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/StringRef.h"
21#include "llvm/ADT/iterator_range.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/RegisterBank.h"
24#include "llvm/IR/CallingConv.h"
25#include "llvm/MC/LaneBitmask.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/MathExtras.h"
29#include "llvm/Support/Printable.h"
30#include <cassert>
31#include <cstdint>
32
33namespace llvm {
34
35class BitVector;
36class DIExpression;
37class LiveRegMatrix;
38class MachineFunction;
39class MachineInstr;
40class RegScavenger;
41class VirtRegMap;
42class LiveIntervals;
43class LiveInterval;
44
45class TargetRegisterClass {
46public:
47 using iterator = const MCPhysReg *;
48 using const_iterator = const MCPhysReg *;
49 using sc_iterator = const TargetRegisterClass* const *;
50
51 // Instance variables filled by tablegen, do not use!
52 const MCRegisterClass *MC;
53 const uint32_t *SubClassMask;
54 const uint16_t *SuperRegIndices;
55 const LaneBitmask LaneMask;
56 /// Classes with a higher priority value are assigned first by register
57 /// allocators using a greedy heuristic. The value is in the range [0,31].
58 const uint8_t AllocationPriority;
59
60 // Change allocation priority heuristic used by greedy.
61 const bool GlobalPriority;
62
63 /// Configurable target specific flags.
64 const uint8_t TSFlags;
65 /// Whether the class supports two (or more) disjunct subregister indices.
66 const bool HasDisjunctSubRegs;
67 /// Whether a combination of subregisters can cover every register in the
68 /// class. See also the CoveredBySubRegs description in Target.td.
69 const bool CoveredBySubRegs;
70 const sc_iterator SuperClasses;
71 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
72
73 /// Return the register class ID number.
74 unsigned getID() const { return MC->getID(); }
75
76 /// begin/end - Return all of the registers in this class.
77 ///
78 iterator begin() const { return MC->begin(); }
79 iterator end() const { return MC->end(); }
80
81 /// Return the number of registers in this class.
82 unsigned getNumRegs() const { return MC->getNumRegs(); }
83
84 ArrayRef<MCPhysReg> getRegisters() const {
85 return ArrayRef(begin(), getNumRegs());
86 }
87
88 /// Return the specified register in the class.
89 MCRegister getRegister(unsigned i) const {
90 return MC->getRegister(i);
91 }
92
93 /// Return true if the specified register is included in this register class.
94 /// This does not include virtual registers.
95 bool contains(Register Reg) const {
96 /// FIXME: Historically this function has returned false when given vregs
97 /// but it should probably only receive physical registers
98 if (!Reg.isPhysical())
99 return false;
100 return MC->contains(Reg: Reg.asMCReg());
101 }
102
103 /// Return true if both registers are in this class.
104 bool contains(Register Reg1, Register Reg2) const {
105 /// FIXME: Historically this function has returned false when given a vregs
106 /// but it should probably only receive physical registers
107 if (!Reg1.isPhysical() || !Reg2.isPhysical())
108 return false;
109 return MC->contains(Reg1: Reg1.asMCReg(), Reg2: Reg2.asMCReg());
110 }
111
112 /// Return the cost of copying a value between two registers in this class.
113 /// A negative number means the register class is very expensive
114 /// to copy e.g. status flag register classes.
115 int getCopyCost() const { return MC->getCopyCost(); }
116
117 /// Return true if this register class may be used to create virtual
118 /// registers.
119 bool isAllocatable() const { return MC->isAllocatable(); }
120
121 /// Return true if this register class has a defined BaseClassOrder.
122 bool isBaseClass() const { return MC->isBaseClass(); }
123
124 /// Return true if the specified TargetRegisterClass
125 /// is a proper sub-class of this TargetRegisterClass.
126 bool hasSubClass(const TargetRegisterClass *RC) const {
127 return RC != this && hasSubClassEq(RC);
128 }
129
130 /// Returns true if RC is a sub-class of or equal to this class.
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
132 unsigned ID = RC->getID();
133 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
134 }
135
136 /// Return true if the specified TargetRegisterClass is a
137 /// proper super-class of this TargetRegisterClass.
138 bool hasSuperClass(const TargetRegisterClass *RC) const {
139 return RC->hasSubClass(RC: this);
140 }
141
142 /// Returns true if RC is a super-class of or equal to this class.
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
144 return RC->hasSubClassEq(RC: this);
145 }
146
147 /// Returns a bit vector of subclasses, including this one.
148 /// The vector is indexed by class IDs.
149 ///
150 /// To use it, consider the returned array as a chunk of memory that
151 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
152 /// contains a bitset of the ID of the subclasses in big-endian style.
153
154 /// I.e., the representation of the memory from left to right at the
155 /// bit level looks like:
156 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
157 /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
158 /// Where the number represents the class ID and XXX bits that
159 /// should be ignored.
160 ///
161 /// See the implementation of hasSubClassEq for an example of how it
162 /// can be used.
163 const uint32_t *getSubClassMask() const {
164 return SubClassMask;
165 }
166
167 /// Returns a 0-terminated list of sub-register indices that project some
168 /// super-register class into this register class. The list has an entry for
169 /// each Idx such that:
170 ///
171 /// There exists SuperRC where:
172 /// For all Reg in SuperRC:
173 /// this->contains(Reg:Idx)
174 const uint16_t *getSuperRegIndices() const {
175 return SuperRegIndices;
176 }
177
178 /// Returns a NULL-terminated list of super-classes. The
179 /// classes are ordered by ID which is also a topological ordering from large
180 /// to small classes. The list does NOT include the current class.
181 sc_iterator getSuperClasses() const {
182 return SuperClasses;
183 }
184
185 /// Return true if this TargetRegisterClass is a subset
186 /// class of at least one other TargetRegisterClass.
187 bool isASubClass() const {
188 return SuperClasses[0] != nullptr;
189 }
190
191 /// Returns the preferred order for allocating registers from this register
192 /// class in MF. The raw order comes directly from the .td file and may
193 /// include reserved registers that are not allocatable.
194 /// Register allocators should also make sure to allocate
195 /// callee-saved registers only after all the volatiles are used. The
196 /// RegisterClassInfo class provides filtered allocation orders with
197 /// callee-saved registers moved to the end.
198 ///
199 /// The MachineFunction argument can be used to tune the allocatable
200 /// registers based on the characteristics of the function, subtarget, or
201 /// other criteria.
202 ///
203 /// By default, this method returns all registers in the class.
204 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
205 return OrderFunc ? OrderFunc(MF) : getRegisters();
206 }
207
208 /// Returns the combination of all lane masks of register in this class.
209 /// The lane masks of the registers are the combination of all lane masks
210 /// of their subregisters. Returns 1 if there are no subregisters.
211 LaneBitmask getLaneMask() const {
212 return LaneMask;
213 }
214};
215
216/// Extra information, not in MCRegisterDesc, about registers.
217/// These are used by codegen, not by MC.
218struct TargetRegisterInfoDesc {
219 const uint8_t *CostPerUse; // Extra cost of instructions using register.
220 unsigned NumCosts; // Number of cost values associated with each register.
221 const bool
222 *InAllocatableClass; // Register belongs to an allocatable regclass.
223};
224
225/// Each TargetRegisterClass has a per register weight, and weight
226/// limit which must be less than the limits of its pressure sets.
227struct RegClassWeight {
228 unsigned RegWeight;
229 unsigned WeightLimit;
230};
231
232/// TargetRegisterInfo base class - We assume that the target defines a static
233/// array of TargetRegisterDesc objects that represent all of the machine
234/// registers that the target has. As such, we simply have to track a pointer
235/// to this array so that we can turn register number into a register
236/// descriptor.
237///
238class TargetRegisterInfo : public MCRegisterInfo {
239public:
240 using regclass_iterator = const TargetRegisterClass * const *;
241 using vt_iterator = const MVT::SimpleValueType *;
242 struct RegClassInfo {
243 unsigned RegSize, SpillSize, SpillAlignment;
244 unsigned VTListOffset;
245 };
246private:
247 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
248 const char *const *SubRegIndexNames; // Names of subreg indexes.
249 // Pointer to array of lane masks, one per sub-reg index.
250 const LaneBitmask *SubRegIndexLaneMasks;
251
252 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
253 LaneBitmask CoveringLanes;
254 const RegClassInfo *const RCInfos;
255 const MVT::SimpleValueType *const RCVTLists;
256 unsigned HwMode;
257
258protected:
259 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
260 regclass_iterator RCB,
261 regclass_iterator RCE,
262 const char *const *SRINames,
263 const LaneBitmask *SRILaneMasks,
264 LaneBitmask CoveringLanes,
265 const RegClassInfo *const RCIs,
266 const MVT::SimpleValueType *const RCVTLists,
267 unsigned Mode = 0);
268 virtual ~TargetRegisterInfo();
269
270public:
271 /// Return the number of registers for the function. (may overestimate)
272 virtual unsigned getNumSupportedRegs(const MachineFunction &) const {
273 return getNumRegs();
274 }
275
276 // Register numbers can represent physical registers, virtual registers, and
277 // sometimes stack slots. The unsigned values are divided into these ranges:
278 //
279 // 0 Not a register, can be used as a sentinel.
280 // [1;2^30) Physical registers assigned by TableGen.
281 // [2^30;2^31) Stack slots. (Rarely used.)
282 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
283 //
284 // Further sentinels can be allocated from the small negative integers.
285 // DenseMapInfo<unsigned> uses -1u and -2u.
286
287 /// Return the size in bits of a register from class RC.
288 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const {
289 return TypeSize::getFixed(ExactSize: getRegClassInfo(RC).RegSize);
290 }
291
292 /// Return the size in bytes of the stack slot allocated to hold a spilled
293 /// copy of a register from class RC.
294 unsigned getSpillSize(const TargetRegisterClass &RC) const {
295 return getRegClassInfo(RC).SpillSize / 8;
296 }
297
298 /// Return the minimum required alignment in bytes for a spill slot for
299 /// a register of this class.
300 Align getSpillAlign(const TargetRegisterClass &RC) const {
301 return Align(getRegClassInfo(RC).SpillAlignment / 8);
302 }
303
304 /// Return true if the given TargetRegisterClass has the ValueType T.
305 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
306 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
307 if (MVT(*I) == T)
308 return true;
309 return false;
310 }
311
312 /// Return true if the given TargetRegisterClass is compatible with LLT T.
313 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const {
314 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
315 MVT VT(*I);
316 if (VT == MVT::Untyped)
317 return true;
318
319 if (LLT(VT) == T)
320 return true;
321 }
322 return false;
323 }
324
325 /// Loop over all of the value types that can be represented by values
326 /// in the given register class.
327 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
328 return &RCVTLists[getRegClassInfo(RC).VTListOffset];
329 }
330
331 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
332 vt_iterator I = legalclasstypes_begin(RC);
333 while (*I != MVT::Other)
334 ++I;
335 return I;
336 }
337
338 /// Returns the Register Class of a physical register of the given type,
339 /// picking the most sub register class of the right type that contains this
340 /// physreg.
341 const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
342 MVT VT = MVT::Other) const;
343
344 /// Returns the Register Class of a physical register of the given type,
345 /// picking the most sub register class of the right type that contains this
346 /// physreg. If there is no register class compatible with the given type,
347 /// returns nullptr.
348 const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
349 LLT Ty = LLT()) const;
350
351 /// Return the maximal subclass of the given register class that is
352 /// allocatable or NULL.
353 const TargetRegisterClass *
354 getAllocatableClass(const TargetRegisterClass *RC) const;
355
356 /// Returns a bitset indexed by register number indicating if a register is
357 /// allocatable or not. If a register class is specified, returns the subset
358 /// for the class.
359 BitVector getAllocatableSet(const MachineFunction &MF,
360 const TargetRegisterClass *RC = nullptr) const;
361
362 /// Get a list of cost values for all registers that correspond to the index
363 /// returned by RegisterCostTableIndex.
364 ArrayRef<uint8_t> getRegisterCosts(const MachineFunction &MF) const {
365 unsigned Idx = getRegisterCostTableIndex(MF);
366 unsigned NumRegs = getNumRegs();
367 assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
368
369 return ArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
370 }
371
372 /// Return true if the register is in the allocation of any register class.
373 bool isInAllocatableClass(MCRegister RegNo) const {
374 return InfoDesc->InAllocatableClass[RegNo];
375 }
376
377 /// Return the human-readable symbolic target-specific
378 /// name for the specified SubRegIndex.
379 const char *getSubRegIndexName(unsigned SubIdx) const {
380 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
381 "This is not a subregister index");
382 return SubRegIndexNames[SubIdx-1];
383 }
384
385 /// Return a bitmask representing the parts of a register that are covered by
386 /// SubIdx \see LaneBitmask.
387 ///
388 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
389 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
390 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
391 return SubRegIndexLaneMasks[SubIdx];
392 }
393
394 /// Try to find one or more subregister indexes to cover \p LaneMask.
395 ///
396 /// If this is possible, returns true and appends the best matching set of
397 /// indexes to \p Indexes. If this is not possible, returns false.
398 bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI,
399 const TargetRegisterClass *RC,
400 LaneBitmask LaneMask,
401 SmallVectorImpl<unsigned> &Indexes) const;
402
403 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
404 /// used to determine if sub-registers overlap - they can't be used to
405 /// determine if a set of sub-registers completely cover another
406 /// sub-register.
407 ///
408 /// The X86 general purpose registers have two lanes corresponding to the
409 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
410 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
411 /// sub_32bit sub-register.
412 ///
413 /// On the other hand, the ARM NEON lanes fully cover their registers: The
414 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
415 /// This is related to the CoveredBySubRegs property on register definitions.
416 ///
417 /// This function returns a bit mask of lanes that completely cover their
418 /// sub-registers. More precisely, given:
419 ///
420 /// Covering = getCoveringLanes();
421 /// MaskA = getSubRegIndexLaneMask(SubA);
422 /// MaskB = getSubRegIndexLaneMask(SubB);
423 ///
424 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
425 /// SubB.
426 LaneBitmask getCoveringLanes() const { return CoveringLanes; }
427
428 /// Returns true if the two registers are equal or alias each other.
429 /// The registers may be virtual registers.
430 bool regsOverlap(Register RegA, Register RegB) const {
431 if (RegA == RegB)
432 return true;
433 if (RegA.isPhysical() && RegB.isPhysical())
434 return MCRegisterInfo::regsOverlap(RegA: RegA.asMCReg(), RegB: RegB.asMCReg());
435 return false;
436 }
437
438 /// Returns true if Reg contains RegUnit.
439 bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
440 for (MCRegUnit Unit : regunits(Reg))
441 if (Register(Unit) == RegUnit)
442 return true;
443 return false;
444 }
445
446 /// Returns the original SrcReg unless it is the target of a copy-like
447 /// operation, in which case we chain backwards through all such operations
448 /// to the ultimate source register. If a physical register is encountered,
449 /// we stop the search.
450 virtual Register lookThruCopyLike(Register SrcReg,
451 const MachineRegisterInfo *MRI) const;
452
453 /// Find the original SrcReg unless it is the target of a copy-like operation,
454 /// in which case we chain backwards through all such operations to the
455 /// ultimate source register. If a physical register is encountered, we stop
456 /// the search.
457 /// Return the original SrcReg if all the definitions in the chain only have
458 /// one user and not a physical register.
459 virtual Register
460 lookThruSingleUseCopyChain(Register SrcReg,
461 const MachineRegisterInfo *MRI) const;
462
463 /// Return a null-terminated list of all of the callee-saved registers on
464 /// this target. The register should be in the order of desired callee-save
465 /// stack frame offset. The first register is closest to the incoming stack
466 /// pointer if stack grows down, and vice versa.
467 /// Notice: This function does not take into account disabled CSRs.
468 /// In most cases you will want to use instead the function
469 /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
470 virtual const MCPhysReg*
471 getCalleeSavedRegs(const MachineFunction *MF) const = 0;
472
473 /// Return a mask of call-preserved registers for the given calling convention
474 /// on the current function. The mask should include all call-preserved
475 /// aliases. This is used by the register allocator to determine which
476 /// registers can be live across a call.
477 ///
478 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
479 /// A set bit indicates that all bits of the corresponding register are
480 /// preserved across the function call. The bit mask is expected to be
481 /// sub-register complete, i.e. if A is preserved, so are all its
482 /// sub-registers.
483 ///
484 /// Bits are numbered from the LSB, so the bit for physical register Reg can
485 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
486 ///
487 /// A NULL pointer means that no register mask will be used, and call
488 /// instructions should use implicit-def operands to indicate call clobbered
489 /// registers.
490 ///
491 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF,
492 CallingConv::ID) const {
493 // The default mask clobbers everything. All targets should override.
494 return nullptr;
495 }
496
497 /// Return a register mask for the registers preserved by the unwinder,
498 /// or nullptr if no custom mask is needed.
499 virtual const uint32_t *
500 getCustomEHPadPreservedMask(const MachineFunction &MF) const {
501 return nullptr;
502 }
503
504 /// Return a register mask that clobbers everything.
505 virtual const uint32_t *getNoPreservedMask() const {
506 llvm_unreachable("target does not provide no preserved mask");
507 }
508
509 /// Return a list of all of the registers which are clobbered "inside" a call
510 /// to the given function. For example, these might be needed for PLT
511 /// sequences of long-branch veneers.
512 virtual ArrayRef<MCPhysReg>
513 getIntraCallClobberedRegs(const MachineFunction *MF) const {
514 return {};
515 }
516
517 /// Return true if all bits that are set in mask \p mask0 are also set in
518 /// \p mask1.
519 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
520
521 /// Return all the call-preserved register masks defined for this target.
522 virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
523 virtual ArrayRef<const char *> getRegMaskNames() const = 0;
524
525 /// Returns a bitset indexed by physical register number indicating if a
526 /// register is a special register that has particular uses and should be
527 /// considered unavailable at all times, e.g. stack pointer, return address.
528 /// A reserved register:
529 /// - is not allocatable
530 /// - is considered always live
531 /// - is ignored by liveness tracking
532 /// It is often necessary to reserve the super registers of a reserved
533 /// register as well, to avoid them getting allocated indirectly. You may use
534 /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
535 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
536
537 /// Returns either a string explaining why the given register is reserved for
538 /// this function, or an empty optional if no explanation has been written.
539 /// The absence of an explanation does not mean that the register is not
540 /// reserved (meaning, you should check that PhysReg is in fact reserved
541 /// before calling this).
542 virtual std::optional<std::string>
543 explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const {
544 return {};
545 }
546
547 /// Returns false if we can't guarantee that Physreg, specified as an IR asm
548 /// clobber constraint, will be preserved across the statement.
549 virtual bool isAsmClobberable(const MachineFunction &MF,
550 MCRegister PhysReg) const {
551 return true;
552 }
553
554 /// Returns true if PhysReg cannot be written to in inline asm statements.
555 virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF,
556 unsigned PhysReg) const {
557 return false;
558 }
559
560 /// Returns true if PhysReg is unallocatable and constant throughout the
561 /// function. Used by MachineRegisterInfo::isConstantPhysReg().
562 virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
563
564 /// Returns true if the register class is considered divergent.
565 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
566 return false;
567 }
568
569 /// Returns true if the register is considered uniform.
570 virtual bool isUniformReg(const MachineRegisterInfo &MRI,
571 const RegisterBankInfo &RBI, Register Reg) const {
572 return false;
573 }
574
575 /// Physical registers that may be modified within a function but are
576 /// guaranteed to be restored before any uses. This is useful for targets that
577 /// have call sequences where a GOT register may be updated by the caller
578 /// prior to a call and is guaranteed to be restored (also by the caller)
579 /// after the call.
580 virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
581 const MachineFunction &MF) const {
582 return false;
583 }
584
585 /// This is a wrapper around getCallPreservedMask().
586 /// Return true if the register is preserved after the call.
587 virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
588 const MachineFunction &MF) const;
589
590 /// Returns true if PhysReg can be used as an argument to a function.
591 virtual bool isArgumentRegister(const MachineFunction &MF,
592 MCRegister PhysReg) const {
593 return false;
594 }
595
596 /// Returns true if PhysReg is a fixed register.
597 virtual bool isFixedRegister(const MachineFunction &MF,
598 MCRegister PhysReg) const {
599 return false;
600 }
601
602 /// Returns true if PhysReg is a general purpose register.
603 virtual bool isGeneralPurposeRegister(const MachineFunction &MF,
604 MCRegister PhysReg) const {
605 return false;
606 }
607
608 /// Prior to adding the live-out mask to a stackmap or patchpoint
609 /// instruction, provide the target the opportunity to adjust it (mainly to
610 /// remove pseudo-registers that should be ignored).
611 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
612
613 /// Return a super-register of the specified register
614 /// Reg so its sub-register of index SubIdx is Reg.
615 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
616 const TargetRegisterClass *RC) const {
617 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC: RC->MC);
618 }
619
620 /// Return a subclass of the specified register
621 /// class A so that each register in it has a sub-register of the
622 /// specified sub-register index which is in the specified register class B.
623 ///
624 /// TableGen will synthesize missing A sub-classes.
625 virtual const TargetRegisterClass *
626 getMatchingSuperRegClass(const TargetRegisterClass *A,
627 const TargetRegisterClass *B, unsigned Idx) const;
628
629 // For a copy-like instruction that defines a register of class DefRC with
630 // subreg index DefSubReg, reading from another source with class SrcRC and
631 // subregister SrcSubReg return true if this is a preferable copy
632 // instruction or an earlier use should be used.
633 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
634 unsigned DefSubReg,
635 const TargetRegisterClass *SrcRC,
636 unsigned SrcSubReg) const;
637
638 /// Returns the largest legal sub-class of RC that
639 /// supports the sub-register index Idx.
640 /// If no such sub-class exists, return NULL.
641 /// If all registers in RC already have an Idx sub-register, return RC.
642 ///
643 /// TableGen generates a version of this function that is good enough in most
644 /// cases. Targets can override if they have constraints that TableGen
645 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
646 /// supported by the full GR32 register class in 64-bit mode, but only by the
647 /// GR32_ABCD regiister class in 32-bit mode.
648 ///
649 /// TableGen will synthesize missing RC sub-classes.
650 virtual const TargetRegisterClass *
651 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
652 assert(Idx == 0 && "Target has no sub-registers");
653 return RC;
654 }
655
656 /// Return a register class that can be used for a subregister copy from/into
657 /// \p SuperRC at \p SubRegIdx.
658 virtual const TargetRegisterClass *
659 getSubRegisterClass(const TargetRegisterClass *SuperRC,
660 unsigned SubRegIdx) const {
661 return nullptr;
662 }
663
664 /// Return the subregister index you get from composing
665 /// two subregister indices.
666 ///
667 /// The special null sub-register index composes as the identity.
668 ///
669 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
670 /// returns c. Note that composeSubRegIndices does not tell you about illegal
671 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
672 /// b, composeSubRegIndices doesn't tell you.
673 ///
674 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
675 /// ssub_0:S0 - ssub_3:S3 subregs.
676 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
677 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
678 if (!a) return b;
679 if (!b) return a;
680 return composeSubRegIndicesImpl(a, b);
681 }
682
683 /// Transforms a LaneMask computed for one subregister to the lanemask that
684 /// would have been computed when composing the subsubregisters with IdxA
685 /// first. @sa composeSubRegIndices()
686 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA,
687 LaneBitmask Mask) const {
688 if (!IdxA)
689 return Mask;
690 return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
691 }
692
693 /// Transform a lanemask given for a virtual register to the corresponding
694 /// lanemask before using subregister with index \p IdxA.
695 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
696 /// valie lane mask (no invalid bits set) the following holds:
697 /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
698 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
699 /// => X1 == Mask
700 LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA,
701 LaneBitmask LaneMask) const {
702 if (!IdxA)
703 return LaneMask;
704 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
705 }
706
707 /// Debugging helper: dump register in human readable form to dbgs() stream.
708 static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
709 const TargetRegisterInfo *TRI = nullptr);
710
711 /// Return target defined base register class for a physical register.
712 /// This is the register class with the lowest BaseClassOrder containing the
713 /// register.
714 /// Will be nullptr if the register is not in any base register class.
715 virtual const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const {
716 return nullptr;
717 }
718
719protected:
720 /// Overridden by TableGen in targets that have sub-registers.
721 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
722 llvm_unreachable("Target has no sub-registers");
723 }
724
725 /// Overridden by TableGen in targets that have sub-registers.
726 virtual LaneBitmask
727 composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const {
728 llvm_unreachable("Target has no sub-registers");
729 }
730
731 virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned,
732 LaneBitmask) const {
733 llvm_unreachable("Target has no sub-registers");
734 }
735
736 /// Return the register cost table index. This implementation is sufficient
737 /// for most architectures and can be overriden by targets in case there are
738 /// multiple cost values associated with each register.
739 virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
740 return 0;
741 }
742
743public:
744 /// Find a common super-register class if it exists.
745 ///
746 /// Find a register class, SuperRC and two sub-register indices, PreA and
747 /// PreB, such that:
748 ///
749 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
750 ///
751 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
752 ///
753 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
754 ///
755 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
756 /// requirements, and there is no register class with a smaller spill size
757 /// that satisfies the requirements.
758 ///
759 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
760 ///
761 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
762 /// that case, the returned register class will be a sub-class of the
763 /// corresponding argument register class.
764 ///
765 /// The function returns NULL if no register class can be found.
766 const TargetRegisterClass*
767 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
768 const TargetRegisterClass *RCB, unsigned SubB,
769 unsigned &PreA, unsigned &PreB) const;
770
771 //===--------------------------------------------------------------------===//
772 // Register Class Information
773 //
774protected:
775 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
776 return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
777 }
778
779public:
780 /// Register class iterators
781 regclass_iterator regclass_begin() const { return RegClassBegin; }
782 regclass_iterator regclass_end() const { return RegClassEnd; }
783 iterator_range<regclass_iterator> regclasses() const {
784 return make_range(x: regclass_begin(), y: regclass_end());
785 }
786
787 unsigned getNumRegClasses() const {
788 return (unsigned)(regclass_end()-regclass_begin());
789 }
790
791 /// Returns the register class associated with the enumeration value.
792 /// See class MCOperandInfo.
793 const TargetRegisterClass *getRegClass(unsigned i) const {
794 assert(i < getNumRegClasses() && "Register Class ID out of range");
795 return RegClassBegin[i];
796 }
797
798 /// Returns the name of the register class.
799 const char *getRegClassName(const TargetRegisterClass *Class) const {
800 return MCRegisterInfo::getRegClassName(Class: Class->MC);
801 }
802
803 /// Find the largest common subclass of A and B.
804 /// Return NULL if there is no common subclass.
805 const TargetRegisterClass *
806 getCommonSubClass(const TargetRegisterClass *A,
807 const TargetRegisterClass *B) const;
808
809 /// Returns a TargetRegisterClass used for pointer values.
810 /// If a target supports multiple different pointer register classes,
811 /// kind specifies which one is indicated.
812 virtual const TargetRegisterClass *
813 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
814 llvm_unreachable("Target didn't implement getPointerRegClass!");
815 }
816
817 /// Returns a legal register class to copy a register in the specified class
818 /// to or from. If it is possible to copy the register directly without using
819 /// a cross register class copy, return the specified RC. Returns NULL if it
820 /// is not possible to copy between two registers of the specified class.
821 virtual const TargetRegisterClass *
822 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
823 return RC;
824 }
825
826 /// Returns the largest super class of RC that is legal to use in the current
827 /// sub-target and has the same spill size.
828 /// The returned register class can be used to create virtual registers which
829 /// means that all its registers can be copied and spilled.
830 virtual const TargetRegisterClass *
831 getLargestLegalSuperClass(const TargetRegisterClass *RC,
832 const MachineFunction &) const {
833 /// The default implementation is very conservative and doesn't allow the
834 /// register allocator to inflate register classes.
835 return RC;
836 }
837
838 /// Return the register pressure "high water mark" for the specific register
839 /// class. The scheduler is in high register pressure mode (for the specific
840 /// register class) if it goes over the limit.
841 ///
842 /// Note: this is the old register pressure model that relies on a manually
843 /// specified representative register class per value type.
844 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
845 MachineFunction &MF) const {
846 return 0;
847 }
848
849 /// Return a heuristic for the machine scheduler to compare the profitability
850 /// of increasing one register pressure set versus another. The scheduler
851 /// will prefer increasing the register pressure of the set which returns
852 /// the largest value for this function.
853 virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
854 unsigned PSetID) const {
855 return PSetID;
856 }
857
858 /// Get the weight in units of pressure for this register class.
859 virtual const RegClassWeight &getRegClassWeight(
860 const TargetRegisterClass *RC) const = 0;
861
862 /// Returns size in bits of a phys/virtual/generic register.
863 TypeSize getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
864
865 /// Get the weight in units of pressure for this register unit.
866 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
867
868 /// Get the number of dimensions of register pressure.
869 virtual unsigned getNumRegPressureSets() const = 0;
870
871 /// Get the name of this register unit pressure set.
872 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
873
874 /// Get the register unit pressure limit for this dimension.
875 /// This limit must be adjusted dynamically for reserved registers.
876 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
877 unsigned Idx) const = 0;
878
879 /// Get the dimensions of register pressure impacted by this register class.
880 /// Returns a -1 terminated array of pressure set IDs.
881 virtual const int *getRegClassPressureSets(
882 const TargetRegisterClass *RC) const = 0;
883
884 /// Get the dimensions of register pressure impacted by this register unit.
885 /// Returns a -1 terminated array of pressure set IDs.
886 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
887
888 /// Get a list of 'hint' registers that the register allocator should try
889 /// first when allocating a physical register for the virtual register
890 /// VirtReg. These registers are effectively moved to the front of the
891 /// allocation order. If true is returned, regalloc will try to only use
892 /// hints to the greatest extent possible even if it means spilling.
893 ///
894 /// The Order argument is the allocation order for VirtReg's register class
895 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
896 /// come from Order, and they must not be reserved.
897 ///
898 /// The default implementation of this function will only add target
899 /// independent register allocation hints. Targets that override this
900 /// function should typically call this default implementation as well and
901 /// expect to see generic copy hints added.
902 virtual bool
903 getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
904 SmallVectorImpl<MCPhysReg> &Hints,
905 const MachineFunction &MF,
906 const VirtRegMap *VRM = nullptr,
907 const LiveRegMatrix *Matrix = nullptr) const;
908
909 /// A callback to allow target a chance to update register allocation hints
910 /// when a register is "changed" (e.g. coalesced) to another register.
911 /// e.g. On ARM, some virtual registers should target register pairs,
912 /// if one of pair is coalesced to another register, the allocation hint of
913 /// the other half of the pair should be changed to point to the new register.
914 virtual void updateRegAllocHint(Register Reg, Register NewReg,
915 MachineFunction &MF) const {
916 // Do nothing.
917 }
918
919 /// Allow the target to reverse allocation order of local live ranges. This
920 /// will generally allocate shorter local live ranges first. For targets with
921 /// many registers, this could reduce regalloc compile time by a large
922 /// factor. It is disabled by default for three reasons:
923 /// (1) Top-down allocation is simpler and easier to debug for targets that
924 /// don't benefit from reversing the order.
925 /// (2) Bottom-up allocation could result in poor evicition decisions on some
926 /// targets affecting the performance of compiled code.
927 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
928 virtual bool reverseLocalAssignment() const { return false; }
929
930 /// Allow the target to override the cost of using a callee-saved register for
931 /// the first time. Default value of 0 means we will use a callee-saved
932 /// register if it is available.
933 virtual unsigned getCSRFirstUseCost() const { return 0; }
934
935 /// Returns true if the target requires (and can make use of) the register
936 /// scavenger.
937 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
938 return false;
939 }
940
941 /// Returns true if the target wants to use frame pointer based accesses to
942 /// spill to the scavenger emergency spill slot.
943 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
944 return true;
945 }
946
947 /// Returns true if the target requires post PEI scavenging of registers for
948 /// materializing frame index constants.
949 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
950 return false;
951 }
952
953 /// Returns true if the target requires using the RegScavenger directly for
954 /// frame elimination despite using requiresFrameIndexScavenging.
955 virtual bool requiresFrameIndexReplacementScavenging(
956 const MachineFunction &MF) const {
957 return false;
958 }
959
960 /// Returns true if the target wants the LocalStackAllocation pass to be run
961 /// and virtual base registers used for more efficient stack access.
962 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
963 return false;
964 }
965
966 /// Return true if target has reserved a spill slot in the stack frame of
967 /// the given function for the specified register. e.g. On x86, if the frame
968 /// register is required, the first fixed stack object is reserved as its
969 /// spill slot. This tells PEI not to create a new stack frame
970 /// object for the given register. It should be called only after
971 /// determineCalleeSaves().
972 virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
973 int &FrameIdx) const {
974 return false;
975 }
976
977 /// Returns true if the live-ins should be tracked after register allocation.
978 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
979 return true;
980 }
981
982 /// True if the stack can be realigned for the target.
983 virtual bool canRealignStack(const MachineFunction &MF) const;
984
985 /// True if storage within the function requires the stack pointer to be
986 /// aligned more than the normal calling convention calls for.
987 virtual bool shouldRealignStack(const MachineFunction &MF) const;
988
989 /// True if stack realignment is required and still possible.
990 bool hasStackRealignment(const MachineFunction &MF) const {
991 return shouldRealignStack(MF) && canRealignStack(MF);
992 }
993
994 /// Get the offset from the referenced frame index in the instruction,
995 /// if there is one.
996 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
997 int Idx) const {
998 return 0;
999 }
1000
1001 /// Returns true if the instruction's frame index reference would be better
1002 /// served by a base register other than FP or SP.
1003 /// Used by LocalStackFrameAllocation to determine which frame index
1004 /// references it should create new base registers for.
1005 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1006 return false;
1007 }
1008
1009 /// Insert defining instruction(s) for a pointer to FrameIdx before
1010 /// insertion point I. Return materialized frame pointer.
1011 virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB,
1012 int FrameIdx,
1013 int64_t Offset) const {
1014 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
1015 "target");
1016 }
1017
1018 /// Resolve a frame index operand of an instruction
1019 /// to reference the indicated base register plus offset instead.
1020 virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
1021 int64_t Offset) const {
1022 llvm_unreachable("resolveFrameIndex does not exist on this target");
1023 }
1024
1025 /// Determine whether a given base register plus offset immediate is
1026 /// encodable to resolve a frame index.
1027 virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
1028 int64_t Offset) const {
1029 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
1030 }
1031
1032 /// Gets the DWARF expression opcodes for \p Offset.
1033 virtual void getOffsetOpcodes(const StackOffset &Offset,
1034 SmallVectorImpl<uint64_t> &Ops) const;
1035
1036 /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
1037 DIExpression *
1038 prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
1039 const StackOffset &Offset) const;
1040
1041 /// Spill the register so it can be used by the register scavenger.
1042 /// Return true if the register was spilled, false otherwise.
1043 /// If this function does not spill the register, the scavenger
1044 /// will instead spill it to the emergency spill slot.
1045 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
1046 MachineBasicBlock::iterator I,
1047 MachineBasicBlock::iterator &UseMI,
1048 const TargetRegisterClass *RC,
1049 Register Reg) const {
1050 return false;
1051 }
1052
1053 /// Process frame indices in reverse block order. This changes the behavior of
1054 /// the RegScavenger passed to eliminateFrameIndex. If this is true targets
1055 /// should scavengeRegisterBackwards in eliminateFrameIndex. New targets
1056 /// should prefer reverse scavenging behavior.
1057 /// TODO: Remove this when all targets return true.
1058 virtual bool eliminateFrameIndicesBackwards() const { return true; }
1059
1060 /// This method must be overriden to eliminate abstract frame indices from
1061 /// instructions which may use them. The instruction referenced by the
1062 /// iterator contains an MO_FrameIndex operand which must be eliminated by
1063 /// this method. This method may modify or replace the specified instruction,
1064 /// as long as it keeps the iterator pointing at the finished product.
1065 /// SPAdj is the SP adjustment due to call frame setup instruction.
1066 /// FIOperandNum is the FI operand number.
1067 /// Returns true if the current instruction was removed and the iterator
1068 /// is not longer valid
1069 virtual bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
1070 int SPAdj, unsigned FIOperandNum,
1071 RegScavenger *RS = nullptr) const = 0;
1072
1073 /// Return the assembly name for \p Reg.
1074 virtual StringRef getRegAsmName(MCRegister Reg) const {
1075 // FIXME: We are assuming that the assembly name is equal to the TableGen
1076 // name converted to lower case
1077 //
1078 // The TableGen name is the name of the definition for this register in the
1079 // target's tablegen files. For example, the TableGen name of
1080 // def EAX : Register <...>; is "EAX"
1081 return StringRef(getName(RegNo: Reg));
1082 }
1083
1084 //===--------------------------------------------------------------------===//
1085 /// Subtarget Hooks
1086
1087 /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1088 virtual bool shouldCoalesce(MachineInstr *MI,
1089 const TargetRegisterClass *SrcRC,
1090 unsigned SubReg,
1091 const TargetRegisterClass *DstRC,
1092 unsigned DstSubReg,
1093 const TargetRegisterClass *NewRC,
1094 LiveIntervals &LIS) const
1095 { return true; }
1096
1097 /// Region split has a high compile time cost especially for large live range.
1098 /// This method is used to decide whether or not \p VirtReg should
1099 /// go through this expensive splitting heuristic.
1100 virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1101 const LiveInterval &VirtReg) const;
1102
1103 /// Last chance recoloring has a high compile time cost especially for
1104 /// targets with a lot of registers.
1105 /// This method is used to decide whether or not \p VirtReg should
1106 /// go through this expensive heuristic.
1107 /// When this target hook is hit, by returning false, there is a high
1108 /// chance that the register allocation will fail altogether (usually with
1109 /// "ran out of registers").
1110 /// That said, this error usually points to another problem in the
1111 /// optimization pipeline.
1112 virtual bool
1113 shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF,
1114 const LiveInterval &VirtReg) const {
1115 return true;
1116 }
1117
1118 /// Deferred spilling delays the spill insertion of a virtual register
1119 /// after every other allocation. By deferring the spilling, it is
1120 /// sometimes possible to eliminate that spilling altogether because
1121 /// something else could have been eliminated, thus leaving some space
1122 /// for the virtual register.
1123 /// However, this comes with a compile time impact because it adds one
1124 /// more stage to the greedy register allocator.
1125 /// This method is used to decide whether \p VirtReg should use the deferred
1126 /// spilling stage instead of being spilled right away.
1127 virtual bool
1128 shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF,
1129 const LiveInterval &VirtReg) const {
1130 return false;
1131 }
1132
1133 /// When prioritizing live ranges in register allocation, if this hook returns
1134 /// true then the AllocationPriority of the register class will be treated as
1135 /// more important than whether the range is local to a basic block or global.
1136 virtual bool
1137 regClassPriorityTrumpsGlobalness(const MachineFunction &MF) const {
1138 return false;
1139 }
1140
1141 //===--------------------------------------------------------------------===//
1142 /// Debug information queries.
1143
1144 /// getFrameRegister - This method should return the register used as a base
1145 /// for values allocated in the current stack frame.
1146 virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1147
1148 /// Mark a register and all its aliases as reserved in the given set.
1149 void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const;
1150
1151 /// Returns true if for every register in the set all super registers are part
1152 /// of the set as well.
1153 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
1154 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1155
1156 virtual const TargetRegisterClass *
1157 getConstrainedRegClassForOperand(const MachineOperand &MO,
1158 const MachineRegisterInfo &MRI) const {
1159 return nullptr;
1160 }
1161
1162 /// Returns the physical register number of sub-register "Index"
1163 /// for physical register RegNo. Return zero if the sub-register does not
1164 /// exist.
1165 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1166 return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1167 }
1168
1169 /// Some targets have non-allocatable registers that aren't technically part
1170 /// of the explicit callee saved register list, but should be handled as such
1171 /// in certain cases.
1172 virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const {
1173 return false;
1174 }
1175};
1176
1177//===----------------------------------------------------------------------===//
1178// SuperRegClassIterator
1179//===----------------------------------------------------------------------===//
1180//
1181// Iterate over the possible super-registers for a given register class. The
1182// iterator will visit a list of pairs (Idx, Mask) corresponding to the
1183// possible classes of super-registers.
1184//
1185// Each bit mask will have at least one set bit, and each set bit in Mask
1186// corresponds to a SuperRC such that:
1187//
1188// For all Reg in SuperRC: Reg:Idx is in RC.
1189//
1190// The iterator can include (O, RC->getSubClassMask()) as the first entry which
1191// also satisfies the above requirement, assuming Reg:0 == Reg.
1192//
1193class SuperRegClassIterator {
1194 const unsigned RCMaskWords;
1195 unsigned SubReg = 0;
1196 const uint16_t *Idx;
1197 const uint32_t *Mask;
1198
1199public:
1200 /// Create a SuperRegClassIterator that visits all the super-register classes
1201 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1202 SuperRegClassIterator(const TargetRegisterClass *RC,
1203 const TargetRegisterInfo *TRI,
1204 bool IncludeSelf = false)
1205 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1206 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1207 if (!IncludeSelf)
1208 ++*this;
1209 }
1210
1211 /// Returns true if this iterator is still pointing at a valid entry.
1212 bool isValid() const { return Idx; }
1213
1214 /// Returns the current sub-register index.
1215 unsigned getSubReg() const { return SubReg; }
1216
1217 /// Returns the bit mask of register classes that getSubReg() projects into
1218 /// RC.
1219 /// See TargetRegisterClass::getSubClassMask() for how to use it.
1220 const uint32_t *getMask() const { return Mask; }
1221
1222 /// Advance iterator to the next entry.
1223 void operator++() {
1224 assert(isValid() && "Cannot move iterator past end.");
1225 Mask += RCMaskWords;
1226 SubReg = *Idx++;
1227 if (!SubReg)
1228 Idx = nullptr;
1229 }
1230};
1231
1232//===----------------------------------------------------------------------===//
1233// BitMaskClassIterator
1234//===----------------------------------------------------------------------===//
1235/// This class encapuslates the logic to iterate over bitmask returned by
1236/// the various RegClass related APIs.
1237/// E.g., this class can be used to iterate over the subclasses provided by
1238/// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1239class BitMaskClassIterator {
1240 /// Total number of register classes.
1241 const unsigned NumRegClasses;
1242 /// Base index of CurrentChunk.
1243 /// In other words, the number of bit we read to get at the
1244 /// beginning of that chunck.
1245 unsigned Base = 0;
1246 /// Adjust base index of CurrentChunk.
1247 /// Base index + how many bit we read within CurrentChunk.
1248 unsigned Idx = 0;
1249 /// Current register class ID.
1250 unsigned ID = 0;
1251 /// Mask we are iterating over.
1252 const uint32_t *Mask;
1253 /// Current chunk of the Mask we are traversing.
1254 uint32_t CurrentChunk;
1255
1256 /// Move ID to the next set bit.
1257 void moveToNextID() {
1258 // If the current chunk of memory is empty, move to the next one,
1259 // while making sure we do not go pass the number of register
1260 // classes.
1261 while (!CurrentChunk) {
1262 // Move to the next chunk.
1263 Base += 32;
1264 if (Base >= NumRegClasses) {
1265 ID = NumRegClasses;
1266 return;
1267 }
1268 CurrentChunk = *++Mask;
1269 Idx = Base;
1270 }
1271 // Otherwise look for the first bit set from the right
1272 // (representation of the class ID is big endian).
1273 // See getSubClassMask for more details on the representation.
1274 unsigned Offset = llvm::countr_zero(Val: CurrentChunk);
1275 // Add the Offset to the adjusted base number of this chunk: Idx.
1276 // This is the ID of the register class.
1277 ID = Idx + Offset;
1278
1279 // Consume the zeros, if any, and the bit we just read
1280 // so that we are at the right spot for the next call.
1281 // Do not do Offset + 1 because Offset may be 31 and 32
1282 // will be UB for the shift, though in that case we could
1283 // have make the chunk being equal to 0, but that would
1284 // have introduced a if statement.
1285 moveNBits(NumBits: Offset);
1286 moveNBits(NumBits: 1);
1287 }
1288
1289 /// Move \p NumBits Bits forward in CurrentChunk.
1290 void moveNBits(unsigned NumBits) {
1291 assert(NumBits < 32 && "Undefined behavior spotted!");
1292 // Consume the bit we read for the next call.
1293 CurrentChunk >>= NumBits;
1294 // Adjust the base for the chunk.
1295 Idx += NumBits;
1296 }
1297
1298public:
1299 /// Create a BitMaskClassIterator that visits all the register classes
1300 /// represented by \p Mask.
1301 ///
1302 /// \pre \p Mask != nullptr
1303 BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
1304 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1305 // Move to the first ID.
1306 moveToNextID();
1307 }
1308
1309 /// Returns true if this iterator is still pointing at a valid entry.
1310 bool isValid() const { return getID() != NumRegClasses; }
1311
1312 /// Returns the current register class ID.
1313 unsigned getID() const { return ID; }
1314
1315 /// Advance iterator to the next entry.
1316 void operator++() {
1317 assert(isValid() && "Cannot move iterator past end.");
1318 moveToNextID();
1319 }
1320};
1321
1322// This is useful when building IndexedMaps keyed on virtual registers
1323struct VirtReg2IndexFunctor {
1324 using argument_type = Register;
1325 unsigned operator()(Register Reg) const {
1326 return Register::virtReg2Index(Reg);
1327 }
1328};
1329
1330/// Prints virtual and physical registers with or without a TRI instance.
1331///
1332/// The format is:
1333/// %noreg - NoRegister
1334/// %5 - a virtual register.
1335/// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1336/// %eax - a physical register
1337/// %physreg17 - a physical register when no TRI instance given.
1338///
1339/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1340Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1341 unsigned SubIdx = 0,
1342 const MachineRegisterInfo *MRI = nullptr);
1343
1344/// Create Printable object to print register units on a \ref raw_ostream.
1345///
1346/// Register units are named after their root registers:
1347///
1348/// al - Single root.
1349/// fp0~st7 - Dual roots.
1350///
1351/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1352Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1353
1354/// Create Printable object to print virtual registers and physical
1355/// registers on a \ref raw_ostream.
1356Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1357
1358/// Create Printable object to print register classes or register banks
1359/// on a \ref raw_ostream.
1360Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1361 const TargetRegisterInfo *TRI);
1362
1363} // end namespace llvm
1364
1365#endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
1366

source code of llvm/include/llvm/CodeGen/TargetRegisterInfo.h