1//===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the subtarget options of a Target machine.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
14#define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/CodeGen/MacroFusion.h"
20#include "llvm/CodeGen/PBQPRAConstraint.h"
21#include "llvm/CodeGen/SchedulerRegistry.h"
22#include "llvm/IR/GlobalValue.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/CodeGen.h"
25#include <memory>
26#include <vector>
27
28namespace llvm {
29
30class APInt;
31class MachineFunction;
32class ScheduleDAGMutation;
33class CallLowering;
34class GlobalValue;
35class InlineAsmLowering;
36class InstrItineraryData;
37struct InstrStage;
38class InstructionSelector;
39class LegalizerInfo;
40class MachineInstr;
41struct MachineSchedPolicy;
42struct MCReadAdvanceEntry;
43struct MCWriteLatencyEntry;
44struct MCWriteProcResEntry;
45class RegisterBankInfo;
46class SDep;
47class SelectionDAGTargetInfo;
48class SUnit;
49class TargetFrameLowering;
50class TargetInstrInfo;
51class TargetLowering;
52class TargetRegisterClass;
53class TargetRegisterInfo;
54class TargetSchedModel;
55class Triple;
56
57//===----------------------------------------------------------------------===//
58///
59/// TargetSubtargetInfo - Generic base class for all target subtargets. All
60/// Target-specific options that control code generation and printing should
61/// be exposed through a TargetSubtargetInfo-derived class.
62///
63class TargetSubtargetInfo : public MCSubtargetInfo {
64protected: // Can only create subclasses...
65 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
66 StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
67 ArrayRef<SubtargetSubTypeKV> PD,
68 const MCWriteProcResEntry *WPR,
69 const MCWriteLatencyEntry *WL,
70 const MCReadAdvanceEntry *RA, const InstrStage *IS,
71 const unsigned *OC, const unsigned *FP);
72
73public:
74 // AntiDepBreakMode - Type of anti-dependence breaking that should
75 // be performed before post-RA scheduling.
76 using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
77 using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
78
79 TargetSubtargetInfo() = delete;
80 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
81 TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
82 ~TargetSubtargetInfo() override;
83
84 virtual bool isXRaySupported() const { return false; }
85
86 // Interfaces to the major aspects of target machine information:
87 //
88 // -- Instruction opcode and operand information
89 // -- Pipelines and scheduling information
90 // -- Stack frame information
91 // -- Selection DAG lowering information
92 // -- Call lowering information
93 //
94 // N.B. These objects may change during compilation. It's not safe to cache
95 // them between functions.
96 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
97 virtual const TargetFrameLowering *getFrameLowering() const {
98 return nullptr;
99 }
100 virtual const TargetLowering *getTargetLowering() const { return nullptr; }
101 virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const {
102 return nullptr;
103 }
104 virtual const CallLowering *getCallLowering() const { return nullptr; }
105
106 virtual const InlineAsmLowering *getInlineAsmLowering() const {
107 return nullptr;
108 }
109
110 // FIXME: This lets targets specialize the selector by subtarget (which lets
111 // us do things like a dedicated avx512 selector). However, we might want
112 // to also specialize selectors by MachineFunction, which would let us be
113 // aware of optsize/optnone and such.
114 virtual InstructionSelector *getInstructionSelector() const {
115 return nullptr;
116 }
117
118 /// Target can subclass this hook to select a different DAG scheduler.
119 virtual RegisterScheduler::FunctionPassCtor
120 getDAGScheduler(CodeGenOptLevel) const {
121 return nullptr;
122 }
123
124 virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
125
126 /// getRegisterInfo - If register information is available, return it. If
127 /// not, return null.
128 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
129
130 /// If the information for the register banks is available, return it.
131 /// Otherwise return nullptr.
132 virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
133
134 /// getInstrItineraryData - Returns instruction itinerary data for the target
135 /// or specific subtarget.
136 virtual const InstrItineraryData *getInstrItineraryData() const {
137 return nullptr;
138 }
139
140 /// Resolve a SchedClass at runtime, where SchedClass identifies an
141 /// MCSchedClassDesc with the isVariant property. This may return the ID of
142 /// another variant SchedClass, but repeated invocation must quickly terminate
143 /// in a nonvariant SchedClass.
144 virtual unsigned resolveSchedClass(unsigned SchedClass,
145 const MachineInstr *MI,
146 const TargetSchedModel *SchedModel) const {
147 return 0;
148 }
149
150 /// Returns true if MI is a dependency breaking zero-idiom instruction for the
151 /// subtarget.
152 ///
153 /// This function also sets bits in Mask related to input operands that
154 /// are not in a data dependency relationship. There is one bit for each
155 /// machine operand; implicit operands follow explicit operands in the bit
156 /// representation used for Mask. An empty (i.e. a mask with all bits
157 /// cleared) means: data dependencies are "broken" for all the explicit input
158 /// machine operands of MI.
159 virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
160 return false;
161 }
162
163 /// Returns true if MI is a dependency breaking instruction for the subtarget.
164 ///
165 /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
166 /// all dependency breaking instructions (i.e. not just zero-idioms).
167 ///
168 /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
169 /// (See method `isZeroIdiom` for a detailed description of Mask).
170 virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
171 return isZeroIdiom(MI, Mask);
172 }
173
174 /// Returns true if MI is a candidate for move elimination.
175 ///
176 /// A candidate for move elimination may be optimized out at register renaming
177 /// stage. Subtargets can specify the set of optimizable moves by
178 /// instantiating tablegen class `IsOptimizableRegisterMove` (see
179 /// llvm/Target/TargetInstrPredicate.td).
180 ///
181 /// SubtargetEmitter is responsible for processing all the definitions of class
182 /// IsOptimizableRegisterMove, and auto-generate an override for this method.
183 virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
184 return false;
185 }
186
187 /// True if the subtarget should run MachineScheduler after aggressive
188 /// coalescing.
189 ///
190 /// This currently replaces the SelectionDAG scheduler with the "source" order
191 /// scheduler (though see below for an option to turn this off and use the
192 /// TargetLowering preference). It does not yet disable the postRA scheduler.
193 virtual bool enableMachineScheduler() const;
194
195 /// True if the machine scheduler should disable the TLI preference
196 /// for preRA scheduling with the source level scheduler.
197 virtual bool enableMachineSchedDefaultSched() const { return true; }
198
199 /// True if the subtarget should run MachinePipeliner
200 virtual bool enableMachinePipeliner() const { return true; };
201
202 /// True if the subtarget should enable joining global copies.
203 ///
204 /// By default this is enabled if the machine scheduler is enabled, but
205 /// can be overridden.
206 virtual bool enableJoinGlobalCopies() const;
207
208 /// True if the subtarget should run a scheduler after register allocation.
209 ///
210 /// By default this queries the PostRAScheduling bit in the scheduling model
211 /// which is the preferred way to influence this.
212 virtual bool enablePostRAScheduler() const;
213
214 /// True if the subtarget should run a machine scheduler after register
215 /// allocation.
216 virtual bool enablePostRAMachineScheduler() const;
217
218 /// True if the subtarget should run the atomic expansion pass.
219 virtual bool enableAtomicExpand() const;
220
221 /// True if the subtarget should run the indirectbr expansion pass.
222 virtual bool enableIndirectBrExpand() const;
223
224 /// Override generic scheduling policy within a region.
225 ///
226 /// This is a convenient way for targets that don't provide any custom
227 /// scheduling heuristics (no custom MachineSchedStrategy) to make
228 /// changes to the generic scheduling policy.
229 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
230 unsigned NumRegionInstrs) const {}
231
232 // Perform target-specific adjustments to the latency of a schedule
233 // dependency.
234 // If a pair of operands is associated with the schedule dependency, DefOpIdx
235 // and UseOpIdx are the indices of the operands in Def and Use, respectively.
236 // Otherwise, either may be -1.
237 virtual void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use,
238 int UseOpIdx, SDep &Dep) const {}
239
240 // For use with PostRAScheduling: get the anti-dependence breaking that should
241 // be performed before post-RA scheduling.
242 virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
243
244 // For use with PostRAScheduling: in CriticalPathRCs, return any register
245 // classes that should only be considered for anti-dependence breaking if they
246 // are on the critical path.
247 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
248 return CriticalPathRCs.clear();
249 }
250
251 // Provide an ordered list of schedule DAG mutations for the post-RA
252 // scheduler.
253 virtual void getPostRAMutations(
254 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
255 }
256
257 // Provide an ordered list of schedule DAG mutations for the machine
258 // pipeliner.
259 virtual void getSMSMutations(
260 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
261 }
262
263 /// Default to DFA for resource management, return false when target will use
264 /// ProcResource in InstrSchedModel instead.
265 virtual bool useDFAforSMS() const { return true; }
266
267 // For use with PostRAScheduling: get the minimum optimization level needed
268 // to enable post-RA scheduling.
269 virtual CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const {
270 return CodeGenOptLevel::Default;
271 }
272
273 /// True if the subtarget should run the local reassignment
274 /// heuristic of the register allocator.
275 /// This heuristic may be compile time intensive, \p OptLevel provides
276 /// a finer grain to tune the register allocator.
277 virtual bool enableRALocalReassignment(CodeGenOptLevel OptLevel) const;
278
279 /// Enable use of alias analysis during code generation (during MI
280 /// scheduling, DAGCombine, etc.).
281 virtual bool useAA() const;
282
283 /// \brief Sink addresses into blocks using GEP instructions rather than
284 /// pointer casts and arithmetic.
285 virtual bool addrSinkUsingGEPs() const {
286 return useAA();
287 }
288
289 /// Enable the use of the early if conversion pass.
290 virtual bool enableEarlyIfConversion() const { return false; }
291
292 /// Return PBQPConstraint(s) for the target.
293 ///
294 /// Override to provide custom PBQP constraints.
295 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
296 return nullptr;
297 }
298
299 /// Enable tracking of subregister liveness in register allocator.
300 /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
301 /// possible.
302 virtual bool enableSubRegLiveness() const { return false; }
303
304 /// This is called after a .mir file was loaded.
305 virtual void mirFileLoaded(MachineFunction &MF) const;
306
307 /// True if the register allocator should use the allocation orders exactly as
308 /// written in the tablegen descriptions, false if it should allocate
309 /// the specified physical register later if is it callee-saved.
310 virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
311 unsigned PhysReg) const {
312 return false;
313 }
314
315 /// Classify a global function reference. This mainly used to fetch target
316 /// special flags for lowering a function address. For example mark a function
317 /// call should be plt or pc-related addressing.
318 virtual unsigned char
319 classifyGlobalFunctionReference(const GlobalValue *GV) const {
320 return 0;
321 }
322
323 /// Enable spillage copy elimination in MachineCopyPropagation pass. This
324 /// helps removing redundant copies generated by register allocator when
325 /// handling complex eviction chains.
326 virtual bool enableSpillageCopyElimination() const { return false; }
327
328 /// Get the list of MacroFusion predicates.
329 virtual std::vector<MacroFusionPredTy> getMacroFusions() const { return {}; };
330};
331
332} // end namespace llvm
333
334#endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H
335

source code of llvm/include/llvm/CodeGen/TargetSubtargetInfo.h