1//===-- IR/VPIntrinsics.def - Describes llvm.vp.* Intrinsics -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains descriptions of the various Vector Predication intrinsics.
10// This is used as a central place for enumerating the different instructions
11// and should eventually be the place to put comments about the instructions.
12//
13//===----------------------------------------------------------------------===//
14
15// NOTE: NO INCLUDE GUARD DESIRED!
16
17// Provide definitions of macros so that users of this file do not have to
18// define everything to use it...
19//
20// Register a VP intrinsic and begin its property scope.
21// All VP intrinsic scopes are top level, ie it is illegal to place a
22// BEGIN_REGISTER_VP_INTRINSIC within a VP intrinsic scope.
23// \p VPID The VP intrinsic id.
24// \p MASKPOS The mask operand position.
25// \p EVLPOS The explicit vector length operand position.
26#ifndef BEGIN_REGISTER_VP_INTRINSIC
27#define BEGIN_REGISTER_VP_INTRINSIC(VPID, MASKPOS, EVLPOS)
28#endif
29
30// End the property scope of a VP intrinsic.
31#ifndef END_REGISTER_VP_INTRINSIC
32#define END_REGISTER_VP_INTRINSIC(VPID)
33#endif
34
35// Register a new VP SDNode and begin its property scope.
36// When the SDNode scope is nested within a VP intrinsic scope, it is implicitly registered as the canonical SDNode for this VP intrinsic.
37// There is one VP intrinsic that maps directly to one SDNode that goes by the
38// same name. Since the operands are also the same, we open the property
39// scopes for both the VPIntrinsic and the SDNode at once.
40// \p SDOPC The SelectionDAG Node id (eg VP_ADD).
41// \p LEGALPOS The operand position of the SDNode that is used for legalizing
42// this SDNode. This can be `-1`, in which case the return type of
43// the SDNode is used.
44// \p TDNAME The name of the TableGen definition of this SDNode.
45// \p MASKPOS The mask operand position.
46// \p EVLPOS The explicit vector length operand position.
47#ifndef BEGIN_REGISTER_VP_SDNODE
48#define BEGIN_REGISTER_VP_SDNODE(SDOPC, LEGALPOS, TDNAME, MASKPOS, EVLPOS)
49#endif
50
51// End the property scope of a new VP SDNode.
52#ifndef END_REGISTER_VP_SDNODE
53#define END_REGISTER_VP_SDNODE(SDOPC)
54#endif
55
56// Helper macros for the common "1:1 - Intrinsic : SDNode" case.
57//
58// There is one VP intrinsic that maps directly to one SDNode that goes by the
59// same name. Since the operands are also the same, we open the property
60// scopes for both the VPIntrinsic and the SDNode at once.
61//
62// \p INTRIN The canonical name (eg `vp_add`, which at the same time is the
63// name of the intrinsic and the TableGen def of the SDNode).
64// \p MASKPOS The mask operand position.
65// \p EVLPOS The explicit vector length operand position.
66// \p SDOPC The SelectionDAG Node id (eg VP_ADD).
67// \p LEGALPOS The operand position of the SDNode that is used for legalizing
68// this SDNode. This can be `-1`, in which case the return type of
69// the SDNode is used.
70#define BEGIN_REGISTER_VP(INTRIN, MASKPOS, EVLPOS, SDOPC, LEGALPOS) \
71BEGIN_REGISTER_VP_INTRINSIC(INTRIN, MASKPOS, EVLPOS) \
72BEGIN_REGISTER_VP_SDNODE(SDOPC, LEGALPOS, INTRIN, MASKPOS, EVLPOS)
73
74#define END_REGISTER_VP(INTRIN, SDOPC) \
75END_REGISTER_VP_INTRINSIC(INTRIN) \
76END_REGISTER_VP_SDNODE(SDOPC)
77
78
79// The following macros attach properties to the scope they are placed in. This
80// assigns the property to the VP Intrinsic and/or SDNode that belongs to the
81// scope.
82//
83// Property Macros {
84
85// The intrinsic and/or SDNode has the same function as this LLVM IR Opcode.
86// \p OPC The standard IR opcode.
87#ifndef HANDLE_VP_TO_OPC
88#define HANDLE_VP_TO_OPC(OPC)
89#endif
90
91/// } Property Macros
92
93///// Integer Arithmetic {
94
95// Specialized helper macro for integer binary operators (%x, %y, %mask, %evl).
96#ifdef HELPER_REGISTER_BINARY_INT_VP
97#error "The internal helper macro HELPER_REGISTER_BINARY_INT_VP is already defined!"
98#endif
99#define HELPER_REGISTER_BINARY_INT_VP(INTRIN, SDOPC, OPC) \
100BEGIN_REGISTER_VP(INTRIN, 2, 3, SDOPC, -1) \
101HANDLE_VP_TO_OPC(OPC) \
102END_REGISTER_VP(INTRIN, SDOPC)
103
104
105
106// llvm.vp.add(x,y,mask,vlen)
107HELPER_REGISTER_BINARY_INT_VP(vp_add, VP_ADD, Add)
108
109// llvm.vp.and(x,y,mask,vlen)
110HELPER_REGISTER_BINARY_INT_VP(vp_and, VP_AND, And)
111
112// llvm.vp.ashr(x,y,mask,vlen)
113HELPER_REGISTER_BINARY_INT_VP(vp_ashr, VP_ASHR, AShr)
114
115// llvm.vp.lshr(x,y,mask,vlen)
116HELPER_REGISTER_BINARY_INT_VP(vp_lshr, VP_LSHR, LShr)
117
118// llvm.vp.mul(x,y,mask,vlen)
119HELPER_REGISTER_BINARY_INT_VP(vp_mul, VP_MUL, Mul)
120
121// llvm.vp.or(x,y,mask,vlen)
122HELPER_REGISTER_BINARY_INT_VP(vp_or, VP_OR, Or)
123
124// llvm.vp.sdiv(x,y,mask,vlen)
125HELPER_REGISTER_BINARY_INT_VP(vp_sdiv, VP_SDIV, SDiv)
126
127// llvm.vp.shl(x,y,mask,vlen)
128HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl)
129
130// llvm.vp.srem(x,y,mask,vlen)
131HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem)
132
133// llvm.vp.sub(x,y,mask,vlen)
134HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub)
135
136// llvm.vp.udiv(x,y,mask,vlen)
137HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv)
138
139// llvm.vp.urem(x,y,mask,vlen)
140HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem)
141
142// llvm.vp.xor(x,y,mask,vlen)
143HELPER_REGISTER_BINARY_INT_VP(vp_xor, VP_XOR, Xor)
144
145#undef HELPER_REGISTER_BINARY_INT_VP
146
147///// } Integer Arithmetic
148
149
150#undef BEGIN_REGISTER_VP
151#undef BEGIN_REGISTER_VP_INTRINSIC
152#undef BEGIN_REGISTER_VP_SDNODE
153#undef END_REGISTER_VP
154#undef END_REGISTER_VP_INTRINSIC
155#undef END_REGISTER_VP_SDNODE
156#undef HANDLE_VP_TO_OPC
157