1//===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes an abstract interface used to get information about a
10// target machines register file. This information is used for a variety of
11// purposed, especially register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCREGISTERINFO_H
16#define LLVM_MC_MCREGISTERINFO_H
17
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/iterator.h"
20#include "llvm/ADT/iterator_range.h"
21#include "llvm/MC/LaneBitmask.h"
22#include "llvm/MC/MCRegister.h"
23#include <cassert>
24#include <cstdint>
25#include <iterator>
26#include <utility>
27
28namespace llvm {
29
30class MCRegUnitIterator;
31class MCSubRegIterator;
32class MCSuperRegIterator;
33
34/// MCRegisterClass - Base class of TargetRegisterClass.
35class MCRegisterClass {
36public:
37 using iterator = const MCPhysReg*;
38 using const_iterator = const MCPhysReg*;
39
40 const iterator RegsBegin;
41 const uint8_t *const RegSet;
42 const uint32_t NameIdx;
43 const uint16_t RegsSize;
44 const uint16_t RegSetSize;
45 const uint16_t ID;
46 const uint16_t RegSizeInBits;
47 const int8_t CopyCost;
48 const bool Allocatable;
49 const bool BaseClass;
50
51 /// getID() - Return the register class ID number.
52 ///
53 unsigned getID() const { return ID; }
54
55 /// begin/end - Return all of the registers in this class.
56 ///
57 iterator begin() const { return RegsBegin; }
58 iterator end() const { return RegsBegin + RegsSize; }
59
60 /// getNumRegs - Return the number of registers in this class.
61 ///
62 unsigned getNumRegs() const { return RegsSize; }
63
64 /// getRegister - Return the specified register in the class.
65 ///
66 unsigned getRegister(unsigned i) const {
67 assert(i < getNumRegs() && "Register number out of range!");
68 return RegsBegin[i];
69 }
70
71 /// contains - Return true if the specified register is included in this
72 /// register class. This does not include virtual registers.
73 bool contains(MCRegister Reg) const {
74 unsigned RegNo = unsigned(Reg);
75 unsigned InByte = RegNo % 8;
76 unsigned Byte = RegNo / 8;
77 if (Byte >= RegSetSize)
78 return false;
79 return (RegSet[Byte] & (1 << InByte)) != 0;
80 }
81
82 /// contains - Return true if both registers are in this class.
83 bool contains(MCRegister Reg1, MCRegister Reg2) const {
84 return contains(Reg: Reg1) && contains(Reg: Reg2);
85 }
86
87 /// Return the size of the physical register in bits if we are able to
88 /// determine it. This always returns zero for registers of targets that use
89 /// HW modes, as we need more information to determine the size of registers
90 /// in such cases. Use TargetRegisterInfo to cover them.
91 unsigned getSizeInBits() const { return RegSizeInBits; }
92
93 /// getCopyCost - Return the cost of copying a value between two registers in
94 /// this class. A negative number means the register class is very expensive
95 /// to copy e.g. status flag register classes.
96 int getCopyCost() const { return CopyCost; }
97
98 /// isAllocatable - Return true if this register class may be used to create
99 /// virtual registers.
100 bool isAllocatable() const { return Allocatable; }
101
102 /// Return true if this register class has a defined BaseClassOrder.
103 bool isBaseClass() const { return BaseClass; }
104};
105
106/// MCRegisterDesc - This record contains information about a particular
107/// register. The SubRegs field is a zero terminated array of registers that
108/// are sub-registers of the specific register, e.g. AL, AH are sub-registers
109/// of AX. The SuperRegs field is a zero terminated array of registers that are
110/// super-registers of the specific register, e.g. RAX, EAX, are
111/// super-registers of AX.
112///
113struct MCRegisterDesc {
114 uint32_t Name; // Printable name for the reg (for debugging)
115 uint32_t SubRegs; // Sub-register set, described above
116 uint32_t SuperRegs; // Super-register set, described above
117
118 // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
119 // sub-register in SubRegs.
120 uint32_t SubRegIndices;
121
122 // Points to the list of register units. The low bits hold the first regunit
123 // number, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
124 uint32_t RegUnits;
125
126 /// Index into list with lane mask sequences. The sequence contains a lanemask
127 /// for every register unit.
128 uint16_t RegUnitLaneMasks;
129};
130
131/// MCRegisterInfo base class - We assume that the target defines a static
132/// array of MCRegisterDesc objects that represent all of the machine
133/// registers that the target has. As such, we simply have to track a pointer
134/// to this array so that we can turn register number into a register
135/// descriptor.
136///
137/// Note this class is designed to be a base class of TargetRegisterInfo, which
138/// is the interface used by codegen. However, specific targets *should never*
139/// specialize this class. MCRegisterInfo should only contain getters to access
140/// TableGen generated physical register data. It must not be extended with
141/// virtual methods.
142///
143class MCRegisterInfo {
144public:
145 using regclass_iterator = const MCRegisterClass *;
146
147 /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
148 /// performed with a binary search.
149 struct DwarfLLVMRegPair {
150 unsigned FromReg;
151 unsigned ToReg;
152
153 bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
154 };
155
156 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
157 /// index, -1 in any being invalid.
158 struct SubRegCoveredBits {
159 uint16_t Offset;
160 uint16_t Size;
161 };
162
163private:
164 const MCRegisterDesc *Desc; // Pointer to the descriptor array
165 unsigned NumRegs; // Number of entries in the array
166 MCRegister RAReg; // Return address register
167 MCRegister PCReg; // Program counter register
168 const MCRegisterClass *Classes; // Pointer to the regclass array
169 unsigned NumClasses; // Number of entries in the array
170 unsigned NumRegUnits; // Number of regunits.
171 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
172 const int16_t *DiffLists; // Pointer to the difflists array
173 const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
174 // for register units.
175 const char *RegStrings; // Pointer to the string table.
176 const char *RegClassStrings; // Pointer to the class strings.
177 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
178 // array.
179 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
180 // bit ranges array.
181 unsigned NumSubRegIndices; // Number of subreg indices.
182 const uint16_t *RegEncodingTable; // Pointer to array of register
183 // encodings.
184
185 unsigned L2DwarfRegsSize;
186 unsigned EHL2DwarfRegsSize;
187 unsigned Dwarf2LRegsSize;
188 unsigned EHDwarf2LRegsSize;
189 const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
190 const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
191 const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
192 const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
193 DenseMap<MCRegister, int> L2SEHRegs; // LLVM to SEH regs mapping
194 DenseMap<MCRegister, int> L2CVRegs; // LLVM to CV regs mapping
195
196 /// Iterator class that can traverse the differentially encoded values in
197 /// DiffLists. Don't use this class directly, use one of the adaptors below.
198 class DiffListIterator
199 : public iterator_facade_base<DiffListIterator, std::forward_iterator_tag,
200 unsigned> {
201 unsigned Val = 0;
202 const int16_t *List = nullptr;
203
204 public:
205 /// Constructs an invalid iterator, which is also the end iterator.
206 /// Call init() to point to something useful.
207 DiffListIterator() = default;
208
209 /// Point the iterator to InitVal, decoding subsequent values from DiffList.
210 void init(unsigned InitVal, const int16_t *DiffList) {
211 Val = InitVal;
212 List = DiffList;
213 }
214
215 /// Returns true if this iterator is not yet at the end.
216 bool isValid() const { return List; }
217
218 /// Dereference the iterator to get the value at the current position.
219 const unsigned &operator*() const { return Val; }
220
221 using DiffListIterator::iterator_facade_base::operator++;
222 /// Pre-increment to move to the next position.
223 DiffListIterator &operator++() {
224 assert(isValid() && "Cannot move off the end of the list.");
225 int16_t D = *List++;
226 Val += D;
227 // The end of the list is encoded as a 0 differential.
228 if (!D)
229 List = nullptr;
230 return *this;
231 }
232
233 bool operator==(const DiffListIterator &Other) const {
234 return List == Other.List;
235 }
236 };
237
238public:
239 /// Return an iterator range over all sub-registers of \p Reg, excluding \p
240 /// Reg.
241 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const;
242
243 /// Return an iterator range over all sub-registers of \p Reg, including \p
244 /// Reg.
245 iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const;
246
247 /// Return an iterator range over all super-registers of \p Reg, excluding \p
248 /// Reg.
249 iterator_range<MCSuperRegIterator> superregs(MCRegister Reg) const;
250
251 /// Return an iterator range over all super-registers of \p Reg, including \p
252 /// Reg.
253 iterator_range<MCSuperRegIterator> superregs_inclusive(MCRegister Reg) const;
254
255 /// Return an iterator range over all sub- and super-registers of \p Reg,
256 /// including \p Reg.
257 detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>,
258 iterator_range<MCSuperRegIterator>>
259 sub_and_superregs_inclusive(MCRegister Reg) const;
260
261 /// Returns an iterator range over all regunits for \p Reg.
262 iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const;
263
264 // These iterators are allowed to sub-class DiffListIterator and access
265 // internal list pointers.
266 friend class MCSubRegIterator;
267 friend class MCSubRegIndexIterator;
268 friend class MCSuperRegIterator;
269 friend class MCRegUnitIterator;
270 friend class MCRegUnitMaskIterator;
271 friend class MCRegUnitRootIterator;
272
273 /// Initialize MCRegisterInfo, called by TableGen
274 /// auto-generated routines. *DO NOT USE*.
275 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
276 unsigned PC, const MCRegisterClass *C, unsigned NC,
277 const MCPhysReg (*RURoots)[2], unsigned NRU,
278 const int16_t *DL, const LaneBitmask *RUMS,
279 const char *Strings, const char *ClassStrings,
280 const uint16_t *SubIndices, unsigned NumIndices,
281 const SubRegCoveredBits *SubIdxRanges,
282 const uint16_t *RET) {
283 Desc = D;
284 NumRegs = NR;
285 RAReg = RA;
286 PCReg = PC;
287 Classes = C;
288 DiffLists = DL;
289 RegUnitMaskSequences = RUMS;
290 RegStrings = Strings;
291 RegClassStrings = ClassStrings;
292 NumClasses = NC;
293 RegUnitRoots = RURoots;
294 NumRegUnits = NRU;
295 SubRegIndices = SubIndices;
296 NumSubRegIndices = NumIndices;
297 SubRegIdxRanges = SubIdxRanges;
298 RegEncodingTable = RET;
299
300 // Initialize DWARF register mapping variables
301 EHL2DwarfRegs = nullptr;
302 EHL2DwarfRegsSize = 0;
303 L2DwarfRegs = nullptr;
304 L2DwarfRegsSize = 0;
305 EHDwarf2LRegs = nullptr;
306 EHDwarf2LRegsSize = 0;
307 Dwarf2LRegs = nullptr;
308 Dwarf2LRegsSize = 0;
309 }
310
311 /// Used to initialize LLVM register to Dwarf
312 /// register number mapping. Called by TableGen auto-generated routines.
313 /// *DO NOT USE*.
314 void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
315 bool isEH) {
316 if (isEH) {
317 EHL2DwarfRegs = Map;
318 EHL2DwarfRegsSize = Size;
319 } else {
320 L2DwarfRegs = Map;
321 L2DwarfRegsSize = Size;
322 }
323 }
324
325 /// Used to initialize Dwarf register to LLVM
326 /// register number mapping. Called by TableGen auto-generated routines.
327 /// *DO NOT USE*.
328 void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
329 bool isEH) {
330 if (isEH) {
331 EHDwarf2LRegs = Map;
332 EHDwarf2LRegsSize = Size;
333 } else {
334 Dwarf2LRegs = Map;
335 Dwarf2LRegsSize = Size;
336 }
337 }
338
339 /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
340 /// number mapping. By default the SEH register number is just the same
341 /// as the LLVM register number.
342 /// FIXME: TableGen these numbers. Currently this requires target specific
343 /// initialization code.
344 void mapLLVMRegToSEHReg(MCRegister LLVMReg, int SEHReg) {
345 L2SEHRegs[LLVMReg] = SEHReg;
346 }
347
348 void mapLLVMRegToCVReg(MCRegister LLVMReg, int CVReg) {
349 L2CVRegs[LLVMReg] = CVReg;
350 }
351
352 /// This method should return the register where the return
353 /// address can be found.
354 MCRegister getRARegister() const {
355 return RAReg;
356 }
357
358 /// Return the register which is the program counter.
359 MCRegister getProgramCounter() const {
360 return PCReg;
361 }
362
363 const MCRegisterDesc &operator[](MCRegister RegNo) const {
364 assert(RegNo < NumRegs &&
365 "Attempting to access record for invalid register number!");
366 return Desc[RegNo];
367 }
368
369 /// Provide a get method, equivalent to [], but more useful with a
370 /// pointer to this object.
371 const MCRegisterDesc &get(MCRegister RegNo) const {
372 return operator[](RegNo);
373 }
374
375 /// Returns the physical register number of sub-register "Index"
376 /// for physical register RegNo. Return zero if the sub-register does not
377 /// exist.
378 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
379
380 /// Return a super-register of the specified register
381 /// Reg so its sub-register of index SubIdx is Reg.
382 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
383 const MCRegisterClass *RC) const;
384
385 /// For a given register pair, return the sub-register index
386 /// if the second register is a sub-register of the first. Return zero
387 /// otherwise.
388 unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const;
389
390 /// Get the size of the bit range covered by a sub-register index.
391 /// If the index isn't continuous, return the sum of the sizes of its parts.
392 /// If the index is used to access subregisters of different sizes, return -1.
393 unsigned getSubRegIdxSize(unsigned Idx) const;
394
395 /// Get the offset of the bit range covered by a sub-register index.
396 /// If an Offset doesn't make sense (the index isn't continuous, or is used to
397 /// access sub-registers at different offsets), return -1.
398 unsigned getSubRegIdxOffset(unsigned Idx) const;
399
400 /// Return the human-readable symbolic target-specific name for the
401 /// specified physical register.
402 const char *getName(MCRegister RegNo) const {
403 return RegStrings + get(RegNo).Name;
404 }
405
406 /// Return the number of registers this target has (useful for
407 /// sizing arrays holding per register information)
408 unsigned getNumRegs() const {
409 return NumRegs;
410 }
411
412 /// Return the number of sub-register indices
413 /// understood by the target. Index 0 is reserved for the no-op sub-register,
414 /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
415 unsigned getNumSubRegIndices() const {
416 return NumSubRegIndices;
417 }
418
419 /// Return the number of (native) register units in the
420 /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
421 /// can be accessed through MCRegUnitIterator defined below.
422 unsigned getNumRegUnits() const {
423 return NumRegUnits;
424 }
425
426 /// Map a target register to an equivalent dwarf register
427 /// number. Returns -1 if there is no equivalent value. The second
428 /// parameter allows targets to use different numberings for EH info and
429 /// debugging info.
430 int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
431
432 /// Map a dwarf register back to a target register. Returns std::nullopt is
433 /// there is no mapping.
434 std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
435
436 /// Map a target EH register number to an equivalent DWARF register
437 /// number.
438 int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
439
440 /// Map a target register to an equivalent SEH register
441 /// number. Returns LLVM register number if there is no equivalent value.
442 int getSEHRegNum(MCRegister RegNum) const;
443
444 /// Map a target register to an equivalent CodeView register
445 /// number.
446 int getCodeViewRegNum(MCRegister RegNum) const;
447
448 regclass_iterator regclass_begin() const { return Classes; }
449 regclass_iterator regclass_end() const { return Classes+NumClasses; }
450 iterator_range<regclass_iterator> regclasses() const {
451 return make_range(x: regclass_begin(), y: regclass_end());
452 }
453
454 unsigned getNumRegClasses() const {
455 return (unsigned)(regclass_end()-regclass_begin());
456 }
457
458 /// Returns the register class associated with the enumeration
459 /// value. See class MCOperandInfo.
460 const MCRegisterClass& getRegClass(unsigned i) const {
461 assert(i < getNumRegClasses() && "Register Class ID out of range");
462 return Classes[i];
463 }
464
465 const char *getRegClassName(const MCRegisterClass *Class) const {
466 return RegClassStrings + Class->NameIdx;
467 }
468
469 /// Returns the encoding for RegNo
470 uint16_t getEncodingValue(MCRegister RegNo) const {
471 assert(RegNo < NumRegs &&
472 "Attempting to get encoding for invalid register number!");
473 return RegEncodingTable[RegNo];
474 }
475
476 /// Returns true if RegB is a sub-register of RegA.
477 bool isSubRegister(MCRegister RegA, MCRegister RegB) const {
478 return isSuperRegister(RegA: RegB, RegB: RegA);
479 }
480
481 /// Returns true if RegB is a super-register of RegA.
482 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
483
484 /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
485 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
486 return isSuperRegisterEq(RegA: RegB, RegB: RegA);
487 }
488
489 /// Returns true if RegB is a super-register of RegA or if
490 /// RegB == RegA.
491 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const {
492 return RegA == RegB || isSuperRegister(RegA, RegB);
493 }
494
495 /// Returns true if RegB is a super-register or sub-register of RegA
496 /// or if RegB == RegA.
497 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
498 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
499 }
500
501 /// Returns true if the two registers are equal or alias each other.
502 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
503};
504
505//===----------------------------------------------------------------------===//
506// Register List Iterators
507//===----------------------------------------------------------------------===//
508
509// MCRegisterInfo provides lists of super-registers, sub-registers, and
510// aliasing registers. Use these iterator classes to traverse the lists.
511
512/// MCSubRegIterator enumerates all sub-registers of Reg.
513/// If IncludeSelf is set, Reg itself is included in the list.
514class MCSubRegIterator
515 : public iterator_adaptor_base<MCSubRegIterator,
516 MCRegisterInfo::DiffListIterator,
517 std::forward_iterator_tag, const MCPhysReg> {
518 // Cache the current value, so that we can return a reference to it.
519 MCPhysReg Val;
520
521public:
522 /// Constructs an end iterator.
523 MCSubRegIterator() = default;
524
525 MCSubRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
526 bool IncludeSelf = false) {
527 assert(MCRegister::isPhysicalRegister(Reg.id()));
528 I.init(InitVal: Reg.id(), DiffList: MCRI->DiffLists + MCRI->get(RegNo: Reg).SubRegs);
529 // Initially, the iterator points to Reg itself.
530 Val = MCPhysReg(*I);
531 if (!IncludeSelf)
532 ++*this;
533 }
534
535 const MCPhysReg &operator*() const { return Val; }
536
537 using iterator_adaptor_base::operator++;
538 MCSubRegIterator &operator++() {
539 Val = MCPhysReg(*++I);
540 return *this;
541 }
542
543 /// Returns true if this iterator is not yet at the end.
544 bool isValid() const { return I.isValid(); }
545};
546
547/// Iterator that enumerates the sub-registers of a Reg and the associated
548/// sub-register indices.
549class MCSubRegIndexIterator {
550 MCSubRegIterator SRIter;
551 const uint16_t *SRIndex;
552
553public:
554 /// Constructs an iterator that traverses subregisters and their
555 /// associated subregister indices.
556 MCSubRegIndexIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
557 : SRIter(Reg, MCRI) {
558 SRIndex = MCRI->SubRegIndices + MCRI->get(RegNo: Reg).SubRegIndices;
559 }
560
561 /// Returns current sub-register.
562 MCRegister getSubReg() const {
563 return *SRIter;
564 }
565
566 /// Returns sub-register index of the current sub-register.
567 unsigned getSubRegIndex() const {
568 return *SRIndex;
569 }
570
571 /// Returns true if this iterator is not yet at the end.
572 bool isValid() const { return SRIter.isValid(); }
573
574 /// Moves to the next position.
575 MCSubRegIndexIterator &operator++() {
576 ++SRIter;
577 ++SRIndex;
578 return *this;
579 }
580};
581
582/// MCSuperRegIterator enumerates all super-registers of Reg.
583/// If IncludeSelf is set, Reg itself is included in the list.
584class MCSuperRegIterator
585 : public iterator_adaptor_base<MCSuperRegIterator,
586 MCRegisterInfo::DiffListIterator,
587 std::forward_iterator_tag, const MCPhysReg> {
588 // Cache the current value, so that we can return a reference to it.
589 MCPhysReg Val;
590
591public:
592 /// Constructs an end iterator.
593 MCSuperRegIterator() = default;
594
595 MCSuperRegIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
596 bool IncludeSelf = false) {
597 assert(MCRegister::isPhysicalRegister(Reg.id()));
598 I.init(InitVal: Reg.id(), DiffList: MCRI->DiffLists + MCRI->get(RegNo: Reg).SuperRegs);
599 // Initially, the iterator points to Reg itself.
600 Val = MCPhysReg(*I);
601 if (!IncludeSelf)
602 ++*this;
603 }
604
605 const MCPhysReg &operator*() const { return Val; }
606
607 using iterator_adaptor_base::operator++;
608 MCSuperRegIterator &operator++() {
609 Val = MCPhysReg(*++I);
610 return *this;
611 }
612
613 /// Returns true if this iterator is not yet at the end.
614 bool isValid() const { return I.isValid(); }
615};
616
617// Definition for isSuperRegister. Put it down here since it needs the
618// iterator defined above in addition to the MCRegisterInfo class itself.
619inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{
620 return is_contained(Range: superregs(Reg: RegA), Element: RegB);
621}
622
623//===----------------------------------------------------------------------===//
624// Register Units
625//===----------------------------------------------------------------------===//
626
627// MCRegUnitIterator enumerates a list of register units for Reg. The list is
628// in ascending numerical order.
629class MCRegUnitIterator
630 : public iterator_adaptor_base<MCRegUnitIterator,
631 MCRegisterInfo::DiffListIterator,
632 std::forward_iterator_tag, const MCRegUnit> {
633 // The value must be kept in sync with RegisterInfoEmitter.cpp.
634 static constexpr unsigned RegUnitBits = 12;
635 // Cache the current value, so that we can return a reference to it.
636 MCRegUnit Val;
637
638public:
639 /// Constructs an end iterator.
640 MCRegUnitIterator() = default;
641
642 MCRegUnitIterator(MCRegister Reg, const MCRegisterInfo *MCRI) {
643 assert(Reg && "Null register has no regunits");
644 assert(MCRegister::isPhysicalRegister(Reg.id()));
645 // Decode the RegUnits MCRegisterDesc field.
646 unsigned RU = MCRI->get(RegNo: Reg).RegUnits;
647 unsigned FirstRU = RU & ((1u << RegUnitBits) - 1);
648 unsigned Offset = RU >> RegUnitBits;
649 I.init(InitVal: FirstRU, DiffList: MCRI->DiffLists + Offset);
650 Val = MCRegUnit(*I);
651 }
652
653 const MCRegUnit &operator*() const { return Val; }
654
655 using iterator_adaptor_base::operator++;
656 MCRegUnitIterator &operator++() {
657 Val = MCRegUnit(*++I);
658 return *this;
659 }
660
661 /// Returns true if this iterator is not yet at the end.
662 bool isValid() const { return I.isValid(); }
663};
664
665/// MCRegUnitMaskIterator enumerates a list of register units and their
666/// associated lane masks for Reg. The register units are in ascending
667/// numerical order.
668class MCRegUnitMaskIterator {
669 MCRegUnitIterator RUIter;
670 const LaneBitmask *MaskListIter;
671
672public:
673 MCRegUnitMaskIterator() = default;
674
675 /// Constructs an iterator that traverses the register units and their
676 /// associated LaneMasks in Reg.
677 MCRegUnitMaskIterator(MCRegister Reg, const MCRegisterInfo *MCRI)
678 : RUIter(Reg, MCRI) {
679 uint16_t Idx = MCRI->get(RegNo: Reg).RegUnitLaneMasks;
680 MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
681 }
682
683 /// Returns a (RegUnit, LaneMask) pair.
684 std::pair<unsigned,LaneBitmask> operator*() const {
685 return std::make_pair(x: *RUIter, y: *MaskListIter);
686 }
687
688 /// Returns true if this iterator is not yet at the end.
689 bool isValid() const { return RUIter.isValid(); }
690
691 /// Moves to the next position.
692 MCRegUnitMaskIterator &operator++() {
693 ++MaskListIter;
694 ++RUIter;
695 return *this;
696 }
697};
698
699// Each register unit has one or two root registers. The complete set of
700// registers containing a register unit is the union of the roots and their
701// super-registers. All registers aliasing Unit can be visited like this:
702//
703// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
704// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
705// visit(*SI);
706// }
707
708/// MCRegUnitRootIterator enumerates the root registers of a register unit.
709class MCRegUnitRootIterator {
710 uint16_t Reg0 = 0;
711 uint16_t Reg1 = 0;
712
713public:
714 MCRegUnitRootIterator() = default;
715
716 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
717 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
718 Reg0 = MCRI->RegUnitRoots[RegUnit][0];
719 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
720 }
721
722 /// Dereference to get the current root register.
723 unsigned operator*() const {
724 return Reg0;
725 }
726
727 /// Check if the iterator is at the end of the list.
728 bool isValid() const {
729 return Reg0;
730 }
731
732 /// Preincrement to move to the next root register.
733 MCRegUnitRootIterator &operator++() {
734 assert(isValid() && "Cannot move off the end of the list.");
735 Reg0 = Reg1;
736 Reg1 = 0;
737 return *this;
738 }
739};
740
741/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
742/// set, Reg itself is included in the list. This iterator does not guarantee
743/// any ordering or that entries are unique.
744class MCRegAliasIterator {
745private:
746 MCRegister Reg;
747 const MCRegisterInfo *MCRI;
748 bool IncludeSelf;
749
750 MCRegUnitIterator RI;
751 MCRegUnitRootIterator RRI;
752 MCSuperRegIterator SI;
753
754public:
755 MCRegAliasIterator(MCRegister Reg, const MCRegisterInfo *MCRI,
756 bool IncludeSelf)
757 : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
758 // Initialize the iterators.
759 for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
760 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
761 for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
762 if (!(!IncludeSelf && Reg == *SI))
763 return;
764 }
765 }
766 }
767 }
768
769 bool isValid() const { return RI.isValid(); }
770
771 MCRegister operator*() const {
772 assert(SI.isValid() && "Cannot dereference an invalid iterator.");
773 return *SI;
774 }
775
776 void advance() {
777 // Assuming SI is valid.
778 ++SI;
779 if (SI.isValid()) return;
780
781 ++RRI;
782 if (RRI.isValid()) {
783 SI = MCSuperRegIterator(*RRI, MCRI, true);
784 return;
785 }
786
787 ++RI;
788 if (RI.isValid()) {
789 RRI = MCRegUnitRootIterator(*RI, MCRI);
790 SI = MCSuperRegIterator(*RRI, MCRI, true);
791 }
792 }
793
794 MCRegAliasIterator &operator++() {
795 assert(isValid() && "Cannot move off the end of the list.");
796 do advance();
797 while (!IncludeSelf && isValid() && *SI == Reg);
798 return *this;
799 }
800};
801
802inline iterator_range<MCSubRegIterator>
803MCRegisterInfo::subregs(MCRegister Reg) const {
804 return make_range(x: {Reg, this, /*IncludeSelf=*/false}, y: MCSubRegIterator());
805}
806
807inline iterator_range<MCSubRegIterator>
808MCRegisterInfo::subregs_inclusive(MCRegister Reg) const {
809 return make_range(x: {Reg, this, /*IncludeSelf=*/true}, y: MCSubRegIterator());
810}
811
812inline iterator_range<MCSuperRegIterator>
813MCRegisterInfo::superregs(MCRegister Reg) const {
814 return make_range(x: {Reg, this, /*IncludeSelf=*/false}, y: MCSuperRegIterator());
815}
816
817inline iterator_range<MCSuperRegIterator>
818MCRegisterInfo::superregs_inclusive(MCRegister Reg) const {
819 return make_range(x: {Reg, this, /*IncludeSelf=*/true}, y: MCSuperRegIterator());
820}
821
822inline detail::concat_range<const MCPhysReg, iterator_range<MCSubRegIterator>,
823 iterator_range<MCSuperRegIterator>>
824MCRegisterInfo::sub_and_superregs_inclusive(MCRegister Reg) const {
825 return concat<const MCPhysReg>(Ranges: subregs_inclusive(Reg), Ranges: superregs(Reg));
826}
827
828inline iterator_range<MCRegUnitIterator>
829MCRegisterInfo::regunits(MCRegister Reg) const {
830 return make_range(x: {Reg, this}, y: MCRegUnitIterator());
831}
832
833} // end namespace llvm
834
835#endif // LLVM_MC_MCREGISTERINFO_H
836

source code of llvm/include/llvm/MC/MCRegisterInfo.h