1 | //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // Methods common to all machine instructions. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #include "llvm/CodeGen/MachineInstr.h" |
14 | #include "llvm/ADT/ArrayRef.h" |
15 | #include "llvm/ADT/Hashing.h" |
16 | #include "llvm/ADT/STLExtras.h" |
17 | #include "llvm/ADT/SmallBitVector.h" |
18 | #include "llvm/ADT/SmallVector.h" |
19 | #include "llvm/Analysis/AliasAnalysis.h" |
20 | #include "llvm/Analysis/MemoryLocation.h" |
21 | #include "llvm/CodeGen/MachineBasicBlock.h" |
22 | #include "llvm/CodeGen/MachineFrameInfo.h" |
23 | #include "llvm/CodeGen/MachineFunction.h" |
24 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
25 | #include "llvm/CodeGen/MachineInstrBundle.h" |
26 | #include "llvm/CodeGen/MachineMemOperand.h" |
27 | #include "llvm/CodeGen/MachineModuleInfo.h" |
28 | #include "llvm/CodeGen/MachineOperand.h" |
29 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
30 | #include "llvm/CodeGen/PseudoSourceValue.h" |
31 | #include "llvm/CodeGen/Register.h" |
32 | #include "llvm/CodeGen/StackMaps.h" |
33 | #include "llvm/CodeGen/TargetInstrInfo.h" |
34 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
35 | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
36 | #include "llvm/CodeGenTypes/LowLevelType.h" |
37 | #include "llvm/IR/Constants.h" |
38 | #include "llvm/IR/DebugInfoMetadata.h" |
39 | #include "llvm/IR/DebugLoc.h" |
40 | #include "llvm/IR/Function.h" |
41 | #include "llvm/IR/InlineAsm.h" |
42 | #include "llvm/IR/LLVMContext.h" |
43 | #include "llvm/IR/Metadata.h" |
44 | #include "llvm/IR/Module.h" |
45 | #include "llvm/IR/ModuleSlotTracker.h" |
46 | #include "llvm/IR/Operator.h" |
47 | #include "llvm/MC/MCInstrDesc.h" |
48 | #include "llvm/MC/MCRegisterInfo.h" |
49 | #include "llvm/Support/Casting.h" |
50 | #include "llvm/Support/Compiler.h" |
51 | #include "llvm/Support/Debug.h" |
52 | #include "llvm/Support/ErrorHandling.h" |
53 | #include "llvm/Support/FormattedStream.h" |
54 | #include "llvm/Support/raw_ostream.h" |
55 | #include "llvm/Target/TargetMachine.h" |
56 | #include <algorithm> |
57 | #include <cassert> |
58 | #include <cstdint> |
59 | #include <cstring> |
60 | #include <utility> |
61 | |
62 | using namespace llvm; |
63 | |
64 | static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { |
65 | if (const MachineBasicBlock *MBB = MI.getParent()) |
66 | if (const MachineFunction *MF = MBB->getParent()) |
67 | return MF; |
68 | return nullptr; |
69 | } |
70 | |
71 | // Try to crawl up to the machine function and get TRI and IntrinsicInfo from |
72 | // it. |
73 | static void tryToGetTargetInfo(const MachineInstr &MI, |
74 | const TargetRegisterInfo *&TRI, |
75 | const MachineRegisterInfo *&MRI, |
76 | const TargetIntrinsicInfo *&IntrinsicInfo, |
77 | const TargetInstrInfo *&TII) { |
78 | |
79 | if (const MachineFunction *MF = getMFIfAvailable(MI)) { |
80 | TRI = MF->getSubtarget().getRegisterInfo(); |
81 | MRI = &MF->getRegInfo(); |
82 | IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); |
83 | TII = MF->getSubtarget().getInstrInfo(); |
84 | } |
85 | } |
86 | |
87 | void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { |
88 | for (MCPhysReg ImpDef : MCID->implicit_defs()) |
89 | addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpDef, isDef: true, isImp: true)); |
90 | for (MCPhysReg ImpUse : MCID->implicit_uses()) |
91 | addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpUse, isDef: false, isImp: true)); |
92 | } |
93 | |
94 | /// MachineInstr ctor - This constructor creates a MachineInstr and adds the |
95 | /// implicit operands. It reserves space for the number of operands specified by |
96 | /// the MCInstrDesc. |
97 | MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID, |
98 | DebugLoc DL, bool NoImp) |
99 | : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0), |
100 | DbgLoc(std::move(DL)), DebugInstrNum(0) { |
101 | assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor" ); |
102 | |
103 | // Reserve space for the expected number of operands. |
104 | if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() + |
105 | MCID->implicit_uses().size()) { |
106 | CapOperands = OperandCapacity::get(N: NumOps); |
107 | Operands = MF.allocateOperandArray(Cap: CapOperands); |
108 | } |
109 | |
110 | if (!NoImp) |
111 | addImplicitDefUseOperands(MF); |
112 | } |
113 | |
114 | /// MachineInstr ctor - Copies MachineInstr arg exactly. |
115 | /// Does not copy the number from debug instruction numbering, to preserve |
116 | /// uniqueness. |
117 | MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) |
118 | : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0), |
119 | Info(MI.Info), DbgLoc(MI.getDebugLoc()), DebugInstrNum(0) { |
120 | assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor" ); |
121 | |
122 | CapOperands = OperandCapacity::get(N: MI.getNumOperands()); |
123 | Operands = MF.allocateOperandArray(Cap: CapOperands); |
124 | |
125 | // Copy operands. |
126 | for (const MachineOperand &MO : MI.operands()) |
127 | addOperand(MF, Op: MO); |
128 | |
129 | // Replicate ties between the operands, which addOperand was not |
130 | // able to do reliably. |
131 | for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { |
132 | MachineOperand &NewMO = getOperand(i); |
133 | const MachineOperand &OrigMO = MI.getOperand(i); |
134 | NewMO.TiedTo = OrigMO.TiedTo; |
135 | } |
136 | |
137 | // Copy all the sensible flags. |
138 | setFlags(MI.Flags); |
139 | } |
140 | |
141 | void MachineInstr::setDesc(const MCInstrDesc &TID) { |
142 | if (getParent()) |
143 | getMF()->handleChangeDesc(MI&: *this, TID); |
144 | MCID = &TID; |
145 | } |
146 | |
147 | void MachineInstr::moveBefore(MachineInstr *MovePos) { |
148 | MovePos->getParent()->splice(Where: MovePos, Other: getParent(), From: getIterator()); |
149 | } |
150 | |
151 | /// getRegInfo - If this instruction is embedded into a MachineFunction, |
152 | /// return the MachineRegisterInfo object for the current function, otherwise |
153 | /// return null. |
154 | MachineRegisterInfo *MachineInstr::getRegInfo() { |
155 | if (MachineBasicBlock *MBB = getParent()) |
156 | return &MBB->getParent()->getRegInfo(); |
157 | return nullptr; |
158 | } |
159 | |
160 | const MachineRegisterInfo *MachineInstr::getRegInfo() const { |
161 | if (const MachineBasicBlock *MBB = getParent()) |
162 | return &MBB->getParent()->getRegInfo(); |
163 | return nullptr; |
164 | } |
165 | |
166 | void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) { |
167 | for (MachineOperand &MO : operands()) |
168 | if (MO.isReg()) |
169 | MRI.removeRegOperandFromUseList(MO: &MO); |
170 | } |
171 | |
172 | void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) { |
173 | for (MachineOperand &MO : operands()) |
174 | if (MO.isReg()) |
175 | MRI.addRegOperandToUseList(MO: &MO); |
176 | } |
177 | |
178 | void MachineInstr::addOperand(const MachineOperand &Op) { |
179 | MachineBasicBlock *MBB = getParent(); |
180 | assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs" ); |
181 | MachineFunction *MF = MBB->getParent(); |
182 | assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs" ); |
183 | addOperand(MF&: *MF, Op); |
184 | } |
185 | |
186 | /// Move NumOps MachineOperands from Src to Dst, with support for overlapping |
187 | /// ranges. If MRI is non-null also update use-def chains. |
188 | static void moveOperands(MachineOperand *Dst, MachineOperand *Src, |
189 | unsigned NumOps, MachineRegisterInfo *MRI) { |
190 | if (MRI) |
191 | return MRI->moveOperands(Dst, Src, NumOps); |
192 | // MachineOperand is a trivially copyable type so we can just use memmove. |
193 | assert(Dst && Src && "Unknown operands" ); |
194 | std::memmove(dest: Dst, src: Src, n: NumOps * sizeof(MachineOperand)); |
195 | } |
196 | |
197 | /// addOperand - Add the specified operand to the instruction. If it is an |
198 | /// implicit operand, it is added to the end of the operand list. If it is |
199 | /// an explicit operand it is added at the end of the explicit operand list |
200 | /// (before the first implicit operand). |
201 | void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) { |
202 | assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) && |
203 | "Cannot add more operands." ); |
204 | assert(MCID && "Cannot add operands before providing an instr descriptor" ); |
205 | |
206 | // Check if we're adding one of our existing operands. |
207 | if (&Op >= Operands && &Op < Operands + NumOperands) { |
208 | // This is unusual: MI->addOperand(MI->getOperand(i)). |
209 | // If adding Op requires reallocating or moving existing operands around, |
210 | // the Op reference could go stale. Support it by copying Op. |
211 | MachineOperand CopyOp(Op); |
212 | return addOperand(MF, Op: CopyOp); |
213 | } |
214 | |
215 | // Find the insert location for the new operand. Implicit registers go at |
216 | // the end, everything else goes before the implicit regs. |
217 | // |
218 | // FIXME: Allow mixed explicit and implicit operands on inline asm. |
219 | // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as |
220 | // implicit-defs, but they must not be moved around. See the FIXME in |
221 | // InstrEmitter.cpp. |
222 | unsigned OpNo = getNumOperands(); |
223 | bool isImpReg = Op.isReg() && Op.isImplicit(); |
224 | if (!isImpReg && !isInlineAsm()) { |
225 | while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { |
226 | --OpNo; |
227 | assert(!Operands[OpNo].isTied() && "Cannot move tied operands" ); |
228 | } |
229 | } |
230 | |
231 | // OpNo now points as the desired insertion point. Unless this is a variadic |
232 | // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). |
233 | // RegMask operands go between the explicit and implicit operands. |
234 | MachineRegisterInfo *MRI = getRegInfo(); |
235 | |
236 | // Determine if the Operands array needs to be reallocated. |
237 | // Save the old capacity and operand array. |
238 | OperandCapacity OldCap = CapOperands; |
239 | MachineOperand *OldOperands = Operands; |
240 | if (!OldOperands || OldCap.getSize() == getNumOperands()) { |
241 | CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(N: 1); |
242 | Operands = MF.allocateOperandArray(Cap: CapOperands); |
243 | // Move the operands before the insertion point. |
244 | if (OpNo) |
245 | moveOperands(Dst: Operands, Src: OldOperands, NumOps: OpNo, MRI); |
246 | } |
247 | |
248 | // Move the operands following the insertion point. |
249 | if (OpNo != NumOperands) |
250 | moveOperands(Dst: Operands + OpNo + 1, Src: OldOperands + OpNo, NumOps: NumOperands - OpNo, |
251 | MRI); |
252 | ++NumOperands; |
253 | |
254 | // Deallocate the old operand array. |
255 | if (OldOperands != Operands && OldOperands) |
256 | MF.deallocateOperandArray(Cap: OldCap, Array: OldOperands); |
257 | |
258 | // Copy Op into place. It still needs to be inserted into the MRI use lists. |
259 | MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op); |
260 | NewMO->ParentMI = this; |
261 | |
262 | // When adding a register operand, tell MRI about it. |
263 | if (NewMO->isReg()) { |
264 | // Ensure isOnRegUseList() returns false, regardless of Op's status. |
265 | NewMO->Contents.Reg.Prev = nullptr; |
266 | // Ignore existing ties. This is not a property that can be copied. |
267 | NewMO->TiedTo = 0; |
268 | // Add the new operand to MRI, but only for instructions in an MBB. |
269 | if (MRI) |
270 | MRI->addRegOperandToUseList(MO: NewMO); |
271 | // The MCID operand information isn't accurate until we start adding |
272 | // explicit operands. The implicit operands are added first, then the |
273 | // explicits are inserted before them. |
274 | if (!isImpReg) { |
275 | // Tie uses to defs as indicated in MCInstrDesc. |
276 | if (NewMO->isUse()) { |
277 | int DefIdx = MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::TIED_TO); |
278 | if (DefIdx != -1) |
279 | tieOperands(DefIdx, UseIdx: OpNo); |
280 | } |
281 | // If the register operand is flagged as early, mark the operand as such. |
282 | if (MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::EARLY_CLOBBER) != -1) |
283 | NewMO->setIsEarlyClobber(true); |
284 | } |
285 | // Ensure debug instructions set debug flag on register uses. |
286 | if (NewMO->isUse() && isDebugInstr()) |
287 | NewMO->setIsDebug(); |
288 | } |
289 | } |
290 | |
291 | void MachineInstr::removeOperand(unsigned OpNo) { |
292 | assert(OpNo < getNumOperands() && "Invalid operand number" ); |
293 | untieRegOperand(OpIdx: OpNo); |
294 | |
295 | #ifndef NDEBUG |
296 | // Moving tied operands would break the ties. |
297 | for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i) |
298 | if (Operands[i].isReg()) |
299 | assert(!Operands[i].isTied() && "Cannot move tied operands" ); |
300 | #endif |
301 | |
302 | MachineRegisterInfo *MRI = getRegInfo(); |
303 | if (MRI && Operands[OpNo].isReg()) |
304 | MRI->removeRegOperandFromUseList(MO: Operands + OpNo); |
305 | |
306 | // Don't call the MachineOperand destructor. A lot of this code depends on |
307 | // MachineOperand having a trivial destructor anyway, and adding a call here |
308 | // wouldn't make it 'destructor-correct'. |
309 | |
310 | if (unsigned N = NumOperands - 1 - OpNo) |
311 | moveOperands(Dst: Operands + OpNo, Src: Operands + OpNo + 1, NumOps: N, MRI); |
312 | --NumOperands; |
313 | } |
314 | |
315 | void MachineInstr::setExtraInfo(MachineFunction &MF, |
316 | ArrayRef<MachineMemOperand *> MMOs, |
317 | MCSymbol *PreInstrSymbol, |
318 | MCSymbol *PostInstrSymbol, |
319 | MDNode *HeapAllocMarker, MDNode *PCSections, |
320 | uint32_t CFIType) { |
321 | bool HasPreInstrSymbol = PreInstrSymbol != nullptr; |
322 | bool HasPostInstrSymbol = PostInstrSymbol != nullptr; |
323 | bool HasHeapAllocMarker = HeapAllocMarker != nullptr; |
324 | bool HasPCSections = PCSections != nullptr; |
325 | bool HasCFIType = CFIType != 0; |
326 | int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + |
327 | HasHeapAllocMarker + HasPCSections + HasCFIType; |
328 | |
329 | // Drop all extra info if there is none. |
330 | if (NumPointers <= 0) { |
331 | Info.clear(); |
332 | return; |
333 | } |
334 | |
335 | // If more than one pointer, then store out of line. Store heap alloc markers |
336 | // out of line because PointerSumType cannot hold more than 4 tag types with |
337 | // 32-bit pointers. |
338 | // FIXME: Maybe we should make the symbols in the extra info mutable? |
339 | else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections || |
340 | HasCFIType) { |
341 | Info.set<EIIK_OutOfLine>( |
342 | MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol, |
343 | HeapAllocMarker, PCSections, CFIType)); |
344 | return; |
345 | } |
346 | |
347 | // Otherwise store the single pointer inline. |
348 | if (HasPreInstrSymbol) |
349 | Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol); |
350 | else if (HasPostInstrSymbol) |
351 | Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol); |
352 | else |
353 | Info.set<EIIK_MMO>(MMOs[0]); |
354 | } |
355 | |
356 | void MachineInstr::dropMemRefs(MachineFunction &MF) { |
357 | if (memoperands_empty()) |
358 | return; |
359 | |
360 | setExtraInfo(MF, MMOs: {}, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(), |
361 | HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType()); |
362 | } |
363 | |
364 | void MachineInstr::setMemRefs(MachineFunction &MF, |
365 | ArrayRef<MachineMemOperand *> MMOs) { |
366 | if (MMOs.empty()) { |
367 | dropMemRefs(MF); |
368 | return; |
369 | } |
370 | |
371 | setExtraInfo(MF, MMOs, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(), |
372 | HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType()); |
373 | } |
374 | |
375 | void MachineInstr::addMemOperand(MachineFunction &MF, |
376 | MachineMemOperand *MO) { |
377 | SmallVector<MachineMemOperand *, 2> MMOs; |
378 | MMOs.append(in_start: memoperands_begin(), in_end: memoperands_end()); |
379 | MMOs.push_back(Elt: MO); |
380 | setMemRefs(MF, MMOs); |
381 | } |
382 | |
383 | void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) { |
384 | if (this == &MI) |
385 | // Nothing to do for a self-clone! |
386 | return; |
387 | |
388 | assert(&MF == MI.getMF() && |
389 | "Invalid machine functions when cloning memory refrences!" ); |
390 | // See if we can just steal the extra info already allocated for the |
391 | // instruction. We can do this whenever the pre- and post-instruction symbols |
392 | // are the same (including null). |
393 | if (getPreInstrSymbol() == MI.getPreInstrSymbol() && |
394 | getPostInstrSymbol() == MI.getPostInstrSymbol() && |
395 | getHeapAllocMarker() == MI.getHeapAllocMarker() && |
396 | getPCSections() == MI.getPCSections()) { |
397 | Info = MI.Info; |
398 | return; |
399 | } |
400 | |
401 | // Otherwise, fall back on a copy-based clone. |
402 | setMemRefs(MF, MMOs: MI.memoperands()); |
403 | } |
404 | |
405 | /// Check to see if the MMOs pointed to by the two MemRefs arrays are |
406 | /// identical. |
407 | static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS, |
408 | ArrayRef<MachineMemOperand *> RHS) { |
409 | if (LHS.size() != RHS.size()) |
410 | return false; |
411 | |
412 | auto LHSPointees = make_pointee_range(Range&: LHS); |
413 | auto RHSPointees = make_pointee_range(Range&: RHS); |
414 | return std::equal(first1: LHSPointees.begin(), last1: LHSPointees.end(), |
415 | first2: RHSPointees.begin()); |
416 | } |
417 | |
418 | void MachineInstr::cloneMergedMemRefs(MachineFunction &MF, |
419 | ArrayRef<const MachineInstr *> MIs) { |
420 | // Try handling easy numbers of MIs with simpler mechanisms. |
421 | if (MIs.empty()) { |
422 | dropMemRefs(MF); |
423 | return; |
424 | } |
425 | if (MIs.size() == 1) { |
426 | cloneMemRefs(MF, MI: *MIs[0]); |
427 | return; |
428 | } |
429 | // Because an empty memoperands list provides *no* information and must be |
430 | // handled conservatively (assuming the instruction can do anything), the only |
431 | // way to merge with it is to drop all other memoperands. |
432 | if (MIs[0]->memoperands_empty()) { |
433 | dropMemRefs(MF); |
434 | return; |
435 | } |
436 | |
437 | // Handle the general case. |
438 | SmallVector<MachineMemOperand *, 2> MergedMMOs; |
439 | // Start with the first instruction. |
440 | assert(&MF == MIs[0]->getMF() && |
441 | "Invalid machine functions when cloning memory references!" ); |
442 | MergedMMOs.append(in_start: MIs[0]->memoperands_begin(), in_end: MIs[0]->memoperands_end()); |
443 | // Now walk all the other instructions and accumulate any different MMOs. |
444 | for (const MachineInstr &MI : make_pointee_range(Range: MIs.slice(N: 1))) { |
445 | assert(&MF == MI.getMF() && |
446 | "Invalid machine functions when cloning memory references!" ); |
447 | |
448 | // Skip MIs with identical operands to the first. This is a somewhat |
449 | // arbitrary hack but will catch common cases without being quadratic. |
450 | // TODO: We could fully implement merge semantics here if needed. |
451 | if (hasIdenticalMMOs(LHS: MIs[0]->memoperands(), RHS: MI.memoperands())) |
452 | continue; |
453 | |
454 | // Because an empty memoperands list provides *no* information and must be |
455 | // handled conservatively (assuming the instruction can do anything), the |
456 | // only way to merge with it is to drop all other memoperands. |
457 | if (MI.memoperands_empty()) { |
458 | dropMemRefs(MF); |
459 | return; |
460 | } |
461 | |
462 | // Otherwise accumulate these into our temporary buffer of the merged state. |
463 | MergedMMOs.append(in_start: MI.memoperands_begin(), in_end: MI.memoperands_end()); |
464 | } |
465 | |
466 | setMemRefs(MF, MMOs: MergedMMOs); |
467 | } |
468 | |
469 | void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { |
470 | // Do nothing if old and new symbols are the same. |
471 | if (Symbol == getPreInstrSymbol()) |
472 | return; |
473 | |
474 | // If there was only one symbol and we're removing it, just clear info. |
475 | if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) { |
476 | Info.clear(); |
477 | return; |
478 | } |
479 | |
480 | setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: Symbol, PostInstrSymbol: getPostInstrSymbol(), |
481 | HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType()); |
482 | } |
483 | |
484 | void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { |
485 | // Do nothing if old and new symbols are the same. |
486 | if (Symbol == getPostInstrSymbol()) |
487 | return; |
488 | |
489 | // If there was only one symbol and we're removing it, just clear info. |
490 | if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) { |
491 | Info.clear(); |
492 | return; |
493 | } |
494 | |
495 | setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: Symbol, |
496 | HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType()); |
497 | } |
498 | |
499 | void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) { |
500 | // Do nothing if old and new symbols are the same. |
501 | if (Marker == getHeapAllocMarker()) |
502 | return; |
503 | |
504 | setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(), |
505 | HeapAllocMarker: Marker, PCSections: getPCSections(), CFIType: getCFIType()); |
506 | } |
507 | |
508 | void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) { |
509 | // Do nothing if old and new symbols are the same. |
510 | if (PCSections == getPCSections()) |
511 | return; |
512 | |
513 | setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(), |
514 | HeapAllocMarker: getHeapAllocMarker(), PCSections, CFIType: getCFIType()); |
515 | } |
516 | |
517 | void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) { |
518 | // Do nothing if old and new types are the same. |
519 | if (Type == getCFIType()) |
520 | return; |
521 | |
522 | setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(), |
523 | HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: Type); |
524 | } |
525 | |
526 | void MachineInstr::cloneInstrSymbols(MachineFunction &MF, |
527 | const MachineInstr &MI) { |
528 | if (this == &MI) |
529 | // Nothing to do for a self-clone! |
530 | return; |
531 | |
532 | assert(&MF == MI.getMF() && |
533 | "Invalid machine functions when cloning instruction symbols!" ); |
534 | |
535 | setPreInstrSymbol(MF, Symbol: MI.getPreInstrSymbol()); |
536 | setPostInstrSymbol(MF, Symbol: MI.getPostInstrSymbol()); |
537 | setHeapAllocMarker(MF, Marker: MI.getHeapAllocMarker()); |
538 | setPCSections(MF, PCSections: MI.getPCSections()); |
539 | } |
540 | |
541 | uint32_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const { |
542 | // For now, the just return the union of the flags. If the flags get more |
543 | // complicated over time, we might need more logic here. |
544 | return getFlags() | Other.getFlags(); |
545 | } |
546 | |
547 | uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { |
548 | uint32_t MIFlags = 0; |
549 | // Copy the wrapping flags. |
550 | if (const OverflowingBinaryOperator *OB = |
551 | dyn_cast<OverflowingBinaryOperator>(Val: &I)) { |
552 | if (OB->hasNoSignedWrap()) |
553 | MIFlags |= MachineInstr::MIFlag::NoSWrap; |
554 | if (OB->hasNoUnsignedWrap()) |
555 | MIFlags |= MachineInstr::MIFlag::NoUWrap; |
556 | } |
557 | |
558 | // Copy the exact flag. |
559 | if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(Val: &I)) |
560 | if (PE->isExact()) |
561 | MIFlags |= MachineInstr::MIFlag::IsExact; |
562 | |
563 | // Copy the fast-math flags. |
564 | if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(Val: &I)) { |
565 | const FastMathFlags Flags = FP->getFastMathFlags(); |
566 | if (Flags.noNaNs()) |
567 | MIFlags |= MachineInstr::MIFlag::FmNoNans; |
568 | if (Flags.noInfs()) |
569 | MIFlags |= MachineInstr::MIFlag::FmNoInfs; |
570 | if (Flags.noSignedZeros()) |
571 | MIFlags |= MachineInstr::MIFlag::FmNsz; |
572 | if (Flags.allowReciprocal()) |
573 | MIFlags |= MachineInstr::MIFlag::FmArcp; |
574 | if (Flags.allowContract()) |
575 | MIFlags |= MachineInstr::MIFlag::FmContract; |
576 | if (Flags.approxFunc()) |
577 | MIFlags |= MachineInstr::MIFlag::FmAfn; |
578 | if (Flags.allowReassoc()) |
579 | MIFlags |= MachineInstr::MIFlag::FmReassoc; |
580 | } |
581 | |
582 | if (I.getMetadata(KindID: LLVMContext::MD_unpredictable)) |
583 | MIFlags |= MachineInstr::MIFlag::Unpredictable; |
584 | |
585 | return MIFlags; |
586 | } |
587 | |
588 | void MachineInstr::copyIRFlags(const Instruction &I) { |
589 | Flags = copyFlagsFromInstruction(I); |
590 | } |
591 | |
592 | bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const { |
593 | assert(!isBundledWithPred() && "Must be called on bundle header" ); |
594 | for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) { |
595 | if (MII->getDesc().getFlags() & Mask) { |
596 | if (Type == AnyInBundle) |
597 | return true; |
598 | } else { |
599 | if (Type == AllInBundle && !MII->isBundle()) |
600 | return false; |
601 | } |
602 | // This was the last instruction in the bundle. |
603 | if (!MII->isBundledWithSucc()) |
604 | return Type == AllInBundle; |
605 | } |
606 | } |
607 | |
608 | bool MachineInstr::isIdenticalTo(const MachineInstr &Other, |
609 | MICheckType Check) const { |
610 | // If opcodes or number of operands are not the same then the two |
611 | // instructions are obviously not identical. |
612 | if (Other.getOpcode() != getOpcode() || |
613 | Other.getNumOperands() != getNumOperands()) |
614 | return false; |
615 | |
616 | if (isBundle()) { |
617 | // We have passed the test above that both instructions have the same |
618 | // opcode, so we know that both instructions are bundles here. Let's compare |
619 | // MIs inside the bundle. |
620 | assert(Other.isBundle() && "Expected that both instructions are bundles." ); |
621 | MachineBasicBlock::const_instr_iterator I1 = getIterator(); |
622 | MachineBasicBlock::const_instr_iterator I2 = Other.getIterator(); |
623 | // Loop until we analysed the last intruction inside at least one of the |
624 | // bundles. |
625 | while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) { |
626 | ++I1; |
627 | ++I2; |
628 | if (!I1->isIdenticalTo(Other: *I2, Check)) |
629 | return false; |
630 | } |
631 | // If we've reached the end of just one of the two bundles, but not both, |
632 | // the instructions are not identical. |
633 | if (I1->isBundledWithSucc() || I2->isBundledWithSucc()) |
634 | return false; |
635 | } |
636 | |
637 | // Check operands to make sure they match. |
638 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { |
639 | const MachineOperand &MO = getOperand(i); |
640 | const MachineOperand &OMO = Other.getOperand(i); |
641 | if (!MO.isReg()) { |
642 | if (!MO.isIdenticalTo(Other: OMO)) |
643 | return false; |
644 | continue; |
645 | } |
646 | |
647 | // Clients may or may not want to ignore defs when testing for equality. |
648 | // For example, machine CSE pass only cares about finding common |
649 | // subexpressions, so it's safe to ignore virtual register defs. |
650 | if (MO.isDef()) { |
651 | if (Check == IgnoreDefs) |
652 | continue; |
653 | else if (Check == IgnoreVRegDefs) { |
654 | if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual()) |
655 | if (!MO.isIdenticalTo(Other: OMO)) |
656 | return false; |
657 | } else { |
658 | if (!MO.isIdenticalTo(Other: OMO)) |
659 | return false; |
660 | if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) |
661 | return false; |
662 | } |
663 | } else { |
664 | if (!MO.isIdenticalTo(Other: OMO)) |
665 | return false; |
666 | if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) |
667 | return false; |
668 | } |
669 | } |
670 | // If DebugLoc does not match then two debug instructions are not identical. |
671 | if (isDebugInstr()) |
672 | if (getDebugLoc() && Other.getDebugLoc() && |
673 | getDebugLoc() != Other.getDebugLoc()) |
674 | return false; |
675 | // If pre- or post-instruction symbols do not match then the two instructions |
676 | // are not identical. |
677 | if (getPreInstrSymbol() != Other.getPreInstrSymbol() || |
678 | getPostInstrSymbol() != Other.getPostInstrSymbol()) |
679 | return false; |
680 | // Call instructions with different CFI types are not identical. |
681 | if (isCall() && getCFIType() != Other.getCFIType()) |
682 | return false; |
683 | |
684 | return true; |
685 | } |
686 | |
687 | bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const { |
688 | if (!isDebugValueLike() || !Other.isDebugValueLike()) |
689 | return false; |
690 | if (getDebugLoc() != Other.getDebugLoc()) |
691 | return false; |
692 | if (getDebugVariable() != Other.getDebugVariable()) |
693 | return false; |
694 | if (getNumDebugOperands() != Other.getNumDebugOperands()) |
695 | return false; |
696 | for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx) |
697 | if (!getDebugOperand(Index: OpIdx).isIdenticalTo(Other: Other.getDebugOperand(Index: OpIdx))) |
698 | return false; |
699 | if (!DIExpression::isEqualExpression( |
700 | FirstExpr: getDebugExpression(), FirstIndirect: isIndirectDebugValue(), |
701 | SecondExpr: Other.getDebugExpression(), SecondIndirect: Other.isIndirectDebugValue())) |
702 | return false; |
703 | return true; |
704 | } |
705 | |
706 | const MachineFunction *MachineInstr::getMF() const { |
707 | return getParent()->getParent(); |
708 | } |
709 | |
710 | MachineInstr *MachineInstr::removeFromParent() { |
711 | assert(getParent() && "Not embedded in a basic block!" ); |
712 | return getParent()->remove(I: this); |
713 | } |
714 | |
715 | MachineInstr *MachineInstr::removeFromBundle() { |
716 | assert(getParent() && "Not embedded in a basic block!" ); |
717 | return getParent()->remove_instr(I: this); |
718 | } |
719 | |
720 | void MachineInstr::eraseFromParent() { |
721 | assert(getParent() && "Not embedded in a basic block!" ); |
722 | getParent()->erase(I: this); |
723 | } |
724 | |
725 | void MachineInstr::eraseFromBundle() { |
726 | assert(getParent() && "Not embedded in a basic block!" ); |
727 | getParent()->erase_instr(I: this); |
728 | } |
729 | |
730 | bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const { |
731 | if (!isCall(Type)) |
732 | return false; |
733 | switch (getOpcode()) { |
734 | case TargetOpcode::PATCHPOINT: |
735 | case TargetOpcode::STACKMAP: |
736 | case TargetOpcode::STATEPOINT: |
737 | case TargetOpcode::FENTRY_CALL: |
738 | return false; |
739 | } |
740 | return true; |
741 | } |
742 | |
743 | bool MachineInstr::shouldUpdateCallSiteInfo() const { |
744 | if (isBundle()) |
745 | return isCandidateForCallSiteEntry(Type: MachineInstr::AnyInBundle); |
746 | return isCandidateForCallSiteEntry(); |
747 | } |
748 | |
749 | unsigned MachineInstr::getNumExplicitOperands() const { |
750 | unsigned NumOperands = MCID->getNumOperands(); |
751 | if (!MCID->isVariadic()) |
752 | return NumOperands; |
753 | |
754 | for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) { |
755 | const MachineOperand &MO = getOperand(i: I); |
756 | // The operands must always be in the following order: |
757 | // - explicit reg defs, |
758 | // - other explicit operands (reg uses, immediates, etc.), |
759 | // - implicit reg defs |
760 | // - implicit reg uses |
761 | if (MO.isReg() && MO.isImplicit()) |
762 | break; |
763 | ++NumOperands; |
764 | } |
765 | return NumOperands; |
766 | } |
767 | |
768 | unsigned MachineInstr::getNumExplicitDefs() const { |
769 | unsigned NumDefs = MCID->getNumDefs(); |
770 | if (!MCID->isVariadic()) |
771 | return NumDefs; |
772 | |
773 | for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) { |
774 | const MachineOperand &MO = getOperand(i: I); |
775 | if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) |
776 | break; |
777 | ++NumDefs; |
778 | } |
779 | return NumDefs; |
780 | } |
781 | |
782 | void MachineInstr::bundleWithPred() { |
783 | assert(!isBundledWithPred() && "MI is already bundled with its predecessor" ); |
784 | setFlag(BundledPred); |
785 | MachineBasicBlock::instr_iterator Pred = getIterator(); |
786 | --Pred; |
787 | assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags" ); |
788 | Pred->setFlag(BundledSucc); |
789 | } |
790 | |
791 | void MachineInstr::bundleWithSucc() { |
792 | assert(!isBundledWithSucc() && "MI is already bundled with its successor" ); |
793 | setFlag(BundledSucc); |
794 | MachineBasicBlock::instr_iterator Succ = getIterator(); |
795 | ++Succ; |
796 | assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags" ); |
797 | Succ->setFlag(BundledPred); |
798 | } |
799 | |
800 | void MachineInstr::unbundleFromPred() { |
801 | assert(isBundledWithPred() && "MI isn't bundled with its predecessor" ); |
802 | clearFlag(Flag: BundledPred); |
803 | MachineBasicBlock::instr_iterator Pred = getIterator(); |
804 | --Pred; |
805 | assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags" ); |
806 | Pred->clearFlag(Flag: BundledSucc); |
807 | } |
808 | |
809 | void MachineInstr::unbundleFromSucc() { |
810 | assert(isBundledWithSucc() && "MI isn't bundled with its successor" ); |
811 | clearFlag(Flag: BundledSucc); |
812 | MachineBasicBlock::instr_iterator Succ = getIterator(); |
813 | ++Succ; |
814 | assert(Succ->isBundledWithPred() && "Inconsistent bundle flags" ); |
815 | Succ->clearFlag(Flag: BundledPred); |
816 | } |
817 | |
818 | bool MachineInstr::isStackAligningInlineAsm() const { |
819 | if (isInlineAsm()) { |
820 | unsigned = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm(); |
821 | if (ExtraInfo & InlineAsm::Extra_IsAlignStack) |
822 | return true; |
823 | } |
824 | return false; |
825 | } |
826 | |
827 | InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const { |
828 | assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!" ); |
829 | unsigned = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm(); |
830 | return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0); |
831 | } |
832 | |
833 | int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, |
834 | unsigned *GroupNo) const { |
835 | assert(isInlineAsm() && "Expected an inline asm instruction" ); |
836 | assert(OpIdx < getNumOperands() && "OpIdx out of range" ); |
837 | |
838 | // Ignore queries about the initial operands. |
839 | if (OpIdx < InlineAsm::MIOp_FirstOperand) |
840 | return -1; |
841 | |
842 | unsigned Group = 0; |
843 | unsigned NumOps; |
844 | for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; |
845 | i += NumOps) { |
846 | const MachineOperand &FlagMO = getOperand(i); |
847 | // If we reach the implicit register operands, stop looking. |
848 | if (!FlagMO.isImm()) |
849 | return -1; |
850 | const InlineAsm::Flag F(FlagMO.getImm()); |
851 | NumOps = 1 + F.getNumOperandRegisters(); |
852 | if (i + NumOps > OpIdx) { |
853 | if (GroupNo) |
854 | *GroupNo = Group; |
855 | return i; |
856 | } |
857 | ++Group; |
858 | } |
859 | return -1; |
860 | } |
861 | |
862 | const DILabel *MachineInstr::getDebugLabel() const { |
863 | assert(isDebugLabel() && "not a DBG_LABEL" ); |
864 | return cast<DILabel>(Val: getOperand(i: 0).getMetadata()); |
865 | } |
866 | |
867 | const MachineOperand &MachineInstr::getDebugVariableOp() const { |
868 | assert((isDebugValueLike()) && "not a DBG_VALUE*" ); |
869 | unsigned VariableOp = isNonListDebugValue() ? 2 : 0; |
870 | return getOperand(i: VariableOp); |
871 | } |
872 | |
873 | MachineOperand &MachineInstr::getDebugVariableOp() { |
874 | assert((isDebugValueLike()) && "not a DBG_VALUE*" ); |
875 | unsigned VariableOp = isNonListDebugValue() ? 2 : 0; |
876 | return getOperand(i: VariableOp); |
877 | } |
878 | |
879 | const DILocalVariable *MachineInstr::getDebugVariable() const { |
880 | return cast<DILocalVariable>(Val: getDebugVariableOp().getMetadata()); |
881 | } |
882 | |
883 | const MachineOperand &MachineInstr::getDebugExpressionOp() const { |
884 | assert((isDebugValueLike()) && "not a DBG_VALUE*" ); |
885 | unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1; |
886 | return getOperand(i: ExpressionOp); |
887 | } |
888 | |
889 | MachineOperand &MachineInstr::getDebugExpressionOp() { |
890 | assert((isDebugValueLike()) && "not a DBG_VALUE*" ); |
891 | unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1; |
892 | return getOperand(i: ExpressionOp); |
893 | } |
894 | |
895 | const DIExpression *MachineInstr::getDebugExpression() const { |
896 | return cast<DIExpression>(Val: getDebugExpressionOp().getMetadata()); |
897 | } |
898 | |
899 | bool MachineInstr::isDebugEntryValue() const { |
900 | return isDebugValue() && getDebugExpression()->isEntryValue(); |
901 | } |
902 | |
903 | const TargetRegisterClass* |
904 | MachineInstr::getRegClassConstraint(unsigned OpIdx, |
905 | const TargetInstrInfo *TII, |
906 | const TargetRegisterInfo *TRI) const { |
907 | assert(getParent() && "Can't have an MBB reference here!" ); |
908 | assert(getMF() && "Can't have an MF reference here!" ); |
909 | const MachineFunction &MF = *getMF(); |
910 | |
911 | // Most opcodes have fixed constraints in their MCInstrDesc. |
912 | if (!isInlineAsm()) |
913 | return TII->getRegClass(MCID: getDesc(), OpNum: OpIdx, TRI, MF); |
914 | |
915 | if (!getOperand(i: OpIdx).isReg()) |
916 | return nullptr; |
917 | |
918 | // For tied uses on inline asm, get the constraint from the def. |
919 | unsigned DefIdx; |
920 | if (getOperand(i: OpIdx).isUse() && isRegTiedToDefOperand(UseOpIdx: OpIdx, DefOpIdx: &DefIdx)) |
921 | OpIdx = DefIdx; |
922 | |
923 | // Inline asm stores register class constraints in the flag word. |
924 | int FlagIdx = findInlineAsmFlagIdx(OpIdx); |
925 | if (FlagIdx < 0) |
926 | return nullptr; |
927 | |
928 | const InlineAsm::Flag F(getOperand(i: FlagIdx).getImm()); |
929 | unsigned RCID; |
930 | if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) && |
931 | F.hasRegClassConstraint(RC&: RCID)) |
932 | return TRI->getRegClass(i: RCID); |
933 | |
934 | // Assume that all registers in a memory operand are pointers. |
935 | if (F.isMemKind()) |
936 | return TRI->getPointerRegClass(MF); |
937 | |
938 | return nullptr; |
939 | } |
940 | |
941 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg( |
942 | Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, |
943 | const TargetRegisterInfo *TRI, bool ExploreBundle) const { |
944 | // Check every operands inside the bundle if we have |
945 | // been asked to. |
946 | if (ExploreBundle) |
947 | for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC; |
948 | ++OpndIt) |
949 | CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl( |
950 | OpIdx: OpndIt.getOperandNo(), Reg, CurRC, TII, TRI); |
951 | else |
952 | // Otherwise, just check the current operands. |
953 | for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i) |
954 | CurRC = getRegClassConstraintEffectForVRegImpl(OpIdx: i, Reg, CurRC, TII, TRI); |
955 | return CurRC; |
956 | } |
957 | |
958 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl( |
959 | unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, |
960 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { |
961 | assert(CurRC && "Invalid initial register class" ); |
962 | // Check if Reg is constrained by some of its use/def from MI. |
963 | const MachineOperand &MO = getOperand(i: OpIdx); |
964 | if (!MO.isReg() || MO.getReg() != Reg) |
965 | return CurRC; |
966 | // If yes, accumulate the constraints through the operand. |
967 | return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI); |
968 | } |
969 | |
970 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect( |
971 | unsigned OpIdx, const TargetRegisterClass *CurRC, |
972 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { |
973 | const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); |
974 | const MachineOperand &MO = getOperand(i: OpIdx); |
975 | assert(MO.isReg() && |
976 | "Cannot get register constraints for non-register operand" ); |
977 | assert(CurRC && "Invalid initial register class" ); |
978 | if (unsigned SubIdx = MO.getSubReg()) { |
979 | if (OpRC) |
980 | CurRC = TRI->getMatchingSuperRegClass(A: CurRC, B: OpRC, Idx: SubIdx); |
981 | else |
982 | CurRC = TRI->getSubClassWithSubReg(RC: CurRC, Idx: SubIdx); |
983 | } else if (OpRC) |
984 | CurRC = TRI->getCommonSubClass(A: CurRC, B: OpRC); |
985 | return CurRC; |
986 | } |
987 | |
988 | /// Return the number of instructions inside the MI bundle, not counting the |
989 | /// header instruction. |
990 | unsigned MachineInstr::getBundleSize() const { |
991 | MachineBasicBlock::const_instr_iterator I = getIterator(); |
992 | unsigned Size = 0; |
993 | while (I->isBundledWithSucc()) { |
994 | ++Size; |
995 | ++I; |
996 | } |
997 | return Size; |
998 | } |
999 | |
1000 | /// Returns true if the MachineInstr has an implicit-use operand of exactly |
1001 | /// the given register (not considering sub/super-registers). |
1002 | bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const { |
1003 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { |
1004 | const MachineOperand &MO = getOperand(i); |
1005 | if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) |
1006 | return true; |
1007 | } |
1008 | return false; |
1009 | } |
1010 | |
1011 | /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of |
1012 | /// the specific register or -1 if it is not found. It further tightens |
1013 | /// the search criteria to a use that kills the register if isKill is true. |
1014 | int MachineInstr::findRegisterUseOperandIdx( |
1015 | Register Reg, bool isKill, const TargetRegisterInfo *TRI) const { |
1016 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { |
1017 | const MachineOperand &MO = getOperand(i); |
1018 | if (!MO.isReg() || !MO.isUse()) |
1019 | continue; |
1020 | Register MOReg = MO.getReg(); |
1021 | if (!MOReg) |
1022 | continue; |
1023 | if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(RegA: MOReg, RegB: Reg))) |
1024 | if (!isKill || MO.isKill()) |
1025 | return i; |
1026 | } |
1027 | return -1; |
1028 | } |
1029 | |
1030 | /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) |
1031 | /// indicating if this instruction reads or writes Reg. This also considers |
1032 | /// partial defines. |
1033 | std::pair<bool,bool> |
1034 | MachineInstr::readsWritesVirtualRegister(Register Reg, |
1035 | SmallVectorImpl<unsigned> *Ops) const { |
1036 | bool PartDef = false; // Partial redefine. |
1037 | bool FullDef = false; // Full define. |
1038 | bool Use = false; |
1039 | |
1040 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { |
1041 | const MachineOperand &MO = getOperand(i); |
1042 | if (!MO.isReg() || MO.getReg() != Reg) |
1043 | continue; |
1044 | if (Ops) |
1045 | Ops->push_back(Elt: i); |
1046 | if (MO.isUse()) |
1047 | Use |= !MO.isUndef(); |
1048 | else if (MO.getSubReg() && !MO.isUndef()) |
1049 | // A partial def undef doesn't count as reading the register. |
1050 | PartDef = true; |
1051 | else |
1052 | FullDef = true; |
1053 | } |
1054 | // A partial redefine uses Reg unless there is also a full define. |
1055 | return std::make_pair(x: Use || (PartDef && !FullDef), y: PartDef || FullDef); |
1056 | } |
1057 | |
1058 | /// findRegisterDefOperandIdx() - Returns the operand index that is a def of |
1059 | /// the specified register or -1 if it is not found. If isDead is true, defs |
1060 | /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it |
1061 | /// also checks if there is a def of a super-register. |
1062 | int |
1063 | MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap, |
1064 | const TargetRegisterInfo *TRI) const { |
1065 | bool isPhys = Reg.isPhysical(); |
1066 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { |
1067 | const MachineOperand &MO = getOperand(i); |
1068 | // Accept regmask operands when Overlap is set. |
1069 | // Ignore them when looking for a specific def operand (Overlap == false). |
1070 | if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(PhysReg: Reg)) |
1071 | return i; |
1072 | if (!MO.isReg() || !MO.isDef()) |
1073 | continue; |
1074 | Register MOReg = MO.getReg(); |
1075 | bool Found = (MOReg == Reg); |
1076 | if (!Found && TRI && isPhys && MOReg.isPhysical()) { |
1077 | if (Overlap) |
1078 | Found = TRI->regsOverlap(RegA: MOReg, RegB: Reg); |
1079 | else |
1080 | Found = TRI->isSubRegister(RegA: MOReg, RegB: Reg); |
1081 | } |
1082 | if (Found && (!isDead || MO.isDead())) |
1083 | return i; |
1084 | } |
1085 | return -1; |
1086 | } |
1087 | |
1088 | /// findFirstPredOperandIdx() - Find the index of the first operand in the |
1089 | /// operand list that is used to represent the predicate. It returns -1 if |
1090 | /// none is found. |
1091 | int MachineInstr::findFirstPredOperandIdx() const { |
1092 | // Don't call MCID.findFirstPredOperandIdx() because this variant |
1093 | // is sometimes called on an instruction that's not yet complete, and |
1094 | // so the number of operands is less than the MCID indicates. In |
1095 | // particular, the PTX target does this. |
1096 | const MCInstrDesc &MCID = getDesc(); |
1097 | if (MCID.isPredicable()) { |
1098 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) |
1099 | if (MCID.operands()[i].isPredicate()) |
1100 | return i; |
1101 | } |
1102 | |
1103 | return -1; |
1104 | } |
1105 | |
1106 | // MachineOperand::TiedTo is 4 bits wide. |
1107 | const unsigned TiedMax = 15; |
1108 | |
1109 | /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. |
1110 | /// |
1111 | /// Use and def operands can be tied together, indicated by a non-zero TiedTo |
1112 | /// field. TiedTo can have these values: |
1113 | /// |
1114 | /// 0: Operand is not tied to anything. |
1115 | /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). |
1116 | /// TiedMax: Tied to an operand >= TiedMax-1. |
1117 | /// |
1118 | /// The tied def must be one of the first TiedMax operands on a normal |
1119 | /// instruction. INLINEASM instructions allow more tied defs. |
1120 | /// |
1121 | void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { |
1122 | MachineOperand &DefMO = getOperand(i: DefIdx); |
1123 | MachineOperand &UseMO = getOperand(i: UseIdx); |
1124 | assert(DefMO.isDef() && "DefIdx must be a def operand" ); |
1125 | assert(UseMO.isUse() && "UseIdx must be a use operand" ); |
1126 | assert(!DefMO.isTied() && "Def is already tied to another use" ); |
1127 | assert(!UseMO.isTied() && "Use is already tied to another def" ); |
1128 | |
1129 | if (DefIdx < TiedMax) |
1130 | UseMO.TiedTo = DefIdx + 1; |
1131 | else { |
1132 | // Inline asm can use the group descriptors to find tied operands, |
1133 | // statepoint tied operands are trivial to match (1-1 reg def with reg use), |
1134 | // but on normal instruction, the tied def must be within the first TiedMax |
1135 | // operands. |
1136 | assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && |
1137 | "DefIdx out of range" ); |
1138 | UseMO.TiedTo = TiedMax; |
1139 | } |
1140 | |
1141 | // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). |
1142 | DefMO.TiedTo = std::min(a: UseIdx + 1, b: TiedMax); |
1143 | } |
1144 | |
1145 | /// Given the index of a tied register operand, find the operand it is tied to. |
1146 | /// Defs are tied to uses and vice versa. Returns the index of the tied operand |
1147 | /// which must exist. |
1148 | unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { |
1149 | const MachineOperand &MO = getOperand(i: OpIdx); |
1150 | assert(MO.isTied() && "Operand isn't tied" ); |
1151 | |
1152 | // Normally TiedTo is in range. |
1153 | if (MO.TiedTo < TiedMax) |
1154 | return MO.TiedTo - 1; |
1155 | |
1156 | // Uses on normal instructions can be out of range. |
1157 | if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) { |
1158 | // Normal tied defs must be in the 0..TiedMax-1 range. |
1159 | if (MO.isUse()) |
1160 | return TiedMax - 1; |
1161 | // MO is a def. Search for the tied use. |
1162 | for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { |
1163 | const MachineOperand &UseMO = getOperand(i); |
1164 | if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) |
1165 | return i; |
1166 | } |
1167 | llvm_unreachable("Can't find tied use" ); |
1168 | } |
1169 | |
1170 | if (getOpcode() == TargetOpcode::STATEPOINT) { |
1171 | // In STATEPOINT defs correspond 1-1 to GC pointer operands passed |
1172 | // on registers. |
1173 | StatepointOpers SO(this); |
1174 | unsigned CurUseIdx = SO.getFirstGCPtrIdx(); |
1175 | assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied" ); |
1176 | unsigned NumDefs = getNumDefs(); |
1177 | for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) { |
1178 | while (!getOperand(i: CurUseIdx).isReg()) |
1179 | CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx); |
1180 | if (OpIdx == CurDefIdx) |
1181 | return CurUseIdx; |
1182 | if (OpIdx == CurUseIdx) |
1183 | return CurDefIdx; |
1184 | CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx); |
1185 | } |
1186 | llvm_unreachable("Can't find tied use" ); |
1187 | } |
1188 | |
1189 | // Now deal with inline asm by parsing the operand group descriptor flags. |
1190 | // Find the beginning of each operand group. |
1191 | SmallVector<unsigned, 8> GroupIdx; |
1192 | unsigned OpIdxGroup = ~0u; |
1193 | unsigned NumOps; |
1194 | for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; |
1195 | i += NumOps) { |
1196 | const MachineOperand &FlagMO = getOperand(i); |
1197 | assert(FlagMO.isImm() && "Invalid tied operand on inline asm" ); |
1198 | unsigned CurGroup = GroupIdx.size(); |
1199 | GroupIdx.push_back(Elt: i); |
1200 | const InlineAsm::Flag F(FlagMO.getImm()); |
1201 | NumOps = 1 + F.getNumOperandRegisters(); |
1202 | // OpIdx belongs to this operand group. |
1203 | if (OpIdx > i && OpIdx < i + NumOps) |
1204 | OpIdxGroup = CurGroup; |
1205 | unsigned TiedGroup; |
1206 | if (!F.isUseOperandTiedToDef(Idx&: TiedGroup)) |
1207 | continue; |
1208 | // Operands in this group are tied to operands in TiedGroup which must be |
1209 | // earlier. Find the number of operands between the two groups. |
1210 | unsigned Delta = i - GroupIdx[TiedGroup]; |
1211 | |
1212 | // OpIdx is a use tied to TiedGroup. |
1213 | if (OpIdxGroup == CurGroup) |
1214 | return OpIdx - Delta; |
1215 | |
1216 | // OpIdx is a def tied to this use group. |
1217 | if (OpIdxGroup == TiedGroup) |
1218 | return OpIdx + Delta; |
1219 | } |
1220 | llvm_unreachable("Invalid tied operand on inline asm" ); |
1221 | } |
1222 | |
1223 | /// clearKillInfo - Clears kill flags on all operands. |
1224 | /// |
1225 | void MachineInstr::clearKillInfo() { |
1226 | for (MachineOperand &MO : operands()) { |
1227 | if (MO.isReg() && MO.isUse()) |
1228 | MO.setIsKill(false); |
1229 | } |
1230 | } |
1231 | |
1232 | void MachineInstr::substituteRegister(Register FromReg, Register ToReg, |
1233 | unsigned SubIdx, |
1234 | const TargetRegisterInfo &RegInfo) { |
1235 | if (ToReg.isPhysical()) { |
1236 | if (SubIdx) |
1237 | ToReg = RegInfo.getSubReg(Reg: ToReg, Idx: SubIdx); |
1238 | for (MachineOperand &MO : operands()) { |
1239 | if (!MO.isReg() || MO.getReg() != FromReg) |
1240 | continue; |
1241 | MO.substPhysReg(Reg: ToReg, RegInfo); |
1242 | } |
1243 | } else { |
1244 | for (MachineOperand &MO : operands()) { |
1245 | if (!MO.isReg() || MO.getReg() != FromReg) |
1246 | continue; |
1247 | MO.substVirtReg(Reg: ToReg, SubIdx, RegInfo); |
1248 | } |
1249 | } |
1250 | } |
1251 | |
1252 | /// isSafeToMove - Return true if it is safe to move this instruction. If |
1253 | /// SawStore is set to true, it means that there is a store (or call) between |
1254 | /// the instruction's location and its intended destination. |
1255 | bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const { |
1256 | // Ignore stuff that we obviously can't move. |
1257 | // |
1258 | // Treat volatile loads as stores. This is not strictly necessary for |
1259 | // volatiles, but it is required for atomic loads. It is not allowed to move |
1260 | // a load across an atomic load with Ordering > Monotonic. |
1261 | if (mayStore() || isCall() || isPHI() || |
1262 | (mayLoad() && hasOrderedMemoryRef())) { |
1263 | SawStore = true; |
1264 | return false; |
1265 | } |
1266 | |
1267 | if (isPosition() || isDebugInstr() || isTerminator() || |
1268 | mayRaiseFPException() || hasUnmodeledSideEffects() || |
1269 | isJumpTableDebugInfo()) |
1270 | return false; |
1271 | |
1272 | // See if this instruction does a load. If so, we have to guarantee that the |
1273 | // loaded value doesn't change between the load and the its intended |
1274 | // destination. The check for isInvariantLoad gives the target the chance to |
1275 | // classify the load as always returning a constant, e.g. a constant pool |
1276 | // load. |
1277 | if (mayLoad() && !isDereferenceableInvariantLoad()) |
1278 | // Otherwise, this is a real load. If there is a store between the load and |
1279 | // end of block, we can't move it. |
1280 | return !SawStore; |
1281 | |
1282 | return true; |
1283 | } |
1284 | |
1285 | static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, |
1286 | bool UseTBAA, const MachineMemOperand *MMOa, |
1287 | const MachineMemOperand *MMOb) { |
1288 | // The following interface to AA is fashioned after DAGCombiner::isAlias and |
1289 | // operates with MachineMemOperand offset with some important assumptions: |
1290 | // - LLVM fundamentally assumes flat address spaces. |
1291 | // - MachineOperand offset can *only* result from legalization and cannot |
1292 | // affect queries other than the trivial case of overlap checking. |
1293 | // - These offsets never wrap and never step outside of allocated objects. |
1294 | // - There should never be any negative offsets here. |
1295 | // |
1296 | // FIXME: Modify API to hide this math from "user" |
1297 | // Even before we go to AA we can reason locally about some memory objects. It |
1298 | // can save compile time, and possibly catch some corner cases not currently |
1299 | // covered. |
1300 | |
1301 | int64_t OffsetA = MMOa->getOffset(); |
1302 | int64_t OffsetB = MMOb->getOffset(); |
1303 | int64_t MinOffset = std::min(a: OffsetA, b: OffsetB); |
1304 | |
1305 | uint64_t WidthA = MMOa->getSize(); |
1306 | uint64_t WidthB = MMOb->getSize(); |
1307 | bool KnownWidthA = WidthA != MemoryLocation::UnknownSize; |
1308 | bool KnownWidthB = WidthB != MemoryLocation::UnknownSize; |
1309 | |
1310 | const Value *ValA = MMOa->getValue(); |
1311 | const Value *ValB = MMOb->getValue(); |
1312 | bool SameVal = (ValA && ValB && (ValA == ValB)); |
1313 | if (!SameVal) { |
1314 | const PseudoSourceValue *PSVa = MMOa->getPseudoValue(); |
1315 | const PseudoSourceValue *PSVb = MMOb->getPseudoValue(); |
1316 | if (PSVa && ValB && !PSVa->mayAlias(&MFI)) |
1317 | return false; |
1318 | if (PSVb && ValA && !PSVb->mayAlias(&MFI)) |
1319 | return false; |
1320 | if (PSVa && PSVb && (PSVa == PSVb)) |
1321 | SameVal = true; |
1322 | } |
1323 | |
1324 | if (SameVal) { |
1325 | if (!KnownWidthA || !KnownWidthB) |
1326 | return true; |
1327 | int64_t MaxOffset = std::max(a: OffsetA, b: OffsetB); |
1328 | int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB; |
1329 | return (MinOffset + LowWidth > MaxOffset); |
1330 | } |
1331 | |
1332 | if (!AA) |
1333 | return true; |
1334 | |
1335 | if (!ValA || !ValB) |
1336 | return true; |
1337 | |
1338 | assert((OffsetA >= 0) && "Negative MachineMemOperand offset" ); |
1339 | assert((OffsetB >= 0) && "Negative MachineMemOperand offset" ); |
1340 | |
1341 | int64_t OverlapA = |
1342 | KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize; |
1343 | int64_t OverlapB = |
1344 | KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize; |
1345 | |
1346 | return !AA->isNoAlias( |
1347 | LocA: MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()), |
1348 | LocB: MemoryLocation(ValB, OverlapB, |
1349 | UseTBAA ? MMOb->getAAInfo() : AAMDNodes())); |
1350 | } |
1351 | |
1352 | bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other, |
1353 | bool UseTBAA) const { |
1354 | const MachineFunction *MF = getMF(); |
1355 | const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); |
1356 | const MachineFrameInfo &MFI = MF->getFrameInfo(); |
1357 | |
1358 | // Exclude call instruction which may alter the memory but can not be handled |
1359 | // by this function. |
1360 | if (isCall() || Other.isCall()) |
1361 | return true; |
1362 | |
1363 | // If neither instruction stores to memory, they can't alias in any |
1364 | // meaningful way, even if they read from the same address. |
1365 | if (!mayStore() && !Other.mayStore()) |
1366 | return false; |
1367 | |
1368 | // Both instructions must be memory operations to be able to alias. |
1369 | if (!mayLoadOrStore() || !Other.mayLoadOrStore()) |
1370 | return false; |
1371 | |
1372 | // Let the target decide if memory accesses cannot possibly overlap. |
1373 | if (TII->areMemAccessesTriviallyDisjoint(MIa: *this, MIb: Other)) |
1374 | return false; |
1375 | |
1376 | // Memory operations without memory operands may access anything. Be |
1377 | // conservative and assume `MayAlias`. |
1378 | if (memoperands_empty() || Other.memoperands_empty()) |
1379 | return true; |
1380 | |
1381 | // Skip if there are too many memory operands. |
1382 | auto NumChecks = getNumMemOperands() * Other.getNumMemOperands(); |
1383 | if (NumChecks > TII->getMemOperandAACheckLimit()) |
1384 | return true; |
1385 | |
1386 | // Check each pair of memory operands from both instructions, which can't |
1387 | // alias only if all pairs won't alias. |
1388 | for (auto *MMOa : memoperands()) |
1389 | for (auto *MMOb : Other.memoperands()) |
1390 | if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb)) |
1391 | return true; |
1392 | |
1393 | return false; |
1394 | } |
1395 | |
1396 | /// hasOrderedMemoryRef - Return true if this instruction may have an ordered |
1397 | /// or volatile memory reference, or if the information describing the memory |
1398 | /// reference is not available. Return false if it is known to have no ordered |
1399 | /// memory references. |
1400 | bool MachineInstr::hasOrderedMemoryRef() const { |
1401 | // An instruction known never to access memory won't have a volatile access. |
1402 | if (!mayStore() && |
1403 | !mayLoad() && |
1404 | !isCall() && |
1405 | !hasUnmodeledSideEffects()) |
1406 | return false; |
1407 | |
1408 | // Otherwise, if the instruction has no memory reference information, |
1409 | // conservatively assume it wasn't preserved. |
1410 | if (memoperands_empty()) |
1411 | return true; |
1412 | |
1413 | // Check if any of our memory operands are ordered. |
1414 | return llvm::any_of(Range: memoperands(), P: [](const MachineMemOperand *MMO) { |
1415 | return !MMO->isUnordered(); |
1416 | }); |
1417 | } |
1418 | |
1419 | /// isDereferenceableInvariantLoad - Return true if this instruction will never |
1420 | /// trap and is loading from a location whose value is invariant across a run of |
1421 | /// this function. |
1422 | bool MachineInstr::isDereferenceableInvariantLoad() const { |
1423 | // If the instruction doesn't load at all, it isn't an invariant load. |
1424 | if (!mayLoad()) |
1425 | return false; |
1426 | |
1427 | // If the instruction has lost its memoperands, conservatively assume that |
1428 | // it may not be an invariant load. |
1429 | if (memoperands_empty()) |
1430 | return false; |
1431 | |
1432 | const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo(); |
1433 | |
1434 | for (MachineMemOperand *MMO : memoperands()) { |
1435 | if (!MMO->isUnordered()) |
1436 | // If the memory operand has ordering side effects, we can't move the |
1437 | // instruction. Such an instruction is technically an invariant load, |
1438 | // but the caller code would need updated to expect that. |
1439 | return false; |
1440 | if (MMO->isStore()) return false; |
1441 | if (MMO->isInvariant() && MMO->isDereferenceable()) |
1442 | continue; |
1443 | |
1444 | // A load from a constant PseudoSourceValue is invariant. |
1445 | if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) { |
1446 | if (PSV->isConstant(&MFI)) |
1447 | continue; |
1448 | } |
1449 | |
1450 | // Otherwise assume conservatively. |
1451 | return false; |
1452 | } |
1453 | |
1454 | // Everything checks out. |
1455 | return true; |
1456 | } |
1457 | |
1458 | /// isConstantValuePHI - If the specified instruction is a PHI that always |
1459 | /// merges together the same virtual register, return the register, otherwise |
1460 | /// return 0. |
1461 | unsigned MachineInstr::isConstantValuePHI() const { |
1462 | if (!isPHI()) |
1463 | return 0; |
1464 | assert(getNumOperands() >= 3 && |
1465 | "It's illegal to have a PHI without source operands" ); |
1466 | |
1467 | Register Reg = getOperand(i: 1).getReg(); |
1468 | for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) |
1469 | if (getOperand(i).getReg() != Reg) |
1470 | return 0; |
1471 | return Reg; |
1472 | } |
1473 | |
1474 | bool MachineInstr::hasUnmodeledSideEffects() const { |
1475 | if (hasProperty(MCFlag: MCID::UnmodeledSideEffects)) |
1476 | return true; |
1477 | if (isInlineAsm()) { |
1478 | unsigned = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm(); |
1479 | if (ExtraInfo & InlineAsm::Extra_HasSideEffects) |
1480 | return true; |
1481 | } |
1482 | |
1483 | return false; |
1484 | } |
1485 | |
1486 | bool MachineInstr::isLoadFoldBarrier() const { |
1487 | return mayStore() || isCall() || |
1488 | (hasUnmodeledSideEffects() && !isPseudoProbe()); |
1489 | } |
1490 | |
1491 | /// allDefsAreDead - Return true if all the defs of this instruction are dead. |
1492 | /// |
1493 | bool MachineInstr::allDefsAreDead() const { |
1494 | for (const MachineOperand &MO : operands()) { |
1495 | if (!MO.isReg() || MO.isUse()) |
1496 | continue; |
1497 | if (!MO.isDead()) |
1498 | return false; |
1499 | } |
1500 | return true; |
1501 | } |
1502 | |
1503 | bool MachineInstr::allImplicitDefsAreDead() const { |
1504 | for (const MachineOperand &MO : implicit_operands()) { |
1505 | if (!MO.isReg() || MO.isUse()) |
1506 | continue; |
1507 | if (!MO.isDead()) |
1508 | return false; |
1509 | } |
1510 | return true; |
1511 | } |
1512 | |
1513 | /// copyImplicitOps - Copy implicit register operands from specified |
1514 | /// instruction to this instruction. |
1515 | void MachineInstr::copyImplicitOps(MachineFunction &MF, |
1516 | const MachineInstr &MI) { |
1517 | for (const MachineOperand &MO : |
1518 | llvm::drop_begin(RangeOrContainer: MI.operands(), N: MI.getDesc().getNumOperands())) |
1519 | if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) |
1520 | addOperand(MF, Op: MO); |
1521 | } |
1522 | |
1523 | bool MachineInstr::hasComplexRegisterTies() const { |
1524 | const MCInstrDesc &MCID = getDesc(); |
1525 | if (MCID.Opcode == TargetOpcode::STATEPOINT) |
1526 | return true; |
1527 | for (unsigned I = 0, E = getNumOperands(); I < E; ++I) { |
1528 | const auto &Operand = getOperand(i: I); |
1529 | if (!Operand.isReg() || Operand.isDef()) |
1530 | // Ignore the defined registers as MCID marks only the uses as tied. |
1531 | continue; |
1532 | int ExpectedTiedIdx = MCID.getOperandConstraint(OpNum: I, Constraint: MCOI::TIED_TO); |
1533 | int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(OpIdx: I)) : -1; |
1534 | if (ExpectedTiedIdx != TiedIdx) |
1535 | return true; |
1536 | } |
1537 | return false; |
1538 | } |
1539 | |
1540 | LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, |
1541 | const MachineRegisterInfo &MRI) const { |
1542 | const MachineOperand &Op = getOperand(i: OpIdx); |
1543 | if (!Op.isReg()) |
1544 | return LLT{}; |
1545 | |
1546 | if (isVariadic() || OpIdx >= getNumExplicitOperands()) |
1547 | return MRI.getType(Reg: Op.getReg()); |
1548 | |
1549 | auto &OpInfo = getDesc().operands()[OpIdx]; |
1550 | if (!OpInfo.isGenericType()) |
1551 | return MRI.getType(Reg: Op.getReg()); |
1552 | |
1553 | if (PrintedTypes[OpInfo.getGenericTypeIndex()]) |
1554 | return LLT{}; |
1555 | |
1556 | LLT TypeToPrint = MRI.getType(Reg: Op.getReg()); |
1557 | // Don't mark the type index printed if it wasn't actually printed: maybe |
1558 | // another operand with the same type index has an actual type attached: |
1559 | if (TypeToPrint.isValid()) |
1560 | PrintedTypes.set(OpInfo.getGenericTypeIndex()); |
1561 | return TypeToPrint; |
1562 | } |
1563 | |
1564 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
1565 | LLVM_DUMP_METHOD void MachineInstr::dump() const { |
1566 | dbgs() << " " ; |
1567 | print(OS&: dbgs()); |
1568 | } |
1569 | |
1570 | LLVM_DUMP_METHOD void MachineInstr::dumprImpl( |
1571 | const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth, |
1572 | SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const { |
1573 | if (Depth >= MaxDepth) |
1574 | return; |
1575 | if (!AlreadySeenInstrs.insert(Ptr: this).second) |
1576 | return; |
1577 | // PadToColumn always inserts at least one space. |
1578 | // Don't mess up the alignment if we don't want any space. |
1579 | if (Depth) |
1580 | fdbgs().PadToColumn(NewCol: Depth * 2); |
1581 | print(OS&: fdbgs()); |
1582 | for (const MachineOperand &MO : operands()) { |
1583 | if (!MO.isReg() || MO.isDef()) |
1584 | continue; |
1585 | Register Reg = MO.getReg(); |
1586 | if (Reg.isPhysical()) |
1587 | continue; |
1588 | const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg); |
1589 | if (NewMI == nullptr) |
1590 | continue; |
1591 | NewMI->dumprImpl(MRI, Depth: Depth + 1, MaxDepth, AlreadySeenInstrs); |
1592 | } |
1593 | } |
1594 | |
1595 | LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI, |
1596 | unsigned MaxDepth) const { |
1597 | SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs; |
1598 | dumprImpl(MRI, Depth: 0, MaxDepth, AlreadySeenInstrs); |
1599 | } |
1600 | #endif |
1601 | |
1602 | void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers, |
1603 | bool SkipDebugLoc, bool AddNewLine, |
1604 | const TargetInstrInfo *TII) const { |
1605 | const Module *M = nullptr; |
1606 | const Function *F = nullptr; |
1607 | if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) { |
1608 | F = &MF->getFunction(); |
1609 | M = F->getParent(); |
1610 | if (!TII) |
1611 | TII = MF->getSubtarget().getInstrInfo(); |
1612 | } |
1613 | |
1614 | ModuleSlotTracker MST(M); |
1615 | if (F) |
1616 | MST.incorporateFunction(F: *F); |
1617 | print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII); |
1618 | } |
1619 | |
1620 | void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, |
1621 | bool IsStandalone, bool SkipOpers, bool SkipDebugLoc, |
1622 | bool AddNewLine, const TargetInstrInfo *TII) const { |
1623 | // We can be a bit tidier if we know the MachineFunction. |
1624 | const TargetRegisterInfo *TRI = nullptr; |
1625 | const MachineRegisterInfo *MRI = nullptr; |
1626 | const TargetIntrinsicInfo *IntrinsicInfo = nullptr; |
1627 | tryToGetTargetInfo(MI: *this, TRI, MRI, IntrinsicInfo, TII); |
1628 | |
1629 | if (isCFIInstruction()) |
1630 | assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction" ); |
1631 | |
1632 | SmallBitVector PrintedTypes(8); |
1633 | bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies(); |
1634 | auto getTiedOperandIdx = [&](unsigned OpIdx) { |
1635 | if (!ShouldPrintRegisterTies) |
1636 | return 0U; |
1637 | const MachineOperand &MO = getOperand(i: OpIdx); |
1638 | if (MO.isReg() && MO.isTied() && !MO.isDef()) |
1639 | return findTiedOperandIdx(OpIdx); |
1640 | return 0U; |
1641 | }; |
1642 | unsigned StartOp = 0; |
1643 | unsigned e = getNumOperands(); |
1644 | |
1645 | // Print explicitly defined operands on the left of an assignment syntax. |
1646 | while (StartOp < e) { |
1647 | const MachineOperand &MO = getOperand(i: StartOp); |
1648 | if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) |
1649 | break; |
1650 | |
1651 | if (StartOp != 0) |
1652 | OS << ", " ; |
1653 | |
1654 | LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: StartOp, PrintedTypes, MRI: *MRI) : LLT{}; |
1655 | unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); |
1656 | MO.print(os&: OS, MST, TypeToPrint, OpIdx: StartOp, /*PrintDef=*/false, IsStandalone, |
1657 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); |
1658 | ++StartOp; |
1659 | } |
1660 | |
1661 | if (StartOp != 0) |
1662 | OS << " = " ; |
1663 | |
1664 | if (getFlag(Flag: MachineInstr::FrameSetup)) |
1665 | OS << "frame-setup " ; |
1666 | if (getFlag(Flag: MachineInstr::FrameDestroy)) |
1667 | OS << "frame-destroy " ; |
1668 | if (getFlag(Flag: MachineInstr::FmNoNans)) |
1669 | OS << "nnan " ; |
1670 | if (getFlag(Flag: MachineInstr::FmNoInfs)) |
1671 | OS << "ninf " ; |
1672 | if (getFlag(Flag: MachineInstr::FmNsz)) |
1673 | OS << "nsz " ; |
1674 | if (getFlag(Flag: MachineInstr::FmArcp)) |
1675 | OS << "arcp " ; |
1676 | if (getFlag(Flag: MachineInstr::FmContract)) |
1677 | OS << "contract " ; |
1678 | if (getFlag(Flag: MachineInstr::FmAfn)) |
1679 | OS << "afn " ; |
1680 | if (getFlag(Flag: MachineInstr::FmReassoc)) |
1681 | OS << "reassoc " ; |
1682 | if (getFlag(Flag: MachineInstr::NoUWrap)) |
1683 | OS << "nuw " ; |
1684 | if (getFlag(Flag: MachineInstr::NoSWrap)) |
1685 | OS << "nsw " ; |
1686 | if (getFlag(Flag: MachineInstr::IsExact)) |
1687 | OS << "exact " ; |
1688 | if (getFlag(Flag: MachineInstr::NoFPExcept)) |
1689 | OS << "nofpexcept " ; |
1690 | if (getFlag(Flag: MachineInstr::NoMerge)) |
1691 | OS << "nomerge " ; |
1692 | |
1693 | // Print the opcode name. |
1694 | if (TII) |
1695 | OS << TII->getName(Opcode: getOpcode()); |
1696 | else |
1697 | OS << "UNKNOWN" ; |
1698 | |
1699 | if (SkipOpers) |
1700 | return; |
1701 | |
1702 | // Print the rest of the operands. |
1703 | bool FirstOp = true; |
1704 | unsigned AsmDescOp = ~0u; |
1705 | unsigned AsmOpCount = 0; |
1706 | |
1707 | if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { |
1708 | // Print asm string. |
1709 | OS << " " ; |
1710 | const unsigned OpIdx = InlineAsm::MIOp_AsmString; |
1711 | LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, MRI: *MRI) : LLT{}; |
1712 | unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx); |
1713 | getOperand(i: OpIdx).print(os&: OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone, |
1714 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, |
1715 | IntrinsicInfo); |
1716 | |
1717 | // Print HasSideEffects, MayLoad, MayStore, IsAlignStack |
1718 | unsigned = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm(); |
1719 | if (ExtraInfo & InlineAsm::Extra_HasSideEffects) |
1720 | OS << " [sideeffect]" ; |
1721 | if (ExtraInfo & InlineAsm::Extra_MayLoad) |
1722 | OS << " [mayload]" ; |
1723 | if (ExtraInfo & InlineAsm::Extra_MayStore) |
1724 | OS << " [maystore]" ; |
1725 | if (ExtraInfo & InlineAsm::Extra_IsConvergent) |
1726 | OS << " [isconvergent]" ; |
1727 | if (ExtraInfo & InlineAsm::Extra_IsAlignStack) |
1728 | OS << " [alignstack]" ; |
1729 | if (getInlineAsmDialect() == InlineAsm::AD_ATT) |
1730 | OS << " [attdialect]" ; |
1731 | if (getInlineAsmDialect() == InlineAsm::AD_Intel) |
1732 | OS << " [inteldialect]" ; |
1733 | |
1734 | StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; |
1735 | FirstOp = false; |
1736 | } |
1737 | |
1738 | for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { |
1739 | const MachineOperand &MO = getOperand(i); |
1740 | |
1741 | if (FirstOp) FirstOp = false; else OS << "," ; |
1742 | OS << " " ; |
1743 | |
1744 | if (isDebugValueLike() && MO.isMetadata()) { |
1745 | // Pretty print DBG_VALUE* instructions. |
1746 | auto *DIV = dyn_cast<DILocalVariable>(Val: MO.getMetadata()); |
1747 | if (DIV && !DIV->getName().empty()) |
1748 | OS << "!\"" << DIV->getName() << '\"'; |
1749 | else { |
1750 | LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{}; |
1751 | unsigned TiedOperandIdx = getTiedOperandIdx(i); |
1752 | MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone, |
1753 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); |
1754 | } |
1755 | } else if (isDebugLabel() && MO.isMetadata()) { |
1756 | // Pretty print DBG_LABEL instructions. |
1757 | auto *DIL = dyn_cast<DILabel>(Val: MO.getMetadata()); |
1758 | if (DIL && !DIL->getName().empty()) |
1759 | OS << "\"" << DIL->getName() << '\"'; |
1760 | else { |
1761 | LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{}; |
1762 | unsigned TiedOperandIdx = getTiedOperandIdx(i); |
1763 | MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone, |
1764 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); |
1765 | } |
1766 | } else if (i == AsmDescOp && MO.isImm()) { |
1767 | // Pretty print the inline asm operand descriptor. |
1768 | OS << '$' << AsmOpCount++; |
1769 | unsigned Flag = MO.getImm(); |
1770 | const InlineAsm::Flag F(Flag); |
1771 | OS << ":[" ; |
1772 | OS << F.getKindName(); |
1773 | |
1774 | unsigned RCID; |
1775 | if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RC&: RCID)) { |
1776 | if (TRI) { |
1777 | OS << ':' << TRI->getRegClassName(Class: TRI->getRegClass(i: RCID)); |
1778 | } else |
1779 | OS << ":RC" << RCID; |
1780 | } |
1781 | |
1782 | if (F.isMemKind()) { |
1783 | const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID(); |
1784 | OS << ":" << InlineAsm::getMemConstraintName(C: MCID); |
1785 | } |
1786 | |
1787 | unsigned TiedTo; |
1788 | if (F.isUseOperandTiedToDef(Idx&: TiedTo)) |
1789 | OS << " tiedto:$" << TiedTo; |
1790 | |
1791 | if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() || |
1792 | F.isRegUseKind()) && |
1793 | F.getRegMayBeFolded()) { |
1794 | OS << " foldable" ; |
1795 | } |
1796 | |
1797 | OS << ']'; |
1798 | |
1799 | // Compute the index of the next operand descriptor. |
1800 | AsmDescOp += 1 + F.getNumOperandRegisters(); |
1801 | } else { |
1802 | LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{}; |
1803 | unsigned TiedOperandIdx = getTiedOperandIdx(i); |
1804 | if (MO.isImm() && isOperandSubregIdx(OpIdx: i)) |
1805 | MachineOperand::printSubRegIdx(OS, Index: MO.getImm(), TRI); |
1806 | else |
1807 | MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone, |
1808 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); |
1809 | } |
1810 | } |
1811 | |
1812 | // Print any optional symbols attached to this instruction as-if they were |
1813 | // operands. |
1814 | if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) { |
1815 | if (!FirstOp) { |
1816 | FirstOp = false; |
1817 | OS << ','; |
1818 | } |
1819 | OS << " pre-instr-symbol " ; |
1820 | MachineOperand::printSymbol(OS, Sym&: *PreInstrSymbol); |
1821 | } |
1822 | if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) { |
1823 | if (!FirstOp) { |
1824 | FirstOp = false; |
1825 | OS << ','; |
1826 | } |
1827 | OS << " post-instr-symbol " ; |
1828 | MachineOperand::printSymbol(OS, Sym&: *PostInstrSymbol); |
1829 | } |
1830 | if (MDNode *HeapAllocMarker = getHeapAllocMarker()) { |
1831 | if (!FirstOp) { |
1832 | FirstOp = false; |
1833 | OS << ','; |
1834 | } |
1835 | OS << " heap-alloc-marker " ; |
1836 | HeapAllocMarker->printAsOperand(OS, MST); |
1837 | } |
1838 | if (MDNode *PCSections = getPCSections()) { |
1839 | if (!FirstOp) { |
1840 | FirstOp = false; |
1841 | OS << ','; |
1842 | } |
1843 | OS << " pcsections " ; |
1844 | PCSections->printAsOperand(OS, MST); |
1845 | } |
1846 | if (uint32_t CFIType = getCFIType()) { |
1847 | if (!FirstOp) |
1848 | OS << ','; |
1849 | OS << " cfi-type " << CFIType; |
1850 | } |
1851 | |
1852 | if (DebugInstrNum) { |
1853 | if (!FirstOp) |
1854 | OS << "," ; |
1855 | OS << " debug-instr-number " << DebugInstrNum; |
1856 | } |
1857 | |
1858 | if (!SkipDebugLoc) { |
1859 | if (const DebugLoc &DL = getDebugLoc()) { |
1860 | if (!FirstOp) |
1861 | OS << ','; |
1862 | OS << " debug-location " ; |
1863 | DL->printAsOperand(OS, MST); |
1864 | } |
1865 | } |
1866 | |
1867 | if (!memoperands_empty()) { |
1868 | SmallVector<StringRef, 0> SSNs; |
1869 | const LLVMContext *Context = nullptr; |
1870 | std::unique_ptr<LLVMContext> CtxPtr; |
1871 | const MachineFrameInfo *MFI = nullptr; |
1872 | if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) { |
1873 | MFI = &MF->getFrameInfo(); |
1874 | Context = &MF->getFunction().getContext(); |
1875 | } else { |
1876 | CtxPtr = std::make_unique<LLVMContext>(); |
1877 | Context = CtxPtr.get(); |
1878 | } |
1879 | |
1880 | OS << " :: " ; |
1881 | bool NeedComma = false; |
1882 | for (const MachineMemOperand *Op : memoperands()) { |
1883 | if (NeedComma) |
1884 | OS << ", " ; |
1885 | Op->print(OS, MST, SSNs, Context: *Context, MFI, TII); |
1886 | NeedComma = true; |
1887 | } |
1888 | } |
1889 | |
1890 | if (SkipDebugLoc) |
1891 | return; |
1892 | |
1893 | bool HaveSemi = false; |
1894 | |
1895 | // Print debug location information. |
1896 | if (const DebugLoc &DL = getDebugLoc()) { |
1897 | if (!HaveSemi) { |
1898 | OS << ';'; |
1899 | HaveSemi = true; |
1900 | } |
1901 | OS << ' '; |
1902 | DL.print(OS); |
1903 | } |
1904 | |
1905 | // Print extra comments for DEBUG_VALUE and friends if they are well-formed. |
1906 | if ((isNonListDebugValue() && getNumOperands() >= 4) || |
1907 | (isDebugValueList() && getNumOperands() >= 2) || |
1908 | (isDebugRef() && getNumOperands() >= 3)) { |
1909 | if (getDebugVariableOp().isMetadata()) { |
1910 | if (!HaveSemi) { |
1911 | OS << ";" ; |
1912 | HaveSemi = true; |
1913 | } |
1914 | auto *DV = getDebugVariable(); |
1915 | OS << " line no:" << DV->getLine(); |
1916 | if (isIndirectDebugValue()) |
1917 | OS << " indirect" ; |
1918 | } |
1919 | } |
1920 | // TODO: DBG_LABEL |
1921 | |
1922 | if (AddNewLine) |
1923 | OS << '\n'; |
1924 | } |
1925 | |
1926 | bool MachineInstr::addRegisterKilled(Register IncomingReg, |
1927 | const TargetRegisterInfo *RegInfo, |
1928 | bool AddIfNotFound) { |
1929 | bool isPhysReg = IncomingReg.isPhysical(); |
1930 | bool hasAliases = isPhysReg && |
1931 | MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); |
1932 | bool Found = false; |
1933 | SmallVector<unsigned,4> DeadOps; |
1934 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { |
1935 | MachineOperand &MO = getOperand(i); |
1936 | if (!MO.isReg() || !MO.isUse() || MO.isUndef()) |
1937 | continue; |
1938 | |
1939 | // DEBUG_VALUE nodes do not contribute to code generation and should |
1940 | // always be ignored. Failure to do so may result in trying to modify |
1941 | // KILL flags on DEBUG_VALUE nodes. |
1942 | if (MO.isDebug()) |
1943 | continue; |
1944 | |
1945 | Register Reg = MO.getReg(); |
1946 | if (!Reg) |
1947 | continue; |
1948 | |
1949 | if (Reg == IncomingReg) { |
1950 | if (!Found) { |
1951 | if (MO.isKill()) |
1952 | // The register is already marked kill. |
1953 | return true; |
1954 | if (isPhysReg && isRegTiedToDefOperand(UseOpIdx: i)) |
1955 | // Two-address uses of physregs must not be marked kill. |
1956 | return true; |
1957 | MO.setIsKill(); |
1958 | Found = true; |
1959 | } |
1960 | } else if (hasAliases && MO.isKill() && Reg.isPhysical()) { |
1961 | // A super-register kill already exists. |
1962 | if (RegInfo->isSuperRegister(RegA: IncomingReg, RegB: Reg)) |
1963 | return true; |
1964 | if (RegInfo->isSubRegister(RegA: IncomingReg, RegB: Reg)) |
1965 | DeadOps.push_back(Elt: i); |
1966 | } |
1967 | } |
1968 | |
1969 | // Trim unneeded kill operands. |
1970 | while (!DeadOps.empty()) { |
1971 | unsigned OpIdx = DeadOps.back(); |
1972 | if (getOperand(i: OpIdx).isImplicit() && |
1973 | (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) |
1974 | removeOperand(OpNo: OpIdx); |
1975 | else |
1976 | getOperand(i: OpIdx).setIsKill(false); |
1977 | DeadOps.pop_back(); |
1978 | } |
1979 | |
1980 | // If not found, this means an alias of one of the operands is killed. Add a |
1981 | // new implicit operand if required. |
1982 | if (!Found && AddIfNotFound) { |
1983 | addOperand(Op: MachineOperand::CreateReg(Reg: IncomingReg, |
1984 | isDef: false /*IsDef*/, |
1985 | isImp: true /*IsImp*/, |
1986 | isKill: true /*IsKill*/)); |
1987 | return true; |
1988 | } |
1989 | return Found; |
1990 | } |
1991 | |
1992 | void MachineInstr::clearRegisterKills(Register Reg, |
1993 | const TargetRegisterInfo *RegInfo) { |
1994 | if (!Reg.isPhysical()) |
1995 | RegInfo = nullptr; |
1996 | for (MachineOperand &MO : operands()) { |
1997 | if (!MO.isReg() || !MO.isUse() || !MO.isKill()) |
1998 | continue; |
1999 | Register OpReg = MO.getReg(); |
2000 | if ((RegInfo && RegInfo->regsOverlap(RegA: Reg, RegB: OpReg)) || Reg == OpReg) |
2001 | MO.setIsKill(false); |
2002 | } |
2003 | } |
2004 | |
2005 | bool MachineInstr::addRegisterDead(Register Reg, |
2006 | const TargetRegisterInfo *RegInfo, |
2007 | bool AddIfNotFound) { |
2008 | bool isPhysReg = Reg.isPhysical(); |
2009 | bool hasAliases = isPhysReg && |
2010 | MCRegAliasIterator(Reg, RegInfo, false).isValid(); |
2011 | bool Found = false; |
2012 | SmallVector<unsigned,4> DeadOps; |
2013 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { |
2014 | MachineOperand &MO = getOperand(i); |
2015 | if (!MO.isReg() || !MO.isDef()) |
2016 | continue; |
2017 | Register MOReg = MO.getReg(); |
2018 | if (!MOReg) |
2019 | continue; |
2020 | |
2021 | if (MOReg == Reg) { |
2022 | MO.setIsDead(); |
2023 | Found = true; |
2024 | } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) { |
2025 | // There exists a super-register that's marked dead. |
2026 | if (RegInfo->isSuperRegister(RegA: Reg, RegB: MOReg)) |
2027 | return true; |
2028 | if (RegInfo->isSubRegister(RegA: Reg, RegB: MOReg)) |
2029 | DeadOps.push_back(Elt: i); |
2030 | } |
2031 | } |
2032 | |
2033 | // Trim unneeded dead operands. |
2034 | while (!DeadOps.empty()) { |
2035 | unsigned OpIdx = DeadOps.back(); |
2036 | if (getOperand(i: OpIdx).isImplicit() && |
2037 | (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) |
2038 | removeOperand(OpNo: OpIdx); |
2039 | else |
2040 | getOperand(i: OpIdx).setIsDead(false); |
2041 | DeadOps.pop_back(); |
2042 | } |
2043 | |
2044 | // If not found, this means an alias of one of the operands is dead. Add a |
2045 | // new implicit operand if required. |
2046 | if (Found || !AddIfNotFound) |
2047 | return Found; |
2048 | |
2049 | addOperand(Op: MachineOperand::CreateReg(Reg, |
2050 | isDef: true /*IsDef*/, |
2051 | isImp: true /*IsImp*/, |
2052 | isKill: false /*IsKill*/, |
2053 | isDead: true /*IsDead*/)); |
2054 | return true; |
2055 | } |
2056 | |
2057 | void MachineInstr::clearRegisterDeads(Register Reg) { |
2058 | for (MachineOperand &MO : operands()) { |
2059 | if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) |
2060 | continue; |
2061 | MO.setIsDead(false); |
2062 | } |
2063 | } |
2064 | |
2065 | void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) { |
2066 | for (MachineOperand &MO : operands()) { |
2067 | if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0) |
2068 | continue; |
2069 | MO.setIsUndef(IsUndef); |
2070 | } |
2071 | } |
2072 | |
2073 | void MachineInstr::addRegisterDefined(Register Reg, |
2074 | const TargetRegisterInfo *RegInfo) { |
2075 | if (Reg.isPhysical()) { |
2076 | MachineOperand *MO = findRegisterDefOperand(Reg, isDead: false, Overlap: false, TRI: RegInfo); |
2077 | if (MO) |
2078 | return; |
2079 | } else { |
2080 | for (const MachineOperand &MO : operands()) { |
2081 | if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && |
2082 | MO.getSubReg() == 0) |
2083 | return; |
2084 | } |
2085 | } |
2086 | addOperand(Op: MachineOperand::CreateReg(Reg, |
2087 | isDef: true /*IsDef*/, |
2088 | isImp: true /*IsImp*/)); |
2089 | } |
2090 | |
2091 | void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, |
2092 | const TargetRegisterInfo &TRI) { |
2093 | bool HasRegMask = false; |
2094 | for (MachineOperand &MO : operands()) { |
2095 | if (MO.isRegMask()) { |
2096 | HasRegMask = true; |
2097 | continue; |
2098 | } |
2099 | if (!MO.isReg() || !MO.isDef()) continue; |
2100 | Register Reg = MO.getReg(); |
2101 | if (!Reg.isPhysical()) |
2102 | continue; |
2103 | // If there are no uses, including partial uses, the def is dead. |
2104 | if (llvm::none_of(Range&: UsedRegs, |
2105 | P: [&](MCRegister Use) { return TRI.regsOverlap(RegA: Use, RegB: Reg); })) |
2106 | MO.setIsDead(); |
2107 | } |
2108 | |
2109 | // This is a call with a register mask operand. |
2110 | // Mask clobbers are always dead, so add defs for the non-dead defines. |
2111 | if (HasRegMask) |
2112 | for (const Register &UsedReg : UsedRegs) |
2113 | addRegisterDefined(Reg: UsedReg, RegInfo: &TRI); |
2114 | } |
2115 | |
2116 | unsigned |
2117 | MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { |
2118 | // Build up a buffer of hash code components. |
2119 | SmallVector<size_t, 16> HashComponents; |
2120 | HashComponents.reserve(N: MI->getNumOperands() + 1); |
2121 | HashComponents.push_back(Elt: MI->getOpcode()); |
2122 | for (const MachineOperand &MO : MI->operands()) { |
2123 | if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual()) |
2124 | continue; // Skip virtual register defs. |
2125 | |
2126 | HashComponents.push_back(Elt: hash_value(MO)); |
2127 | } |
2128 | return hash_combine_range(first: HashComponents.begin(), last: HashComponents.end()); |
2129 | } |
2130 | |
2131 | void MachineInstr::emitError(StringRef Msg) const { |
2132 | // Find the source location cookie. |
2133 | uint64_t LocCookie = 0; |
2134 | const MDNode *LocMD = nullptr; |
2135 | for (unsigned i = getNumOperands(); i != 0; --i) { |
2136 | if (getOperand(i: i-1).isMetadata() && |
2137 | (LocMD = getOperand(i: i-1).getMetadata()) && |
2138 | LocMD->getNumOperands() != 0) { |
2139 | if (const ConstantInt *CI = |
2140 | mdconst::dyn_extract<ConstantInt>(MD: LocMD->getOperand(I: 0))) { |
2141 | LocCookie = CI->getZExtValue(); |
2142 | break; |
2143 | } |
2144 | } |
2145 | } |
2146 | |
2147 | if (const MachineBasicBlock *MBB = getParent()) |
2148 | if (const MachineFunction *MF = MBB->getParent()) |
2149 | return MF->getMMI().getModule()->getContext().emitError(LocCookie, ErrorStr: Msg); |
2150 | report_fatal_error(reason: Msg); |
2151 | } |
2152 | |
2153 | MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, |
2154 | const MCInstrDesc &MCID, bool IsIndirect, |
2155 | Register Reg, const MDNode *Variable, |
2156 | const MDNode *Expr) { |
2157 | assert(isa<DILocalVariable>(Variable) && "not a variable" ); |
2158 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression" ); |
2159 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && |
2160 | "Expected inlined-at fields to agree" ); |
2161 | auto MIB = BuildMI(MF, MIMD: DL, MCID).addReg(RegNo: Reg); |
2162 | if (IsIndirect) |
2163 | MIB.addImm(Val: 0U); |
2164 | else |
2165 | MIB.addReg(RegNo: 0U); |
2166 | return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr); |
2167 | } |
2168 | |
2169 | MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, |
2170 | const MCInstrDesc &MCID, bool IsIndirect, |
2171 | ArrayRef<MachineOperand> DebugOps, |
2172 | const MDNode *Variable, const MDNode *Expr) { |
2173 | assert(isa<DILocalVariable>(Variable) && "not a variable" ); |
2174 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression" ); |
2175 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && |
2176 | "Expected inlined-at fields to agree" ); |
2177 | if (MCID.Opcode == TargetOpcode::DBG_VALUE) { |
2178 | assert(DebugOps.size() == 1 && |
2179 | "DBG_VALUE must contain exactly one debug operand" ); |
2180 | MachineOperand DebugOp = DebugOps[0]; |
2181 | if (DebugOp.isReg()) |
2182 | return BuildMI(MF, DL, MCID, IsIndirect, Reg: DebugOp.getReg(), Variable, |
2183 | Expr); |
2184 | |
2185 | auto MIB = BuildMI(MF, MIMD: DL, MCID).add(MO: DebugOp); |
2186 | if (IsIndirect) |
2187 | MIB.addImm(Val: 0U); |
2188 | else |
2189 | MIB.addReg(RegNo: 0U); |
2190 | return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr); |
2191 | } |
2192 | |
2193 | auto MIB = BuildMI(MF, MIMD: DL, MCID); |
2194 | MIB.addMetadata(MD: Variable).addMetadata(MD: Expr); |
2195 | for (const MachineOperand &DebugOp : DebugOps) |
2196 | if (DebugOp.isReg()) |
2197 | MIB.addReg(RegNo: DebugOp.getReg()); |
2198 | else |
2199 | MIB.add(MO: DebugOp); |
2200 | return MIB; |
2201 | } |
2202 | |
2203 | MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, |
2204 | MachineBasicBlock::iterator I, |
2205 | const DebugLoc &DL, const MCInstrDesc &MCID, |
2206 | bool IsIndirect, Register Reg, |
2207 | const MDNode *Variable, const MDNode *Expr) { |
2208 | MachineFunction &MF = *BB.getParent(); |
2209 | MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr); |
2210 | BB.insert(I, MI); |
2211 | return MachineInstrBuilder(MF, MI); |
2212 | } |
2213 | |
2214 | MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, |
2215 | MachineBasicBlock::iterator I, |
2216 | const DebugLoc &DL, const MCInstrDesc &MCID, |
2217 | bool IsIndirect, |
2218 | ArrayRef<MachineOperand> DebugOps, |
2219 | const MDNode *Variable, const MDNode *Expr) { |
2220 | MachineFunction &MF = *BB.getParent(); |
2221 | MachineInstr *MI = |
2222 | BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr); |
2223 | BB.insert(I, MI); |
2224 | return MachineInstrBuilder(MF, *MI); |
2225 | } |
2226 | |
2227 | /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot. |
2228 | /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE. |
2229 | static const DIExpression * |
2230 | computeExprForSpill(const MachineInstr &MI, |
2231 | SmallVectorImpl<const MachineOperand *> &SpilledOperands) { |
2232 | assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && |
2233 | "Expected inlined-at fields to agree" ); |
2234 | |
2235 | const DIExpression *Expr = MI.getDebugExpression(); |
2236 | if (MI.isIndirectDebugValue()) { |
2237 | assert(MI.getDebugOffset().getImm() == 0 && |
2238 | "DBG_VALUE with nonzero offset" ); |
2239 | Expr = DIExpression::prepend(Expr, Flags: DIExpression::DerefBefore); |
2240 | } else if (MI.isDebugValueList()) { |
2241 | // We will replace the spilled register with a frame index, so |
2242 | // immediately deref all references to the spilled register. |
2243 | std::array<uint64_t, 1> Ops{._M_elems: {dwarf::DW_OP_deref}}; |
2244 | for (const MachineOperand *Op : SpilledOperands) { |
2245 | unsigned OpIdx = MI.getDebugOperandIndex(Op); |
2246 | Expr = DIExpression::appendOpsToArg(Expr, Ops, ArgNo: OpIdx); |
2247 | } |
2248 | } |
2249 | return Expr; |
2250 | } |
2251 | static const DIExpression *computeExprForSpill(const MachineInstr &MI, |
2252 | Register SpillReg) { |
2253 | assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI." ); |
2254 | SmallVector<const MachineOperand *> SpillOperands; |
2255 | for (const MachineOperand &Op : MI.getDebugOperandsForReg(Reg: SpillReg)) |
2256 | SpillOperands.push_back(Elt: &Op); |
2257 | return computeExprForSpill(MI, SpilledOperands&: SpillOperands); |
2258 | } |
2259 | |
2260 | MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB, |
2261 | MachineBasicBlock::iterator I, |
2262 | const MachineInstr &Orig, |
2263 | int FrameIndex, Register SpillReg) { |
2264 | assert(!Orig.isDebugRef() && |
2265 | "DBG_INSTR_REF should not reference a virtual register." ); |
2266 | const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg); |
2267 | MachineInstrBuilder NewMI = |
2268 | BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc()); |
2269 | // Non-Variadic Operands: Location, Offset, Variable, Expression |
2270 | // Variadic Operands: Variable, Expression, Locations... |
2271 | if (Orig.isNonListDebugValue()) |
2272 | NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U); |
2273 | NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr); |
2274 | if (Orig.isDebugValueList()) { |
2275 | for (const MachineOperand &Op : Orig.debug_operands()) |
2276 | if (Op.isReg() && Op.getReg() == SpillReg) |
2277 | NewMI.addFrameIndex(Idx: FrameIndex); |
2278 | else |
2279 | NewMI.add(MO: MachineOperand(Op)); |
2280 | } |
2281 | return NewMI; |
2282 | } |
2283 | MachineInstr *llvm::buildDbgValueForSpill( |
2284 | MachineBasicBlock &BB, MachineBasicBlock::iterator I, |
2285 | const MachineInstr &Orig, int FrameIndex, |
2286 | SmallVectorImpl<const MachineOperand *> &SpilledOperands) { |
2287 | const DIExpression *Expr = computeExprForSpill(MI: Orig, SpilledOperands); |
2288 | MachineInstrBuilder NewMI = |
2289 | BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc()); |
2290 | // Non-Variadic Operands: Location, Offset, Variable, Expression |
2291 | // Variadic Operands: Variable, Expression, Locations... |
2292 | if (Orig.isNonListDebugValue()) |
2293 | NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U); |
2294 | NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr); |
2295 | if (Orig.isDebugValueList()) { |
2296 | for (const MachineOperand &Op : Orig.debug_operands()) |
2297 | if (is_contained(Range&: SpilledOperands, Element: &Op)) |
2298 | NewMI.addFrameIndex(Idx: FrameIndex); |
2299 | else |
2300 | NewMI.add(MO: MachineOperand(Op)); |
2301 | } |
2302 | return NewMI; |
2303 | } |
2304 | |
2305 | void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, |
2306 | Register Reg) { |
2307 | const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg: Reg); |
2308 | if (Orig.isNonListDebugValue()) |
2309 | Orig.getDebugOffset().ChangeToImmediate(ImmVal: 0U); |
2310 | for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg)) |
2311 | Op.ChangeToFrameIndex(Idx: FrameIndex); |
2312 | Orig.getDebugExpressionOp().setMetadata(Expr); |
2313 | } |
2314 | |
2315 | void MachineInstr::collectDebugValues( |
2316 | SmallVectorImpl<MachineInstr *> &DbgValues) { |
2317 | MachineInstr &MI = *this; |
2318 | if (!MI.getOperand(i: 0).isReg()) |
2319 | return; |
2320 | |
2321 | MachineBasicBlock::iterator DI = MI; ++DI; |
2322 | for (MachineBasicBlock::iterator DE = MI.getParent()->end(); |
2323 | DI != DE; ++DI) { |
2324 | if (!DI->isDebugValue()) |
2325 | return; |
2326 | if (DI->hasDebugOperandForReg(Reg: MI.getOperand(i: 0).getReg())) |
2327 | DbgValues.push_back(Elt: &*DI); |
2328 | } |
2329 | } |
2330 | |
2331 | void MachineInstr::changeDebugValuesDefReg(Register Reg) { |
2332 | // Collect matching debug values. |
2333 | SmallVector<MachineInstr *, 2> DbgValues; |
2334 | |
2335 | if (!getOperand(i: 0).isReg()) |
2336 | return; |
2337 | |
2338 | Register DefReg = getOperand(i: 0).getReg(); |
2339 | auto *MRI = getRegInfo(); |
2340 | for (auto &MO : MRI->use_operands(Reg: DefReg)) { |
2341 | auto *DI = MO.getParent(); |
2342 | if (!DI->isDebugValue()) |
2343 | continue; |
2344 | if (DI->hasDebugOperandForReg(Reg: DefReg)) { |
2345 | DbgValues.push_back(Elt: DI); |
2346 | } |
2347 | } |
2348 | |
2349 | // Propagate Reg to debug value instructions. |
2350 | for (auto *DBI : DbgValues) |
2351 | for (MachineOperand &Op : DBI->getDebugOperandsForReg(Reg: DefReg)) |
2352 | Op.setReg(Reg); |
2353 | } |
2354 | |
2355 | using MMOList = SmallVector<const MachineMemOperand *, 2>; |
2356 | |
2357 | static unsigned getSpillSlotSize(const MMOList &Accesses, |
2358 | const MachineFrameInfo &MFI) { |
2359 | unsigned Size = 0; |
2360 | for (const auto *A : Accesses) |
2361 | if (MFI.isSpillSlotObjectIndex( |
2362 | ObjectIdx: cast<FixedStackPseudoSourceValue>(Val: A->getPseudoValue()) |
2363 | ->getFrameIndex())) |
2364 | Size += A->getSize(); |
2365 | return Size; |
2366 | } |
2367 | |
2368 | std::optional<unsigned> |
2369 | MachineInstr::getSpillSize(const TargetInstrInfo *TII) const { |
2370 | int FI; |
2371 | if (TII->isStoreToStackSlotPostFE(MI: *this, FrameIndex&: FI)) { |
2372 | const MachineFrameInfo &MFI = getMF()->getFrameInfo(); |
2373 | if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI)) |
2374 | return (*memoperands_begin())->getSize(); |
2375 | } |
2376 | return std::nullopt; |
2377 | } |
2378 | |
2379 | std::optional<unsigned> |
2380 | MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const { |
2381 | MMOList Accesses; |
2382 | if (TII->hasStoreToStackSlot(MI: *this, Accesses)) |
2383 | return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo()); |
2384 | return std::nullopt; |
2385 | } |
2386 | |
2387 | std::optional<unsigned> |
2388 | MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const { |
2389 | int FI; |
2390 | if (TII->isLoadFromStackSlotPostFE(MI: *this, FrameIndex&: FI)) { |
2391 | const MachineFrameInfo &MFI = getMF()->getFrameInfo(); |
2392 | if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI)) |
2393 | return (*memoperands_begin())->getSize(); |
2394 | } |
2395 | return std::nullopt; |
2396 | } |
2397 | |
2398 | std::optional<unsigned> |
2399 | MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const { |
2400 | MMOList Accesses; |
2401 | if (TII->hasLoadFromStackSlot(MI: *this, Accesses)) |
2402 | return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo()); |
2403 | return std::nullopt; |
2404 | } |
2405 | |
2406 | unsigned MachineInstr::getDebugInstrNum() { |
2407 | if (DebugInstrNum == 0) |
2408 | DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum(); |
2409 | return DebugInstrNum; |
2410 | } |
2411 | |
2412 | unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) { |
2413 | if (DebugInstrNum == 0) |
2414 | DebugInstrNum = MF.getNewDebugInstrNum(); |
2415 | return DebugInstrNum; |
2416 | } |
2417 | |
2418 | std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const { |
2419 | return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()), |
2420 | getRegInfo()->getType(Reg: getOperand(i: 1).getReg())); |
2421 | } |
2422 | |
2423 | std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const { |
2424 | return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()), |
2425 | getRegInfo()->getType(Reg: getOperand(i: 1).getReg()), |
2426 | getRegInfo()->getType(Reg: getOperand(i: 2).getReg())); |
2427 | } |
2428 | |
2429 | std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const { |
2430 | return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()), |
2431 | getRegInfo()->getType(Reg: getOperand(i: 1).getReg()), |
2432 | getRegInfo()->getType(Reg: getOperand(i: 2).getReg()), |
2433 | getRegInfo()->getType(Reg: getOperand(i: 3).getReg())); |
2434 | } |
2435 | |
2436 | std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const { |
2437 | return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()), |
2438 | getRegInfo()->getType(Reg: getOperand(i: 1).getReg()), |
2439 | getRegInfo()->getType(Reg: getOperand(i: 2).getReg()), |
2440 | getRegInfo()->getType(Reg: getOperand(i: 3).getReg()), |
2441 | getRegInfo()->getType(Reg: getOperand(i: 4).getReg())); |
2442 | } |
2443 | |
2444 | std::tuple<Register, LLT, Register, LLT> |
2445 | MachineInstr::getFirst2RegLLTs() const { |
2446 | Register Reg0 = getOperand(i: 0).getReg(); |
2447 | Register Reg1 = getOperand(i: 1).getReg(); |
2448 | return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, |
2449 | getRegInfo()->getType(Reg: Reg1)); |
2450 | } |
2451 | |
2452 | std::tuple<Register, LLT, Register, LLT, Register, LLT> |
2453 | MachineInstr::getFirst3RegLLTs() const { |
2454 | Register Reg0 = getOperand(i: 0).getReg(); |
2455 | Register Reg1 = getOperand(i: 1).getReg(); |
2456 | Register Reg2 = getOperand(i: 2).getReg(); |
2457 | return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, |
2458 | getRegInfo()->getType(Reg: Reg1), Reg2, |
2459 | getRegInfo()->getType(Reg: Reg2)); |
2460 | } |
2461 | |
2462 | std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT> |
2463 | MachineInstr::getFirst4RegLLTs() const { |
2464 | Register Reg0 = getOperand(i: 0).getReg(); |
2465 | Register Reg1 = getOperand(i: 1).getReg(); |
2466 | Register Reg2 = getOperand(i: 2).getReg(); |
2467 | Register Reg3 = getOperand(i: 3).getReg(); |
2468 | return std::tuple( |
2469 | Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1), |
2470 | Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3)); |
2471 | } |
2472 | |
2473 | std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, |
2474 | LLT> |
2475 | MachineInstr::getFirst5RegLLTs() const { |
2476 | Register Reg0 = getOperand(i: 0).getReg(); |
2477 | Register Reg1 = getOperand(i: 1).getReg(); |
2478 | Register Reg2 = getOperand(i: 2).getReg(); |
2479 | Register Reg3 = getOperand(i: 3).getReg(); |
2480 | Register Reg4 = getOperand(i: 4).getReg(); |
2481 | return std::tuple( |
2482 | Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1), |
2483 | Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3), |
2484 | Reg4, getRegInfo()->getType(Reg: Reg4)); |
2485 | } |
2486 | |
2487 | void MachineInstr::insert(mop_iterator InsertBefore, |
2488 | ArrayRef<MachineOperand> Ops) { |
2489 | assert(InsertBefore != nullptr && "invalid iterator" ); |
2490 | assert(InsertBefore->getParent() == this && |
2491 | "iterator points to operand of other inst" ); |
2492 | if (Ops.empty()) |
2493 | return; |
2494 | |
2495 | // Do one pass to untie operands. |
2496 | SmallDenseMap<unsigned, unsigned> TiedOpIndices; |
2497 | for (const MachineOperand &MO : operands()) { |
2498 | if (MO.isReg() && MO.isTied()) { |
2499 | unsigned OpNo = getOperandNo(I: &MO); |
2500 | unsigned TiedTo = findTiedOperandIdx(OpIdx: OpNo); |
2501 | TiedOpIndices[OpNo] = TiedTo; |
2502 | untieRegOperand(OpIdx: OpNo); |
2503 | } |
2504 | } |
2505 | |
2506 | unsigned OpIdx = getOperandNo(I: InsertBefore); |
2507 | unsigned NumOperands = getNumOperands(); |
2508 | unsigned OpsToMove = NumOperands - OpIdx; |
2509 | |
2510 | SmallVector<MachineOperand> MovingOps; |
2511 | MovingOps.reserve(N: OpsToMove); |
2512 | |
2513 | for (unsigned I = 0; I < OpsToMove; ++I) { |
2514 | MovingOps.emplace_back(Args&: getOperand(i: OpIdx)); |
2515 | removeOperand(OpNo: OpIdx); |
2516 | } |
2517 | for (const MachineOperand &MO : Ops) |
2518 | addOperand(Op: MO); |
2519 | for (const MachineOperand &OpMoved : MovingOps) |
2520 | addOperand(Op: OpMoved); |
2521 | |
2522 | // Re-tie operands. |
2523 | for (auto [Tie1, Tie2] : TiedOpIndices) { |
2524 | if (Tie1 >= OpIdx) |
2525 | Tie1 += Ops.size(); |
2526 | if (Tie2 >= OpIdx) |
2527 | Tie2 += Ops.size(); |
2528 | tieOperands(DefIdx: Tie1, UseIdx: Tie2); |
2529 | } |
2530 | } |
2531 | |
2532 | bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const { |
2533 | assert(OpId && "expected non-zero operand id" ); |
2534 | assert(isInlineAsm() && "should only be used on inline asm" ); |
2535 | |
2536 | if (!getOperand(i: OpId).isReg()) |
2537 | return false; |
2538 | |
2539 | const MachineOperand &MD = getOperand(i: OpId - 1); |
2540 | if (!MD.isImm()) |
2541 | return false; |
2542 | |
2543 | InlineAsm::Flag F(MD.getImm()); |
2544 | if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) |
2545 | return F.getRegMayBeFolded(); |
2546 | return false; |
2547 | } |
2548 | |