1 | //===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // Implementation of the MachineRegisterInfo class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
14 | #include "llvm/ADT/iterator_range.h" |
15 | #include "llvm/CodeGen/MachineBasicBlock.h" |
16 | #include "llvm/CodeGen/MachineFunction.h" |
17 | #include "llvm/CodeGen/MachineInstr.h" |
18 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
19 | #include "llvm/CodeGen/MachineOperand.h" |
20 | #include "llvm/CodeGen/TargetInstrInfo.h" |
21 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
22 | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
23 | #include "llvm/Config/llvm-config.h" |
24 | #include "llvm/IR/Attributes.h" |
25 | #include "llvm/IR/DebugLoc.h" |
26 | #include "llvm/IR/Function.h" |
27 | #include "llvm/MC/MCRegisterInfo.h" |
28 | #include "llvm/Support/Casting.h" |
29 | #include "llvm/Support/CommandLine.h" |
30 | #include "llvm/Support/Compiler.h" |
31 | #include "llvm/Support/ErrorHandling.h" |
32 | #include "llvm/Support/raw_ostream.h" |
33 | #include <cassert> |
34 | |
35 | using namespace llvm; |
36 | |
37 | static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness" , cl::Hidden, |
38 | cl::init(Val: true), cl::desc("Enable subregister liveness tracking." )); |
39 | |
40 | // Pin the vtable to this file. |
41 | void MachineRegisterInfo::Delegate::anchor() {} |
42 | |
43 | MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) |
44 | : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() && |
45 | EnableSubRegLiveness) { |
46 | unsigned NumRegs = getTargetRegisterInfo()->getNumRegs(); |
47 | VRegInfo.reserve(s: 256); |
48 | RegAllocHints.reserve(s: 256); |
49 | UsedPhysRegMask.resize(N: NumRegs); |
50 | PhysRegUseDefLists.reset(p: new MachineOperand*[NumRegs]()); |
51 | TheDelegates.clear(); |
52 | } |
53 | |
54 | /// setRegClass - Set the register class of the specified virtual register. |
55 | /// |
56 | void |
57 | MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { |
58 | assert(RC && RC->isAllocatable() && "Invalid RC for virtual register" ); |
59 | VRegInfo[Reg].first = RC; |
60 | } |
61 | |
62 | void MachineRegisterInfo::setRegBank(Register Reg, |
63 | const RegisterBank &RegBank) { |
64 | VRegInfo[Reg].first = &RegBank; |
65 | } |
66 | |
67 | static const TargetRegisterClass * |
68 | constrainRegClass(MachineRegisterInfo &MRI, Register Reg, |
69 | const TargetRegisterClass *OldRC, |
70 | const TargetRegisterClass *RC, unsigned MinNumRegs) { |
71 | if (OldRC == RC) |
72 | return RC; |
73 | const TargetRegisterClass *NewRC = |
74 | MRI.getTargetRegisterInfo()->getCommonSubClass(A: OldRC, B: RC); |
75 | if (!NewRC || NewRC == OldRC) |
76 | return NewRC; |
77 | if (NewRC->getNumRegs() < MinNumRegs) |
78 | return nullptr; |
79 | MRI.setRegClass(Reg, RC: NewRC); |
80 | return NewRC; |
81 | } |
82 | |
83 | const TargetRegisterClass *MachineRegisterInfo::constrainRegClass( |
84 | Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { |
85 | if (Reg.isPhysical()) |
86 | return nullptr; |
87 | return ::constrainRegClass(MRI&: *this, Reg, OldRC: getRegClass(Reg), RC, MinNumRegs); |
88 | } |
89 | |
90 | bool |
91 | MachineRegisterInfo::constrainRegAttrs(Register Reg, |
92 | Register ConstrainingReg, |
93 | unsigned MinNumRegs) { |
94 | const LLT RegTy = getType(Reg); |
95 | const LLT ConstrainingRegTy = getType(Reg: ConstrainingReg); |
96 | if (RegTy.isValid() && ConstrainingRegTy.isValid() && |
97 | RegTy != ConstrainingRegTy) |
98 | return false; |
99 | const auto &ConstrainingRegCB = getRegClassOrRegBank(Reg: ConstrainingReg); |
100 | if (!ConstrainingRegCB.isNull()) { |
101 | const auto &RegCB = getRegClassOrRegBank(Reg); |
102 | if (RegCB.isNull()) |
103 | setRegClassOrRegBank(Reg, RCOrRB: ConstrainingRegCB); |
104 | else if (isa<const TargetRegisterClass *>(Val: RegCB) != |
105 | isa<const TargetRegisterClass *>(Val: ConstrainingRegCB)) |
106 | return false; |
107 | else if (isa<const TargetRegisterClass *>(Val: RegCB)) { |
108 | if (!::constrainRegClass( |
109 | MRI&: *this, Reg, OldRC: cast<const TargetRegisterClass *>(Val: RegCB), |
110 | RC: cast<const TargetRegisterClass *>(Val: ConstrainingRegCB), MinNumRegs)) |
111 | return false; |
112 | } else if (RegCB != ConstrainingRegCB) |
113 | return false; |
114 | } |
115 | if (ConstrainingRegTy.isValid()) |
116 | setType(VReg: Reg, Ty: ConstrainingRegTy); |
117 | return true; |
118 | } |
119 | |
120 | bool |
121 | MachineRegisterInfo::recomputeRegClass(Register Reg) { |
122 | const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); |
123 | const TargetRegisterClass *OldRC = getRegClass(Reg); |
124 | const TargetRegisterClass *NewRC = |
125 | getTargetRegisterInfo()->getLargestLegalSuperClass(RC: OldRC, *MF); |
126 | |
127 | // Stop early if there is no room to grow. |
128 | if (NewRC == OldRC) |
129 | return false; |
130 | |
131 | // Accumulate constraints from all uses. |
132 | for (MachineOperand &MO : reg_nodbg_operands(Reg)) { |
133 | // Apply the effect of the given operand to NewRC. |
134 | MachineInstr *MI = MO.getParent(); |
135 | unsigned OpNo = &MO - &MI->getOperand(i: 0); |
136 | NewRC = MI->getRegClassConstraintEffect(OpIdx: OpNo, CurRC: NewRC, TII, |
137 | TRI: getTargetRegisterInfo()); |
138 | if (!NewRC || NewRC == OldRC) |
139 | return false; |
140 | } |
141 | setRegClass(Reg, RC: NewRC); |
142 | return true; |
143 | } |
144 | |
145 | Register MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) { |
146 | Register Reg = Register::index2VirtReg(Index: getNumVirtRegs()); |
147 | VRegInfo.grow(n: Reg); |
148 | RegAllocHints.grow(n: Reg); |
149 | insertVRegByName(Name, Reg); |
150 | return Reg; |
151 | } |
152 | |
153 | /// createVirtualRegister - Create and return a new virtual register in the |
154 | /// function with the specified register class. |
155 | /// |
156 | Register |
157 | MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, |
158 | StringRef Name) { |
159 | assert(RegClass && "Cannot create register without RegClass!" ); |
160 | assert(RegClass->isAllocatable() && |
161 | "Virtual register RegClass must be allocatable." ); |
162 | |
163 | // New virtual register number. |
164 | Register Reg = createIncompleteVirtualRegister(Name); |
165 | VRegInfo[Reg].first = RegClass; |
166 | noteNewVirtualRegister(Reg); |
167 | return Reg; |
168 | } |
169 | |
170 | Register MachineRegisterInfo::createVirtualRegister(VRegAttrs RegAttr, |
171 | StringRef Name) { |
172 | Register Reg = createIncompleteVirtualRegister(Name); |
173 | VRegInfo[Reg].first = RegAttr.RCOrRB; |
174 | setType(VReg: Reg, Ty: RegAttr.Ty); |
175 | noteNewVirtualRegister(Reg); |
176 | return Reg; |
177 | } |
178 | |
179 | Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, |
180 | StringRef Name) { |
181 | Register Reg = createIncompleteVirtualRegister(Name); |
182 | VRegInfo[Reg].first = VRegInfo[VReg].first; |
183 | setType(VReg: Reg, Ty: getType(Reg: VReg)); |
184 | noteCloneVirtualRegister(NewReg: Reg, SrcReg: VReg); |
185 | return Reg; |
186 | } |
187 | |
188 | void MachineRegisterInfo::setType(Register VReg, LLT Ty) { |
189 | VRegToType.grow(n: VReg); |
190 | VRegToType[VReg] = Ty; |
191 | } |
192 | |
193 | Register |
194 | MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) { |
195 | // New virtual register number. |
196 | Register Reg = createIncompleteVirtualRegister(Name); |
197 | // FIXME: Should we use a dummy register class? |
198 | VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr); |
199 | setType(VReg: Reg, Ty); |
200 | noteNewVirtualRegister(Reg); |
201 | return Reg; |
202 | } |
203 | |
204 | void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); } |
205 | |
206 | /// clearVirtRegs - Remove all virtual registers (after physreg assignment). |
207 | void MachineRegisterInfo::clearVirtRegs() { |
208 | #ifndef NDEBUG |
209 | for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { |
210 | Register Reg = Register::index2VirtReg(Index: i); |
211 | if (!VRegInfo[Reg].second) |
212 | continue; |
213 | verifyUseList(Reg); |
214 | errs() << "Remaining virtual register " |
215 | << printReg(Reg, TRI: getTargetRegisterInfo()) << "...\n" ; |
216 | for (MachineInstr &MI : reg_instructions(Reg)) |
217 | errs() << "...in instruction: " << MI << "\n" ; |
218 | std::abort(); |
219 | } |
220 | #endif |
221 | VRegInfo.clear(); |
222 | for (auto &I : LiveIns) |
223 | I.second = 0; |
224 | } |
225 | |
226 | void MachineRegisterInfo::verifyUseList(Register Reg) const { |
227 | #ifndef NDEBUG |
228 | bool Valid = true; |
229 | for (MachineOperand &M : reg_operands(Reg)) { |
230 | MachineOperand *MO = &M; |
231 | MachineInstr *MI = MO->getParent(); |
232 | if (!MI) { |
233 | errs() << printReg(Reg, TRI: getTargetRegisterInfo()) |
234 | << " use list MachineOperand " << MO |
235 | << " has no parent instruction.\n" ; |
236 | Valid = false; |
237 | continue; |
238 | } |
239 | MachineOperand *MO0 = &MI->getOperand(i: 0); |
240 | unsigned NumOps = MI->getNumOperands(); |
241 | if (!(MO >= MO0 && MO < MO0+NumOps)) { |
242 | errs() << printReg(Reg, TRI: getTargetRegisterInfo()) |
243 | << " use list MachineOperand " << MO |
244 | << " doesn't belong to parent MI: " << *MI; |
245 | Valid = false; |
246 | } |
247 | if (!MO->isReg()) { |
248 | errs() << printReg(Reg, TRI: getTargetRegisterInfo()) |
249 | << " MachineOperand " << MO << ": " << *MO |
250 | << " is not a register\n" ; |
251 | Valid = false; |
252 | } |
253 | if (MO->getReg() != Reg) { |
254 | errs() << printReg(Reg, TRI: getTargetRegisterInfo()) |
255 | << " use-list MachineOperand " << MO << ": " |
256 | << *MO << " is the wrong register\n" ; |
257 | Valid = false; |
258 | } |
259 | } |
260 | assert(Valid && "Invalid use list" ); |
261 | #endif |
262 | } |
263 | |
264 | void MachineRegisterInfo::verifyUseLists() const { |
265 | #ifndef NDEBUG |
266 | for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) |
267 | verifyUseList(Reg: Register::index2VirtReg(Index: i)); |
268 | for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) |
269 | verifyUseList(Reg: i); |
270 | #endif |
271 | } |
272 | |
273 | /// Add MO to the linked list of operands for its register. |
274 | void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { |
275 | assert(!MO->isOnRegUseList() && "Already on list" ); |
276 | MachineOperand *&HeadRef = getRegUseDefListHead(RegNo: MO->getReg()); |
277 | MachineOperand *const Head = HeadRef; |
278 | |
279 | // Head points to the first list element. |
280 | // Next is NULL on the last list element. |
281 | // Prev pointers are circular, so Head->Prev == Last. |
282 | |
283 | // Head is NULL for an empty list. |
284 | if (!Head) { |
285 | MO->Contents.Reg.Prev = MO; |
286 | MO->Contents.Reg.Next = nullptr; |
287 | HeadRef = MO; |
288 | return; |
289 | } |
290 | assert(MO->getReg() == Head->getReg() && "Different regs on the same list!" ); |
291 | |
292 | // Insert MO between Last and Head in the circular Prev chain. |
293 | MachineOperand *Last = Head->Contents.Reg.Prev; |
294 | assert(Last && "Inconsistent use list" ); |
295 | assert(MO->getReg() == Last->getReg() && "Different regs on the same list!" ); |
296 | Head->Contents.Reg.Prev = MO; |
297 | MO->Contents.Reg.Prev = Last; |
298 | |
299 | // Def operands always precede uses. This allows def_iterator to stop early. |
300 | // Insert def operands at the front, and use operands at the back. |
301 | if (MO->isDef()) { |
302 | // Insert def at the front. |
303 | MO->Contents.Reg.Next = Head; |
304 | HeadRef = MO; |
305 | } else { |
306 | // Insert use at the end. |
307 | MO->Contents.Reg.Next = nullptr; |
308 | Last->Contents.Reg.Next = MO; |
309 | } |
310 | } |
311 | |
312 | /// Remove MO from its use-def list. |
313 | void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { |
314 | assert(MO->isOnRegUseList() && "Operand not on use list" ); |
315 | MachineOperand *&HeadRef = getRegUseDefListHead(RegNo: MO->getReg()); |
316 | MachineOperand *const Head = HeadRef; |
317 | assert(Head && "List already empty" ); |
318 | |
319 | // Unlink this from the doubly linked list of operands. |
320 | MachineOperand *Next = MO->Contents.Reg.Next; |
321 | MachineOperand *Prev = MO->Contents.Reg.Prev; |
322 | |
323 | // Prev links are circular, next link is NULL instead of looping back to Head. |
324 | if (MO == Head) |
325 | HeadRef = Next; |
326 | else |
327 | Prev->Contents.Reg.Next = Next; |
328 | |
329 | (Next ? Next : Head)->Contents.Reg.Prev = Prev; |
330 | |
331 | MO->Contents.Reg.Prev = nullptr; |
332 | MO->Contents.Reg.Next = nullptr; |
333 | } |
334 | |
335 | /// Move NumOps operands from Src to Dst, updating use-def lists as needed. |
336 | /// |
337 | /// The Dst range is assumed to be uninitialized memory. (Or it may contain |
338 | /// operands that won't be destroyed, which is OK because the MO destructor is |
339 | /// trivial anyway). |
340 | /// |
341 | /// The Src and Dst ranges may overlap. |
342 | void MachineRegisterInfo::moveOperands(MachineOperand *Dst, |
343 | MachineOperand *Src, |
344 | unsigned NumOps) { |
345 | assert(Src != Dst && NumOps && "Noop moveOperands" ); |
346 | |
347 | // Copy backwards if Dst is within the Src range. |
348 | int Stride = 1; |
349 | if (Dst >= Src && Dst < Src + NumOps) { |
350 | Stride = -1; |
351 | Dst += NumOps - 1; |
352 | Src += NumOps - 1; |
353 | } |
354 | |
355 | // Copy one operand at a time. |
356 | do { |
357 | new (Dst) MachineOperand(*Src); |
358 | |
359 | // Dst takes Src's place in the use-def chain. |
360 | if (Src->isReg()) { |
361 | MachineOperand *&Head = getRegUseDefListHead(RegNo: Src->getReg()); |
362 | MachineOperand *Prev = Src->Contents.Reg.Prev; |
363 | MachineOperand *Next = Src->Contents.Reg.Next; |
364 | assert(Head && "List empty, but operand is chained" ); |
365 | assert(Prev && "Operand was not on use-def list" ); |
366 | |
367 | // Prev links are circular, next link is NULL instead of looping back to |
368 | // Head. |
369 | if (Src == Head) |
370 | Head = Dst; |
371 | else |
372 | Prev->Contents.Reg.Next = Dst; |
373 | |
374 | // Update Prev pointer. This also works when Src was pointing to itself |
375 | // in a 1-element list. In that case Head == Dst. |
376 | (Next ? Next : Head)->Contents.Reg.Prev = Dst; |
377 | } |
378 | |
379 | Dst += Stride; |
380 | Src += Stride; |
381 | } while (--NumOps); |
382 | } |
383 | |
384 | /// replaceRegWith - Replace all instances of FromReg with ToReg in the |
385 | /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), |
386 | /// except that it also changes any definitions of the register as well. |
387 | /// If ToReg is a physical register we apply the sub register to obtain the |
388 | /// final/proper physical register. |
389 | void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) { |
390 | assert(FromReg != ToReg && "Cannot replace a reg with itself" ); |
391 | |
392 | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
393 | |
394 | // TODO: This could be more efficient by bulk changing the operands. |
395 | for (MachineOperand &O : llvm::make_early_inc_range(Range: reg_operands(Reg: FromReg))) { |
396 | if (ToReg.isPhysical()) { |
397 | O.substPhysReg(Reg: ToReg, *TRI); |
398 | } else { |
399 | O.setReg(ToReg); |
400 | } |
401 | } |
402 | } |
403 | |
404 | /// getVRegDef - Return the machine instr that defines the specified virtual |
405 | /// register or null if none is found. This assumes that the code is in SSA |
406 | /// form, so there should only be one definition. |
407 | MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const { |
408 | // Since we are in SSA form, we can use the first definition. |
409 | def_instr_iterator I = def_instr_begin(RegNo: Reg); |
410 | assert((I.atEnd() || std::next(I) == def_instr_end()) && |
411 | "getVRegDef assumes a single definition or no definition" ); |
412 | return !I.atEnd() ? &*I : nullptr; |
413 | } |
414 | |
415 | /// getUniqueVRegDef - Return the unique machine instr that defines the |
416 | /// specified virtual register or null if none is found. If there are |
417 | /// multiple definitions or no definition, return null. |
418 | MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const { |
419 | if (def_empty(RegNo: Reg)) return nullptr; |
420 | def_instr_iterator I = def_instr_begin(RegNo: Reg); |
421 | if (std::next(x: I) != def_instr_end()) |
422 | return nullptr; |
423 | return &*I; |
424 | } |
425 | |
426 | bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const { |
427 | return hasSingleElement(C: use_nodbg_operands(Reg: RegNo)); |
428 | } |
429 | |
430 | bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const { |
431 | return hasSingleElement(C: use_nodbg_instructions(Reg: RegNo)); |
432 | } |
433 | |
434 | bool MachineRegisterInfo::hasAtMostUserInstrs(Register Reg, |
435 | unsigned MaxUsers) const { |
436 | return hasNItemsOrLess(Begin: use_instr_nodbg_begin(RegNo: Reg), End: use_instr_nodbg_end(), |
437 | N: MaxUsers); |
438 | } |
439 | |
440 | /// clearKillFlags - Iterate over all the uses of the given register and |
441 | /// clear the kill flag from the MachineOperand. This function is used by |
442 | /// optimization passes which extend register lifetimes and need only |
443 | /// preserve conservative kill flag information. |
444 | void MachineRegisterInfo::clearKillFlags(Register Reg) const { |
445 | for (MachineOperand &MO : use_operands(Reg)) |
446 | MO.setIsKill(false); |
447 | } |
448 | |
449 | bool MachineRegisterInfo::isLiveIn(Register Reg) const { |
450 | for (const std::pair<MCRegister, Register> &LI : liveins()) |
451 | if ((Register)LI.first == Reg || LI.second == Reg) |
452 | return true; |
453 | return false; |
454 | } |
455 | |
456 | /// getLiveInPhysReg - If VReg is a live-in virtual register, return the |
457 | /// corresponding live-in physical register. |
458 | MCRegister MachineRegisterInfo::getLiveInPhysReg(Register VReg) const { |
459 | for (const std::pair<MCRegister, Register> &LI : liveins()) |
460 | if (LI.second == VReg) |
461 | return LI.first; |
462 | return MCRegister(); |
463 | } |
464 | |
465 | /// getLiveInVirtReg - If PReg is a live-in physical register, return the |
466 | /// corresponding live-in physical register. |
467 | Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const { |
468 | for (const std::pair<MCRegister, Register> &LI : liveins()) |
469 | if (LI.first == PReg) |
470 | return LI.second; |
471 | return Register(); |
472 | } |
473 | |
474 | /// EmitLiveInCopies - Emit copies to initialize livein virtual registers |
475 | /// into the given entry block. |
476 | void |
477 | MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, |
478 | const TargetRegisterInfo &TRI, |
479 | const TargetInstrInfo &TII) { |
480 | // Emit the copies into the top of the block. |
481 | for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) |
482 | if (LiveIns[i].second) { |
483 | if (use_nodbg_empty(RegNo: LiveIns[i].second)) { |
484 | // The livein has no non-dbg uses. Drop it. |
485 | // |
486 | // It would be preferable to have isel avoid creating live-in |
487 | // records for unused arguments in the first place, but it's |
488 | // complicated by the debug info code for arguments. |
489 | LiveIns.erase(position: LiveIns.begin() + i); |
490 | --i; --e; |
491 | } else { |
492 | // Emit a copy. |
493 | BuildMI(BB&: *EntryMBB, I: EntryMBB->begin(), MIMD: DebugLoc(), |
494 | MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: LiveIns[i].second) |
495 | .addReg(RegNo: LiveIns[i].first); |
496 | |
497 | // Add the register to the entry block live-in set. |
498 | EntryMBB->addLiveIn(PhysReg: LiveIns[i].first); |
499 | } |
500 | } else { |
501 | // Add the register to the entry block live-in set. |
502 | EntryMBB->addLiveIn(PhysReg: LiveIns[i].first); |
503 | } |
504 | } |
505 | |
506 | LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const { |
507 | // Lane masks are only defined for vregs. |
508 | assert(Reg.isVirtual()); |
509 | const TargetRegisterClass &TRC = *getRegClass(Reg); |
510 | return TRC.getLaneMask(); |
511 | } |
512 | |
513 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
514 | LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const { |
515 | for (MachineInstr &I : use_instructions(Reg)) |
516 | I.dump(); |
517 | } |
518 | #endif |
519 | |
520 | void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { |
521 | ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); |
522 | assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && |
523 | "Invalid ReservedRegs vector from target" ); |
524 | } |
525 | |
526 | bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { |
527 | assert(Register::isPhysicalRegister(PhysReg)); |
528 | |
529 | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
530 | if (TRI->isConstantPhysReg(PhysReg)) |
531 | return true; |
532 | |
533 | // Check if any overlapping register is modified, or allocatable so it may be |
534 | // used later. |
535 | for (MCRegAliasIterator AI(PhysReg, TRI, true); |
536 | AI.isValid(); ++AI) |
537 | if (!def_empty(RegNo: *AI) || isAllocatable(PhysReg: *AI)) |
538 | return false; |
539 | return true; |
540 | } |
541 | |
542 | /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the |
543 | /// specified register as undefined which causes the DBG_VALUE to be |
544 | /// deleted during LiveDebugVariables analysis. |
545 | void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const { |
546 | // Mark any DBG_VALUE* that uses Reg as undef (but don't delete it.) |
547 | // We use make_early_inc_range because setReg invalidates the iterator. |
548 | for (MachineInstr &UseMI : llvm::make_early_inc_range(Range: use_instructions(Reg))) { |
549 | if (UseMI.isDebugValue() && UseMI.hasDebugOperandForReg(Reg)) |
550 | UseMI.setDebugValueUndef(); |
551 | } |
552 | } |
553 | |
554 | static const Function *getCalledFunction(const MachineInstr &MI) { |
555 | for (const MachineOperand &MO : MI.operands()) { |
556 | if (!MO.isGlobal()) |
557 | continue; |
558 | const Function *Func = dyn_cast<Function>(Val: MO.getGlobal()); |
559 | if (Func != nullptr) |
560 | return Func; |
561 | } |
562 | return nullptr; |
563 | } |
564 | |
565 | static bool isNoReturnDef(const MachineOperand &MO) { |
566 | // Anything which is not a noreturn function is a real def. |
567 | const MachineInstr &MI = *MO.getParent(); |
568 | if (!MI.isCall()) |
569 | return false; |
570 | const MachineBasicBlock &MBB = *MI.getParent(); |
571 | if (!MBB.succ_empty()) |
572 | return false; |
573 | const MachineFunction &MF = *MBB.getParent(); |
574 | // We need to keep correct unwind information even if the function will |
575 | // not return, since the runtime may need it. |
576 | if (MF.getFunction().hasFnAttribute(Attribute::UWTable)) |
577 | return false; |
578 | const Function *Called = getCalledFunction(MI); |
579 | return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) || |
580 | !Called->hasFnAttribute(Attribute::NoUnwind)); |
581 | } |
582 | |
583 | bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, |
584 | bool SkipNoReturnDef) const { |
585 | if (UsedPhysRegMask.test(Idx: PhysReg)) |
586 | return true; |
587 | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
588 | for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { |
589 | for (const MachineOperand &MO : make_range(x: def_begin(RegNo: *AI), y: def_end())) { |
590 | if (!SkipNoReturnDef && isNoReturnDef(MO)) |
591 | continue; |
592 | return true; |
593 | } |
594 | } |
595 | return false; |
596 | } |
597 | |
598 | bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg, |
599 | bool SkipRegMaskTest) const { |
600 | if (!SkipRegMaskTest && UsedPhysRegMask.test(Idx: PhysReg)) |
601 | return true; |
602 | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
603 | for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); |
604 | ++AliasReg) { |
605 | if (!reg_nodbg_empty(RegNo: *AliasReg)) |
606 | return true; |
607 | } |
608 | return false; |
609 | } |
610 | |
611 | void MachineRegisterInfo::disableCalleeSavedRegister(MCRegister Reg) { |
612 | |
613 | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
614 | assert(Reg && (Reg < TRI->getNumRegs()) && |
615 | "Trying to disable an invalid register" ); |
616 | |
617 | if (!IsUpdatedCSRsInitialized) { |
618 | const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); |
619 | for (const MCPhysReg *I = CSR; *I; ++I) |
620 | UpdatedCSRs.push_back(Elt: *I); |
621 | |
622 | // Zero value represents the end of the register list |
623 | // (no more registers should be pushed). |
624 | UpdatedCSRs.push_back(Elt: 0); |
625 | |
626 | IsUpdatedCSRsInitialized = true; |
627 | } |
628 | |
629 | // Remove the register (and its aliases from the list). |
630 | for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) |
631 | llvm::erase(C&: UpdatedCSRs, V: *AI); |
632 | } |
633 | |
634 | const MCPhysReg *MachineRegisterInfo::getCalleeSavedRegs() const { |
635 | if (IsUpdatedCSRsInitialized) |
636 | return UpdatedCSRs.data(); |
637 | |
638 | return getTargetRegisterInfo()->getCalleeSavedRegs(MF); |
639 | } |
640 | |
641 | void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) { |
642 | if (IsUpdatedCSRsInitialized) |
643 | UpdatedCSRs.clear(); |
644 | |
645 | append_range(C&: UpdatedCSRs, R&: CSRs); |
646 | |
647 | // Zero value represents the end of the register list |
648 | // (no more registers should be pushed). |
649 | UpdatedCSRs.push_back(Elt: 0); |
650 | IsUpdatedCSRsInitialized = true; |
651 | } |
652 | |
653 | bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const { |
654 | const TargetRegisterInfo *TRI = getTargetRegisterInfo(); |
655 | for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) { |
656 | if (all_of(Range: TRI->superregs_inclusive(Reg: *Root), |
657 | P: [&](MCPhysReg Super) { return isReserved(PhysReg: Super); })) |
658 | return true; |
659 | } |
660 | return false; |
661 | } |
662 | |
663 | bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF, |
664 | MCRegister Reg) const { |
665 | return getTargetRegisterInfo()->isArgumentRegister(MF, PhysReg: Reg); |
666 | } |
667 | |
668 | bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF, |
669 | MCRegister Reg) const { |
670 | return getTargetRegisterInfo()->isFixedRegister(MF, PhysReg: Reg); |
671 | } |
672 | |
673 | bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF, |
674 | MCRegister Reg) const { |
675 | return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, PhysReg: Reg); |
676 | } |
677 | |