1//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating functions from LLVM IR into
10// Machine IR.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/FunctionLoweringInfo.h"
15#include "llvm/ADT/APInt.h"
16#include "llvm/Analysis/UniformityAnalysis.h"
17#include "llvm/CodeGen/Analysis.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/CodeGen/TargetRegisterInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/CodeGen/WasmEHFuncInfo.h"
28#include "llvm/CodeGen/WinEHFuncInfo.h"
29#include "llvm/IR/DataLayout.h"
30#include "llvm/IR/DerivedTypes.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/Instructions.h"
33#include "llvm/IR/IntrinsicInst.h"
34#include "llvm/IR/Module.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include <algorithm>
39using namespace llvm;
40
41#define DEBUG_TYPE "function-lowering-info"
42
43/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
44/// PHI nodes or outside of the basic block that defines it, or used by a
45/// switch or atomic instruction, which may expand to multiple basic blocks.
46static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
47 if (I->use_empty()) return false;
48 if (isa<PHINode>(Val: I)) return true;
49 const BasicBlock *BB = I->getParent();
50 for (const User *U : I->users())
51 if (cast<Instruction>(Val: U)->getParent() != BB || isa<PHINode>(Val: U))
52 return true;
53
54 return false;
55}
56
57static ISD::NodeType getPreferredExtendForValue(const Instruction *I) {
58 // For the users of the source value being used for compare instruction, if
59 // the number of signed predicate is greater than unsigned predicate, we
60 // prefer to use SIGN_EXTEND.
61 //
62 // With this optimization, we would be able to reduce some redundant sign or
63 // zero extension instruction, and eventually more machine CSE opportunities
64 // can be exposed.
65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
66 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
67 for (const Use &U : I->uses()) {
68 if (const auto *CI = dyn_cast<CmpInst>(Val: U.getUser())) {
69 NumOfSigned += CI->isSigned();
70 NumOfUnsigned += CI->isUnsigned();
71 }
72 if (const auto *CallI = dyn_cast<CallBase>(Val: U.getUser())) {
73 if (!CallI->isArgOperand(U: &U))
74 continue;
75 unsigned ArgNo = CallI->getArgOperandNo(U: &U);
76 NumOfUnsigned += CallI->paramHasAttr(ArgNo, Attribute::Kind: ZExt);
77 NumOfSigned += CallI->paramHasAttr(ArgNo, Attribute::Kind: SExt);
78 }
79 }
80 if (NumOfSigned > NumOfUnsigned)
81 ExtendKind = ISD::SIGN_EXTEND;
82
83 return ExtendKind;
84}
85
86void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
87 SelectionDAG *DAG) {
88 Fn = &fn;
89 MF = &mf;
90 TLI = MF->getSubtarget().getTargetLowering();
91 RegInfo = &MF->getRegInfo();
92 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
93 UA = DAG->getUniformityInfo();
94
95 // Check whether the function can return without sret-demotion.
96 SmallVector<ISD::OutputArg, 4> Outs;
97 CallingConv::ID CC = Fn->getCallingConv();
98
99 GetReturnInfo(CC, ReturnType: Fn->getReturnType(), attr: Fn->getAttributes(), Outs, TLI: *TLI,
100 DL: mf.getDataLayout());
101 CanLowerReturn =
102 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
103
104 // If this personality uses funclets, we need to do a bit more work.
105 DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
106 EHPersonality Personality = classifyEHPersonality(
107 Pers: Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
108 if (isFuncletEHPersonality(Pers: Personality)) {
109 // Calculate state numbers if we haven't already.
110 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
111 if (Personality == EHPersonality::MSVC_CXX)
112 calculateWinCXXEHStateNumbers(ParentFn: &fn, FuncInfo&: EHInfo);
113 else if (isAsynchronousEHPersonality(Pers: Personality))
114 calculateSEHStateNumbers(ParentFn: &fn, FuncInfo&: EHInfo);
115 else if (Personality == EHPersonality::CoreCLR)
116 calculateClrEHStateNumbers(Fn: &fn, FuncInfo&: EHInfo);
117
118 // Map all BB references in the WinEH data to MBBs.
119 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
120 for (WinEHHandlerType &H : TBME.HandlerArray) {
121 if (const AllocaInst *AI = H.CatchObj.Alloca)
122 CatchObjects.insert(KV: {AI, {}}).first->second.push_back(
123 NewVal: &H.CatchObj.FrameIndex);
124 else
125 H.CatchObj.FrameIndex = INT_MAX;
126 }
127 }
128 }
129
130 // Initialize the mapping of values to registers. This is only set up for
131 // instruction values that are used outside of the block that defines
132 // them.
133 const Align StackAlign = TFI->getStackAlign();
134 for (const BasicBlock &BB : *Fn) {
135 for (const Instruction &I : BB) {
136 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Val: &I)) {
137 Type *Ty = AI->getAllocatedType();
138 Align Alignment = AI->getAlign();
139
140 // Static allocas can be folded into the initial stack frame
141 // adjustment. For targets that don't realign the stack, don't
142 // do this if there is an extra alignment requirement.
143 if (AI->isStaticAlloca() &&
144 (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
145 const ConstantInt *CUI = cast<ConstantInt>(Val: AI->getArraySize());
146 uint64_t TySize =
147 MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinValue();
148
149 TySize *= CUI->getZExtValue(); // Get total allocated size.
150 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
151 int FrameIndex = INT_MAX;
152 auto Iter = CatchObjects.find(Val: AI);
153 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
154 FrameIndex = MF->getFrameInfo().CreateFixedObject(
155 Size: TySize, SPOffset: 0, /*IsImmutable=*/false, /*isAliased=*/true);
156 MF->getFrameInfo().setObjectAlignment(ObjectIdx: FrameIndex, Alignment);
157 } else {
158 FrameIndex = MF->getFrameInfo().CreateStackObject(Size: TySize, Alignment,
159 isSpillSlot: false, Alloca: AI);
160 }
161
162 // Scalable vectors and structures that contain scalable vectors may
163 // need a special StackID to distinguish them from other (fixed size)
164 // stack objects.
165 if (Ty->isScalableTy())
166 MF->getFrameInfo().setStackID(ObjectIdx: FrameIndex,
167 ID: TFI->getStackIDForScalableVectors());
168
169 StaticAllocaMap[AI] = FrameIndex;
170 // Update the catch handler information.
171 if (Iter != CatchObjects.end()) {
172 for (int *CatchObjPtr : Iter->second)
173 *CatchObjPtr = FrameIndex;
174 }
175 } else {
176 // FIXME: Overaligned static allocas should be grouped into
177 // a single dynamic allocation instead of using a separate
178 // stack allocation for each one.
179 // Inform the Frame Information that we have variable-sized objects.
180 MF->getFrameInfo().CreateVariableSizedObject(
181 Alignment: Alignment <= StackAlign ? Align(1) : Alignment, Alloca: AI);
182 }
183 } else if (auto *Call = dyn_cast<CallBase>(Val: &I)) {
184 // Look for inline asm that clobbers the SP register.
185 if (Call->isInlineAsm()) {
186 Register SP = TLI->getStackPointerRegisterToSaveRestore();
187 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
188 std::vector<TargetLowering::AsmOperandInfo> Ops =
189 TLI->ParseConstraints(DL: Fn->getParent()->getDataLayout(), TRI,
190 Call: *Call);
191 for (TargetLowering::AsmOperandInfo &Op : Ops) {
192 if (Op.Type == InlineAsm::isClobber) {
193 // Clobbers don't have SDValue operands, hence SDValue().
194 TLI->ComputeConstraintToUse(OpInfo&: Op, Op: SDValue(), DAG);
195 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
196 TLI->getRegForInlineAsmConstraint(TRI, Constraint: Op.ConstraintCode,
197 VT: Op.ConstraintVT);
198 if (PhysReg.first == SP)
199 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
200 }
201 }
202 }
203 // Look for calls to the @llvm.va_start intrinsic. We can omit some
204 // prologue boilerplate for variadic functions that don't examine their
205 // arguments.
206 if (const auto *II = dyn_cast<IntrinsicInst>(Val: &I)) {
207 if (II->getIntrinsicID() == Intrinsic::vastart)
208 MF->getFrameInfo().setHasVAStart(true);
209 }
210
211 // If we have a musttail call in a variadic function, we need to ensure
212 // we forward implicit register parameters.
213 if (const auto *CI = dyn_cast<CallInst>(Val: &I)) {
214 if (CI->isMustTailCall() && Fn->isVarArg())
215 MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
216 }
217 }
218
219 // Mark values used outside their block as exported, by allocating
220 // a virtual register for them.
221 if (isUsedOutsideOfDefiningBlock(I: &I))
222 if (!isa<AllocaInst>(Val: I) || !StaticAllocaMap.count(Val: cast<AllocaInst>(Val: &I)))
223 InitializeRegForValue(V: &I);
224
225 // Decide the preferred extend type for a value.
226 PreferredExtendType[&I] = getPreferredExtendForValue(I: &I);
227 }
228 }
229
230 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
231 // also creates the initial PHI MachineInstrs, though none of the input
232 // operands are populated.
233 for (const BasicBlock &BB : *Fn) {
234 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
235 // are really data, and no instructions can live here.
236 if (BB.isEHPad()) {
237 const Instruction *PadInst = BB.getFirstNonPHI();
238 // If this is a non-landingpad EH pad, mark this function as using
239 // funclets.
240 // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
241 // setting this in such cases in order to improve frame layout.
242 if (!isa<LandingPadInst>(Val: PadInst)) {
243 MF->setHasEHScopes(true);
244 MF->setHasEHFunclets(true);
245 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
246 }
247 if (isa<CatchSwitchInst>(Val: PadInst)) {
248 assert(&*BB.begin() == PadInst &&
249 "WinEHPrepare failed to remove PHIs from imaginary BBs");
250 continue;
251 }
252 if (isa<FuncletPadInst>(Val: PadInst) &&
253 Personality != EHPersonality::Wasm_CXX)
254 assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
255 }
256
257 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB: &BB);
258 MBBMap[&BB] = MBB;
259 MF->push_back(MBB);
260
261 // Transfer the address-taken flag. This is necessary because there could
262 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
263 // the first one should be marked.
264 if (BB.hasAddressTaken())
265 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
266
267 // Mark landing pad blocks.
268 if (BB.isEHPad())
269 MBB->setIsEHPad();
270
271 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
272 // appropriate.
273 for (const PHINode &PN : BB.phis()) {
274 if (PN.use_empty())
275 continue;
276
277 // Skip empty types
278 if (PN.getType()->isEmptyTy())
279 continue;
280
281 DebugLoc DL = PN.getDebugLoc();
282 unsigned PHIReg = ValueMap[&PN];
283 assert(PHIReg && "PHI node does not have an assigned virtual register!");
284
285 SmallVector<EVT, 4> ValueVTs;
286 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty: PN.getType(), ValueVTs);
287 for (EVT VT : ValueVTs) {
288 unsigned NumRegisters = TLI->getNumRegisters(Context&: Fn->getContext(), VT);
289 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
290 for (unsigned i = 0; i != NumRegisters; ++i)
291 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::PHI), DestReg: PHIReg + i);
292 PHIReg += NumRegisters;
293 }
294 }
295 }
296
297 if (isFuncletEHPersonality(Pers: Personality)) {
298 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
299
300 // Map all BB references in the WinEH data to MBBs.
301 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
302 for (WinEHHandlerType &H : TBME.HandlerArray) {
303 if (H.Handler)
304 H.Handler = MBBMap[cast<const BasicBlock *>(Val&: H.Handler)];
305 }
306 }
307 for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
308 if (UME.Cleanup)
309 UME.Cleanup = MBBMap[cast<const BasicBlock *>(Val&: UME.Cleanup)];
310 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
311 const auto *BB = cast<const BasicBlock *>(Val&: UME.Handler);
312 UME.Handler = MBBMap[BB];
313 }
314 for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
315 const auto *BB = cast<const BasicBlock *>(Val&: CME.Handler);
316 CME.Handler = MBBMap[BB];
317 }
318 } else if (Personality == EHPersonality::Wasm_CXX) {
319 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
320 calculateWasmEHInfo(F: &fn, EHInfo);
321
322 // Map all BB references in the Wasm EH data to MBBs.
323 DenseMap<BBOrMBB, BBOrMBB> SrcToUnwindDest;
324 for (auto &KV : EHInfo.SrcToUnwindDest) {
325 const auto *Src = cast<const BasicBlock *>(Val&: KV.first);
326 const auto *Dest = cast<const BasicBlock *>(Val&: KV.second);
327 SrcToUnwindDest[MBBMap[Src]] = MBBMap[Dest];
328 }
329 EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest);
330 DenseMap<BBOrMBB, SmallPtrSet<BBOrMBB, 4>> UnwindDestToSrcs;
331 for (auto &KV : EHInfo.UnwindDestToSrcs) {
332 const auto *Dest = cast<const BasicBlock *>(Val&: KV.first);
333 UnwindDestToSrcs[MBBMap[Dest]] = SmallPtrSet<BBOrMBB, 4>();
334 for (const auto P : KV.second)
335 UnwindDestToSrcs[MBBMap[Dest]].insert(
336 Ptr: MBBMap[cast<const BasicBlock *>(Val: P)]);
337 }
338 EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs);
339 }
340}
341
342/// clear - Clear out all the function-specific state. This returns this
343/// FunctionLoweringInfo to an empty state, ready to be used for a
344/// different function.
345void FunctionLoweringInfo::clear() {
346 MBBMap.clear();
347 ValueMap.clear();
348 VirtReg2Value.clear();
349 StaticAllocaMap.clear();
350 LiveOutRegInfo.clear();
351 VisitedBBs.clear();
352 ArgDbgValues.clear();
353 DescribedArgs.clear();
354 ByValArgFrameIndexMap.clear();
355 RegFixups.clear();
356 RegsWithFixups.clear();
357 StatepointStackSlots.clear();
358 StatepointRelocationMaps.clear();
359 PreferredExtendType.clear();
360 PreprocessedDbgDeclares.clear();
361 PreprocessedDPVDeclares.clear();
362}
363
364/// CreateReg - Allocate a single virtual register for the given type.
365Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
366 return RegInfo->createVirtualRegister(RegClass: TLI->getRegClassFor(VT, isDivergent));
367}
368
369/// CreateRegs - Allocate the appropriate number of virtual registers of
370/// the correctly promoted or expanded types. Assign these registers
371/// consecutive vreg numbers and return the first assigned number.
372///
373/// In the case that the given value has struct or array type, this function
374/// will assign registers for each member or element.
375///
376Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
377 SmallVector<EVT, 4> ValueVTs;
378 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty, ValueVTs);
379
380 Register FirstReg;
381 for (EVT ValueVT : ValueVTs) {
382 MVT RegisterVT = TLI->getRegisterType(Context&: Ty->getContext(), VT: ValueVT);
383
384 unsigned NumRegs = TLI->getNumRegisters(Context&: Ty->getContext(), VT: ValueVT);
385 for (unsigned i = 0; i != NumRegs; ++i) {
386 Register R = CreateReg(VT: RegisterVT, isDivergent);
387 if (!FirstReg) FirstReg = R;
388 }
389 }
390 return FirstReg;
391}
392
393Register FunctionLoweringInfo::CreateRegs(const Value *V) {
394 return CreateRegs(Ty: V->getType(), isDivergent: UA && UA->isDivergent(V) &&
395 !TLI->requiresUniformRegister(MF&: *MF, V));
396}
397
398/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
399/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
400/// the register's LiveOutInfo is for a smaller bit width, it is extended to
401/// the larger bit width by zero extension. The bit width must be no smaller
402/// than the LiveOutInfo's existing bit width.
403const FunctionLoweringInfo::LiveOutInfo *
404FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) {
405 if (!LiveOutRegInfo.inBounds(n: Reg))
406 return nullptr;
407
408 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
409 if (!LOI->IsValid)
410 return nullptr;
411
412 if (BitWidth > LOI->Known.getBitWidth()) {
413 LOI->NumSignBits = 1;
414 LOI->Known = LOI->Known.anyext(BitWidth);
415 }
416
417 return LOI;
418}
419
420/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
421/// register based on the LiveOutInfo of its operands.
422void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
423 Type *Ty = PN->getType();
424 if (!Ty->isIntegerTy() || Ty->isVectorTy())
425 return;
426
427 SmallVector<EVT, 1> ValueVTs;
428 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty, ValueVTs);
429 assert(ValueVTs.size() == 1 &&
430 "PHIs with non-vector integer types should have a single VT.");
431 EVT IntVT = ValueVTs[0];
432
433 if (TLI->getNumRegisters(Context&: PN->getContext(), VT: IntVT) != 1)
434 return;
435 IntVT = TLI->getRegisterType(Context&: PN->getContext(), VT: IntVT);
436 unsigned BitWidth = IntVT.getSizeInBits();
437
438 auto It = ValueMap.find(Val: PN);
439 if (It == ValueMap.end())
440 return;
441
442 Register DestReg = It->second;
443 if (DestReg == 0)
444 return;
445 assert(DestReg.isVirtual() && "Expected a virtual reg");
446 LiveOutRegInfo.grow(n: DestReg);
447 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
448
449 Value *V = PN->getIncomingValue(i: 0);
450 if (isa<UndefValue>(Val: V) || isa<ConstantExpr>(Val: V)) {
451 DestLOI.NumSignBits = 1;
452 DestLOI.Known = KnownBits(BitWidth);
453 return;
454 }
455
456 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
457 APInt Val;
458 if (TLI->signExtendConstant(C: CI))
459 Val = CI->getValue().sext(width: BitWidth);
460 else
461 Val = CI->getValue().zext(width: BitWidth);
462 DestLOI.NumSignBits = Val.getNumSignBits();
463 DestLOI.Known = KnownBits::makeConstant(C: Val);
464 } else {
465 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
466 "CopyToReg node was created.");
467 Register SrcReg = ValueMap[V];
468 if (!SrcReg.isVirtual()) {
469 DestLOI.IsValid = false;
470 return;
471 }
472 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(Reg: SrcReg, BitWidth);
473 if (!SrcLOI) {
474 DestLOI.IsValid = false;
475 return;
476 }
477 DestLOI = *SrcLOI;
478 }
479
480 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
481 DestLOI.Known.One.getBitWidth() == BitWidth &&
482 "Masks should have the same bit width as the type.");
483
484 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
485 Value *V = PN->getIncomingValue(i);
486 if (isa<UndefValue>(Val: V) || isa<ConstantExpr>(Val: V)) {
487 DestLOI.NumSignBits = 1;
488 DestLOI.Known = KnownBits(BitWidth);
489 return;
490 }
491
492 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
493 APInt Val;
494 if (TLI->signExtendConstant(C: CI))
495 Val = CI->getValue().sext(width: BitWidth);
496 else
497 Val = CI->getValue().zext(width: BitWidth);
498 DestLOI.NumSignBits = std::min(a: DestLOI.NumSignBits, b: Val.getNumSignBits());
499 DestLOI.Known.Zero &= ~Val;
500 DestLOI.Known.One &= Val;
501 continue;
502 }
503
504 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
505 "its CopyToReg node was created.");
506 Register SrcReg = ValueMap[V];
507 if (!SrcReg.isVirtual()) {
508 DestLOI.IsValid = false;
509 return;
510 }
511 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(Reg: SrcReg, BitWidth);
512 if (!SrcLOI) {
513 DestLOI.IsValid = false;
514 return;
515 }
516 DestLOI.NumSignBits = std::min(a: DestLOI.NumSignBits, b: SrcLOI->NumSignBits);
517 DestLOI.Known = DestLOI.Known.intersectWith(RHS: SrcLOI->Known);
518 }
519}
520
521/// setArgumentFrameIndex - Record frame index for the byval
522/// argument. This overrides previous frame index entry for this argument,
523/// if any.
524void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
525 int FI) {
526 ByValArgFrameIndexMap[A] = FI;
527}
528
529/// getArgumentFrameIndex - Get frame index for the byval argument.
530/// If the argument does not have any assigned frame index then 0 is
531/// returned.
532int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
533 auto I = ByValArgFrameIndexMap.find(Val: A);
534 if (I != ByValArgFrameIndexMap.end())
535 return I->second;
536 LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
537 return INT_MAX;
538}
539
540Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
541 const Value *CPI, const TargetRegisterClass *RC) {
542 MachineRegisterInfo &MRI = MF->getRegInfo();
543 auto I = CatchPadExceptionPointers.insert(KV: {CPI, 0});
544 Register &VReg = I.first->second;
545 if (I.second)
546 VReg = MRI.createVirtualRegister(RegClass: RC);
547 assert(VReg && "null vreg in exception pointer table!");
548 return VReg;
549}
550
551const Value *
552FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
553 if (VirtReg2Value.empty()) {
554 SmallVector<EVT, 4> ValueVTs;
555 for (auto &P : ValueMap) {
556 ValueVTs.clear();
557 ComputeValueVTs(TLI: *TLI, DL: Fn->getParent()->getDataLayout(),
558 Ty: P.first->getType(), ValueVTs);
559 unsigned Reg = P.second;
560 for (EVT VT : ValueVTs) {
561 unsigned NumRegisters = TLI->getNumRegisters(Context&: Fn->getContext(), VT);
562 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
563 VirtReg2Value[Reg++] = P.first;
564 }
565 }
566 }
567 return VirtReg2Value.lookup(Val: Vreg);
568}
569

source code of llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp