| 1 | //===- TargetSubtargetInfo.cpp - General Target Information ----------------==// |
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| 2 | // |
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| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
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| 4 | // See https://llvm.org/LICENSE.txt for license information. |
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| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
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| 6 | // |
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| 7 | //===----------------------------------------------------------------------===// |
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| 8 | // |
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| 9 | /// \file This file describes the general parts of a Subtarget. |
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| 10 | // |
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| 11 | //===----------------------------------------------------------------------===// |
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| 12 | |
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| 13 | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
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| 14 | |
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| 15 | using namespace llvm; |
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| 16 | |
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| 17 | TargetSubtargetInfo::TargetSubtargetInfo( |
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| 18 | const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, |
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| 19 | ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD, |
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| 20 | const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, |
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| 21 | const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, |
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| 22 | const unsigned *FP) |
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| 23 | : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {} |
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| 24 | |
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| 25 | TargetSubtargetInfo::~TargetSubtargetInfo() = default; |
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| 26 | |
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| 27 | bool TargetSubtargetInfo::enableAtomicExpand() const { |
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| 28 | return true; |
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| 29 | } |
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| 30 | |
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| 31 | bool TargetSubtargetInfo::enableIndirectBrExpand() const { |
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| 32 | return false; |
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| 33 | } |
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| 34 | |
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| 35 | bool TargetSubtargetInfo::enableMachineScheduler() const { |
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| 36 | return false; |
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| 37 | } |
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| 38 | |
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| 39 | bool TargetSubtargetInfo::enableJoinGlobalCopies() const { |
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| 40 | return enableMachineScheduler(); |
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| 41 | } |
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| 42 | |
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| 43 | bool TargetSubtargetInfo::enableRALocalReassignment( |
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| 44 | CodeGenOptLevel OptLevel) const { |
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| 45 | return true; |
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| 46 | } |
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| 47 | |
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| 48 | bool TargetSubtargetInfo::enablePostRAScheduler() const { |
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| 49 | return getSchedModel().PostRAScheduler; |
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| 50 | } |
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| 51 | |
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| 52 | bool TargetSubtargetInfo::enablePostRAMachineScheduler() const { |
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| 53 | return enableMachineScheduler() && enablePostRAScheduler(); |
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| 54 | } |
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| 55 | |
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| 56 | bool TargetSubtargetInfo::useAA() const { |
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| 57 | return false; |
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| 58 | } |
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| 59 | |
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| 60 | void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { } |
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| 61 | |
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