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40
41#ifndef QGLOBAL_H
42# include <QtCore/qglobal.h>
43#endif
44
45#ifndef QPROCESSORDETECTION_H
46#define QPROCESSORDETECTION_H
47
48/*
49 This file uses preprocessor #defines to set various Q_PROCESSOR_* #defines
50 based on the following patterns:
51
52 Q_PROCESSOR_{FAMILY}
53 Q_PROCESSOR_{FAMILY}_{VARIANT}
54 Q_PROCESSOR_{FAMILY}_{REVISION}
55
56 The first is always defined. Defines for the various revisions/variants are
57 optional and usually dependent on how the compiler was invoked. Variants
58 that are a superset of another should have a define for the superset.
59
60 In addition to the processor family, variants, and revisions, we also set
61 Q_BYTE_ORDER appropriately for the target processor. For bi-endian
62 processors, we try to auto-detect the byte order using the __BIG_ENDIAN__,
63 __LITTLE_ENDIAN__, or __BYTE_ORDER__ preprocessor macros.
64
65 Note: when adding support for new processors, be sure to update
66 config.tests/arch/arch.cpp to ensure that configure can detect the target
67 and host architectures.
68*/
69
70/* Machine byte-order, reuse preprocessor provided macros when available */
71#if defined(__ORDER_BIG_ENDIAN__)
72# define Q_BIG_ENDIAN __ORDER_BIG_ENDIAN__
73#else
74# define Q_BIG_ENDIAN 4321
75#endif
76#if defined(__ORDER_LITTLE_ENDIAN__)
77# define Q_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
78#else
79# define Q_LITTLE_ENDIAN 1234
80#endif
81
82/*
83 Alpha family, no revisions or variants
84
85 Alpha is bi-endian, use endianness auto-detection implemented below.
86*/
87// #elif defined(__alpha__) || defined(_M_ALPHA)
88// # define Q_PROCESSOR_ALPHA
89// Q_BYTE_ORDER not defined, use endianness auto-detection
90
91/*
92 ARM family, known revisions: V5, V6, V7, V8
93
94 ARM is bi-endian, detect using __ARMEL__ or __ARMEB__, falling back to
95 auto-detection implemented below.
96*/
97#if defined(__arm__) || defined(__TARGET_ARCH_ARM) || defined(_M_ARM) || defined(__aarch64__) || defined(__ARM64__)
98# if defined(__aarch64__) || defined(__ARM64__)
99# define Q_PROCESSOR_ARM_64
100# define Q_PROCESSOR_WORDSIZE 8
101# else
102# define Q_PROCESSOR_ARM_32
103# endif
104# if defined(__ARM_ARCH) && __ARM_ARCH > 1
105# define Q_PROCESSOR_ARM __ARM_ARCH
106# elif defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM > 1
107# define Q_PROCESSOR_ARM __TARGET_ARCH_ARM
108# elif defined(_M_ARM) && _M_ARM > 1
109# define Q_PROCESSOR_ARM _M_ARM
110# elif defined(__ARM64_ARCH_8__) \
111 || defined(__aarch64__) \
112 || defined(__ARMv8__) \
113 || defined(__ARMv8_A__)
114# define Q_PROCESSOR_ARM 8
115# elif defined(__ARM_ARCH_7__) \
116 || defined(__ARM_ARCH_7A__) \
117 || defined(__ARM_ARCH_7R__) \
118 || defined(__ARM_ARCH_7M__) \
119 || defined(__ARM_ARCH_7S__) \
120 || defined(_ARM_ARCH_7) \
121 || defined(__CORE_CORTEXA__)
122# define Q_PROCESSOR_ARM 7
123# elif defined(__ARM_ARCH_6__) \
124 || defined(__ARM_ARCH_6J__) \
125 || defined(__ARM_ARCH_6T2__) \
126 || defined(__ARM_ARCH_6Z__) \
127 || defined(__ARM_ARCH_6K__) \
128 || defined(__ARM_ARCH_6ZK__) \
129 || defined(__ARM_ARCH_6M__)
130# define Q_PROCESSOR_ARM 6
131# elif defined(__ARM_ARCH_5TEJ__) \
132 || defined(__ARM_ARCH_5TE__)
133# define Q_PROCESSOR_ARM 5
134# else
135# define Q_PROCESSOR_ARM 0
136# endif
137# if Q_PROCESSOR_ARM >= 8
138# define Q_PROCESSOR_ARM_V8
139# endif
140# if Q_PROCESSOR_ARM >= 7
141# define Q_PROCESSOR_ARM_V7
142# endif
143# if Q_PROCESSOR_ARM >= 6
144# define Q_PROCESSOR_ARM_V6
145# endif
146# if Q_PROCESSOR_ARM >= 5
147# define Q_PROCESSOR_ARM_V5
148# else
149# error "ARM architecture too old"
150# endif
151# if defined(__ARMEL__)
152# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
153# elif defined(__ARMEB__)
154# define Q_BYTE_ORDER Q_BIG_ENDIAN
155# else
156// Q_BYTE_ORDER not defined, use endianness auto-detection
157#endif
158
159/*
160 AVR32 family, no revisions or variants
161
162 AVR32 is big-endian.
163*/
164// #elif defined(__avr32__)
165// # define Q_PROCESSOR_AVR32
166// # define Q_BYTE_ORDER Q_BIG_ENDIAN
167
168/*
169 Blackfin family, no revisions or variants
170
171 Blackfin is little-endian.
172*/
173// #elif defined(__bfin__)
174// # define Q_PROCESSOR_BLACKFIN
175// # define Q_BYTE_ORDER Q_LITTLE_ENDIAN
176
177/*
178 X86 family, known variants: 32- and 64-bit
179
180 X86 is little-endian.
181*/
182#elif defined(__i386) || defined(__i386__) || defined(_M_IX86)
183# define Q_PROCESSOR_X86_32
184# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
185# define Q_PROCESSOR_WORDSIZE 4
186
187/*
188 * We define Q_PROCESSOR_X86 == 6 for anything above a equivalent or better
189 * than a Pentium Pro (the processor whose architecture was called P6) or an
190 * Athlon.
191 *
192 * All processors since the Pentium III and the Athlon 4 have SSE support, so
193 * we use that to detect. That leaves the original Athlon, Pentium Pro and
194 * Pentium II.
195 */
196
197# if defined(_M_IX86)
198# define Q_PROCESSOR_X86 (_M_IX86/100)
199# elif defined(__i686__) || defined(__athlon__) || defined(__SSE__) || defined(__pentiumpro__)
200# define Q_PROCESSOR_X86 6
201# elif defined(__i586__) || defined(__k6__) || defined(__pentium__)
202# define Q_PROCESSOR_X86 5
203# elif defined(__i486__) || defined(__80486__)
204# define Q_PROCESSOR_X86 4
205# else
206# define Q_PROCESSOR_X86 3
207# endif
208
209#elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
210# define Q_PROCESSOR_X86 6
211# define Q_PROCESSOR_X86_64
212# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
213# define Q_PROCESSOR_WORDSIZE 8
214
215/*
216 Itanium (IA-64) family, no revisions or variants
217
218 Itanium is bi-endian, use endianness auto-detection implemented below.
219*/
220#elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)
221# define Q_PROCESSOR_IA64
222# define Q_PROCESSOR_WORDSIZE 8
223// Q_BYTE_ORDER not defined, use endianness auto-detection
224
225/*
226 MIPS family, known revisions: I, II, III, IV, 32, 64
227
228 MIPS is bi-endian, use endianness auto-detection implemented below.
229*/
230#elif defined(__mips) || defined(__mips__) || defined(_M_MRX000)
231# define Q_PROCESSOR_MIPS
232# if defined(_MIPS_ARCH_MIPS1) || (defined(__mips) && __mips - 0 >= 1)
233# define Q_PROCESSOR_MIPS_I
234# endif
235# if defined(_MIPS_ARCH_MIPS2) || (defined(__mips) && __mips - 0 >= 2)
236# define Q_PROCESSOR_MIPS_II
237# endif
238# if defined(_MIPS_ARCH_MIPS3) || (defined(__mips) && __mips - 0 >= 3)
239# define Q_PROCESSOR_MIPS_III
240# endif
241# if defined(_MIPS_ARCH_MIPS4) || (defined(__mips) && __mips - 0 >= 4)
242# define Q_PROCESSOR_MIPS_IV
243# endif
244# if defined(_MIPS_ARCH_MIPS5) || (defined(__mips) && __mips - 0 >= 5)
245# define Q_PROCESSOR_MIPS_V
246# endif
247# if defined(_MIPS_ARCH_MIPS32) || defined(__mips32) || (defined(__mips) && __mips - 0 >= 32)
248# define Q_PROCESSOR_MIPS_32
249# endif
250# if defined(_MIPS_ARCH_MIPS64) || defined(__mips64)
251# define Q_PROCESSOR_MIPS_64
252# define Q_PROCESSOR_WORDSIZE 8
253# endif
254# if defined(__MIPSEL__)
255# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
256# elif defined(__MIPSEB__)
257# define Q_BYTE_ORDER Q_BIG_ENDIAN
258# else
259// Q_BYTE_ORDER not defined, use endianness auto-detection
260# endif
261
262/*
263 Power family, known variants: 32- and 64-bit
264
265 There are many more known variants/revisions that we do not handle/detect.
266 See http://en.wikipedia.org/wiki/Power_Architecture
267 and http://en.wikipedia.org/wiki/File:PowerISA-evolution.svg
268
269 Power is bi-endian, use endianness auto-detection implemented below.
270*/
271#elif defined(__ppc__) || defined(__ppc) || defined(__powerpc__) \
272 || defined(_ARCH_COM) || defined(_ARCH_PWR) || defined(_ARCH_PPC) \
273 || defined(_M_MPPC) || defined(_M_PPC)
274# define Q_PROCESSOR_POWER
275# if defined(__ppc64__) || defined(__powerpc64__) || defined(__64BIT__)
276# define Q_PROCESSOR_POWER_64
277# define Q_PROCESSOR_WORDSIZE 8
278# else
279# define Q_PROCESSOR_POWER_32
280# endif
281// Q_BYTE_ORDER not defined, use endianness auto-detection
282
283/*
284 S390 family, known variant: S390X (64-bit)
285
286 S390 is big-endian.
287*/
288#elif defined(__s390__)
289# define Q_PROCESSOR_S390
290# if defined(__s390x__)
291# define Q_PROCESSOR_S390_X
292# endif
293# define Q_BYTE_ORDER Q_BIG_ENDIAN
294
295/*
296 SuperH family, optional revision: SH-4A
297
298 SuperH is bi-endian, use endianness auto-detection implemented below.
299*/
300// #elif defined(__sh__)
301// # define Q_PROCESSOR_SH
302// # if defined(__sh4a__)
303// # define Q_PROCESSOR_SH_4A
304// # endif
305// Q_BYTE_ORDER not defined, use endianness auto-detection
306
307/*
308 SPARC family, optional revision: V9
309
310 SPARC is big-endian only prior to V9, while V9 is bi-endian with big-endian
311 as the default byte order. Assume all SPARC systems are big-endian.
312*/
313#elif defined(__sparc__)
314# define Q_PROCESSOR_SPARC
315# if defined(__sparc_v9__)
316# define Q_PROCESSOR_SPARC_V9
317# endif
318# if defined(__sparc64__)
319# define Q_PROCESSOR_SPARC_64
320# endif
321# define Q_BYTE_ORDER Q_BIG_ENDIAN
322
323#endif
324
325/*
326 NOTE:
327 GCC 4.6 added __BYTE_ORDER__, __ORDER_BIG_ENDIAN__, __ORDER_LITTLE_ENDIAN__
328 and __ORDER_PDP_ENDIAN__ in SVN r165881. If you are using GCC 4.6 or newer,
329 this code will properly detect your target byte order; if you are not, and
330 the __LITTLE_ENDIAN__ or __BIG_ENDIAN__ macros are not defined, then this
331 code will fail to detect the target byte order.
332*/
333// Some processors support either endian format, try to detect which we are using.
334#if !defined(Q_BYTE_ORDER)
335# if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == Q_BIG_ENDIAN || __BYTE_ORDER__ == Q_LITTLE_ENDIAN)
336// Reuse __BYTE_ORDER__ as-is, since our Q_*_ENDIAN #defines match the preprocessor defaults
337# define Q_BYTE_ORDER __BYTE_ORDER__
338# elif defined(__BIG_ENDIAN__) || defined(_big_endian__) || defined(_BIG_ENDIAN)
339# define Q_BYTE_ORDER Q_BIG_ENDIAN
340# elif defined(__LITTLE_ENDIAN__) || defined(_little_endian__) || defined(_LITTLE_ENDIAN) \
341 || defined(WINAPI_FAMILY) // WinRT is always little-endian according to MSDN.
342# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
343# else
344# error "Unable to determine byte order!"
345# endif
346#endif
347
348/*
349 Size of a pointer and the machine register size. We detect a 64-bit system by:
350 * GCC and compatible compilers (Clang, ICC on OS X and Windows) always define
351 __SIZEOF_POINTER__. This catches all known cases of ILP32 builds on 64-bit
352 processors.
353 * Most other Unix compilers define __LP64__ or _LP64 on 64-bit mode
354 (Long and Pointer 64-bit)
355 * If Q_PROCESSOR_WORDSIZE was defined above, it's assumed to match the pointer
356 size.
357 Otherwise, we assume to be 32-bit and then check in qglobal.cpp that it is right.
358*/
359
360#if defined __SIZEOF_POINTER__
361# define QT_POINTER_SIZE __SIZEOF_POINTER__
362#elif defined(__LP64__) || defined(_LP64)
363# define QT_POINTER_SIZE 8
364#elif defined(Q_PROCESSOR_WORDSIZE)
365# define QT_POINTER_SIZE Q_PROCESSOR_WORDSIZE
366#else
367# define QT_POINTER_SIZE 4
368#endif
369
370/*
371 Define Q_PROCESSOR_WORDSIZE to be the size of the machine's word (usually,
372 the size of the register). On some architectures where a pointer could be
373 smaller than the register, the macro is defined above.
374
375 Falls back to QT_POINTER_SIZE if not set explicitly for the platform.
376*/
377#ifndef Q_PROCESSOR_WORDSIZE
378# define Q_PROCESSOR_WORDSIZE QT_POINTER_SIZE
379#endif
380
381
382#endif // QPROCESSORDETECTION_H
383