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1 | /* FPU control word definitions. ARM VFP version. |
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2 | Copyright (C) 2004-2022 Free Software Foundation, Inc. |
3 | This file is part of the GNU C Library. |
4 | |
5 | The GNU C Library is free software; you can redistribute it and/or |
6 | modify it under the terms of the GNU Lesser General Public |
7 | License as published by the Free Software Foundation; either |
8 | version 2.1 of the License, or (at your option) any later version. |
9 | |
10 | The GNU C Library is distributed in the hope that it will be useful, |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
13 | Lesser General Public License for more details. |
14 | |
15 | You should have received a copy of the GNU Lesser General Public |
16 | License along with the GNU C Library. If not, see |
17 | <https://www.gnu.org/licenses/>. */ |
18 | |
19 | #ifndef _FPU_CONTROL_H |
20 | #define _FPU_CONTROL_H |
21 | |
22 | #if !(defined(_LIBC) && !defined(_LIBC_TEST)) && defined(__SOFTFP__) |
23 | |
24 | #define _FPU_RESERVED 0xffffffff |
25 | #define _FPU_DEFAULT 0x00000000 |
26 | typedef unsigned int fpu_control_t; |
27 | #define _FPU_GETCW(cw) (cw) = 0 |
28 | #define _FPU_SETCW(cw) (void) (cw) |
29 | extern fpu_control_t __fpu_control; |
30 | |
31 | #else |
32 | |
33 | /* masking of interrupts */ |
34 | #define _FPU_MASK_IM 0x00000100 /* invalid operation */ |
35 | #define _FPU_MASK_ZM 0x00000200 /* divide by zero */ |
36 | #define _FPU_MASK_OM 0x00000400 /* overflow */ |
37 | #define _FPU_MASK_UM 0x00000800 /* underflow */ |
38 | #define _FPU_MASK_PM 0x00001000 /* inexact */ |
39 | |
40 | #define _FPU_MASK_NZCV 0xf0000000 /* NZCV flags */ |
41 | #define _FPU_MASK_RM 0x00c00000 /* rounding mode */ |
42 | #define _FPU_MASK_EXCEPT 0x00001f1f /* all exception flags */ |
43 | |
44 | /* Some bits in the FPSCR are not yet defined. They must be preserved when |
45 | modifying the contents. */ |
46 | #define _FPU_RESERVED 0x00086060 |
47 | #define _FPU_DEFAULT 0x00000000 |
48 | |
49 | /* Default + exceptions enabled. */ |
50 | #define _FPU_IEEE (_FPU_DEFAULT | 0x00001f00) |
51 | |
52 | /* Type of the control word. */ |
53 | typedef unsigned int fpu_control_t; |
54 | |
55 | /* Macros for accessing the hardware control word. */ |
56 | #ifdef __SOFTFP__ |
57 | /* This is fmrx %0, fpscr. */ |
58 | # define _FPU_GETCW(cw) \ |
59 | __asm__ __volatile__ ("mrc p10, 7, %0, cr1, cr0, 0" : "=r" (cw)) |
60 | /* This is fmxr fpscr, %0. */ |
61 | # define _FPU_SETCW(cw) \ |
62 | __asm__ __volatile__ ("mcr p10, 7, %0, cr1, cr0, 0" : : "r" (cw)) |
63 | #else |
64 | # define _FPU_GETCW(cw) \ |
65 | __asm__ __volatile__ ("vmrs %0, fpscr" : "=r" (cw)) |
66 | # define _FPU_SETCW(cw) \ |
67 | __asm__ __volatile__ ("vmsr fpscr, %0" : : "r" (cw)) |
68 | #endif |
69 | |
70 | /* Default control word set at startup. */ |
71 | extern fpu_control_t __fpu_control; |
72 | |
73 | #endif /* __SOFTFP__ */ |
74 | |
75 | #endif /* _FPU_CONTROL_H */ |
76 |
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