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1/* Copyright (C) 2003-2019 Free Software Foundation, Inc.
2
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library. If not, see
17 <http://www.gnu.org/licenses/>. */
18
19#include <stdint.h>
20#include <sysdep.h>
21
22
23typedef int8_t atomic8_t;
24typedef uint8_t uatomic8_t;
25typedef int_fast8_t atomic_fast8_t;
26typedef uint_fast8_t uatomic_fast8_t;
27
28typedef int32_t atomic32_t;
29typedef uint32_t uatomic32_t;
30typedef int_fast32_t atomic_fast32_t;
31typedef uint_fast32_t uatomic_fast32_t;
32
33typedef intptr_t atomicptr_t;
34typedef uintptr_t uatomicptr_t;
35typedef intmax_t atomic_max_t;
36typedef uintmax_t uatomic_max_t;
37
38#define __HAVE_64B_ATOMICS 0
39#define USE_ATOMIC_COMPILER_BUILTINS 0
40
41/* XXX Is this actually correct? */
42#define ATOMIC_EXCHANGE_USES_CAS 1
43
44
45/* Microblaze does not have byte and halfword forms of load and reserve and
46 store conditional. So for microblaze we stub out the 8- and 16-bit forms. */
47#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
48 (abort (), 0)
49
50#define __arch_compare_and_exchange_bool_16_acq(mem, newval, oldval) \
51 (abort (), 0)
52
53#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
54 ({ \
55 __typeof (*(mem)) __tmp; \
56 __typeof (mem) __memp = (mem); \
57 int test; \
58 __asm __volatile ( \
59 " addc r0, r0, r0;" \
60 "1: lwx %0, %3, r0;" \
61 " addic %1, r0, 0;" \
62 " bnei %1, 1b;" \
63 " cmp %1, %0, %4;" \
64 " bnei %1, 2f;" \
65 " swx %5, %3, r0;" \
66 " addic %1, r0, 0;" \
67 " bnei %1, 1b;" \
68 "2:" \
69 : "=&r" (__tmp), \
70 "=&r" (test), \
71 "=m" (*__memp) \
72 : "r" (__memp), \
73 "r" (oldval), \
74 "r" (newval) \
75 : "cc", "memory"); \
76 __tmp; \
77 })
78
79#define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
80 (abort (), (__typeof (*mem)) 0)
81
82#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
83 ({ \
84 __typeof (*(mem)) __result; \
85 if (sizeof (*mem) == 4) \
86 __result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
87 else if (sizeof (*mem) == 8) \
88 __result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
89 else \
90 abort (); \
91 __result; \
92 })
93
94#define atomic_compare_and_exchange_val_rel(mem, newval, oldval) \
95 ({ \
96 __typeof (*(mem)) __result; \
97 if (sizeof (*mem) == 4) \
98 __result = __arch_compare_and_exchange_val_32_acq (mem, newval, oldval); \
99 else if (sizeof (*mem) == 8) \
100 __result = __arch_compare_and_exchange_val_64_acq (mem, newval, oldval); \
101 else \
102 abort (); \
103 __result; \
104 })
105
106#define __arch_atomic_exchange_32_acq(mem, value) \
107 ({ \
108 __typeof (*(mem)) __tmp; \
109 __typeof (mem) __memp = (mem); \
110 int test; \
111 __asm __volatile ( \
112 " addc r0, r0, r0;" \
113 "1: lwx %0, %4, r0;" \
114 " addic %1, r0, 0;" \
115 " bnei %1, 1b;" \
116 " swx %3, %4, r0;" \
117 " addic %1, r0, 0;" \
118 " bnei %1, 1b;" \
119 : "=&r" (__tmp), \
120 "=&r" (test), \
121 "=m" (*__memp) \
122 : "r" (value), \
123 "r" (__memp) \
124 : "cc", "memory"); \
125 __tmp; \
126 })
127
128#define __arch_atomic_exchange_64_acq(mem, newval) \
129 (abort (), (__typeof (*mem)) 0)
130
131#define atomic_exchange_acq(mem, value) \
132 ({ \
133 __typeof (*(mem)) __result; \
134 if (sizeof (*mem) == 4) \
135 __result = __arch_atomic_exchange_32_acq (mem, value); \
136 else if (sizeof (*mem) == 8) \
137 __result = __arch_atomic_exchange_64_acq (mem, value); \
138 else \
139 abort (); \
140 __result; \
141 })
142
143#define atomic_exchange_rel(mem, value) \
144 ({ \
145 __typeof (*(mem)) __result; \
146 if (sizeof (*mem) == 4) \
147 __result = __arch_atomic_exchange_32_acq (mem, value); \
148 else if (sizeof (*mem) == 8) \
149 __result = __arch_atomic_exchange_64_acq (mem, value); \
150 else \
151 abort (); \
152 __result; \
153 })
154
155#define __arch_atomic_exchange_and_add_32(mem, value) \
156 ({ \
157 __typeof (*(mem)) __tmp; \
158 __typeof (mem) __memp = (mem); \
159 int test; \
160 __asm __volatile ( \
161 " addc r0, r0, r0;" \
162 "1: lwx %0, %4, r0;" \
163 " addic %1, r0, 0;" \
164 " bnei %1, 1b;" \
165 " add %1, %3, %0;" \
166 " swx %1, %4, r0;" \
167 " addic %1, r0, 0;" \
168 " bnei %1, 1b;" \
169 : "=&r" (__tmp), \
170 "=&r" (test), \
171 "=m" (*__memp) \
172 : "r" (value), \
173 "r" (__memp) \
174 : "cc", "memory"); \
175 __tmp; \
176 })
177
178#define __arch_atomic_exchange_and_add_64(mem, value) \
179 (abort (), (__typeof (*mem)) 0)
180
181#define atomic_exchange_and_add(mem, value) \
182 ({ \
183 __typeof (*(mem)) __result; \
184 if (sizeof (*mem) == 4) \
185 __result = __arch_atomic_exchange_and_add_32 (mem, value); \
186 else if (sizeof (*mem) == 8) \
187 __result = __arch_atomic_exchange_and_add_64 (mem, value); \
188 else \
189 abort (); \
190 __result; \
191 })
192
193#define __arch_atomic_increment_val_32(mem) \
194 ({ \
195 __typeof (*(mem)) __val; \
196 int test; \
197 __asm __volatile ( \
198 " addc r0, r0, r0;" \
199 "1: lwx %0, %3, r0;" \
200 " addic %1, r0, 0;" \
201 " bnei %1, 1b;" \
202 " addi %0, %0, 1;" \
203 " swx %0, %3, r0;" \
204 " addic %1, r0, 0;" \
205 " bnei %1, 1b;" \
206 : "=&r" (__val), \
207 "=&r" (test), \
208 "=m" (*mem) \
209 : "r" (mem), \
210 "m" (*mem) \
211 : "cc", "memory"); \
212 __val; \
213 })
214
215#define __arch_atomic_increment_val_64(mem) \
216 (abort (), (__typeof (*mem)) 0)
217
218#define atomic_increment_val(mem) \
219 ({ \
220 __typeof (*(mem)) __result; \
221 if (sizeof (*(mem)) == 4) \
222 __result = __arch_atomic_increment_val_32 (mem); \
223 else if (sizeof (*(mem)) == 8) \
224 __result = __arch_atomic_increment_val_64 (mem); \
225 else \
226 abort (); \
227 __result; \
228 })
229
230#define atomic_increment(mem) ({ atomic_increment_val (mem); (void) 0; })
231
232#define __arch_atomic_decrement_val_32(mem) \
233 ({ \
234 __typeof (*(mem)) __val; \
235 int test; \
236 __asm __volatile ( \
237 " addc r0, r0, r0;" \
238 "1: lwx %0, %3, r0;" \
239 " addic %1, r0, 0;" \
240 " bnei %1, 1b;" \
241 " rsubi %0, %0, 1;" \
242 " swx %0, %3, r0;" \
243 " addic %1, r0, 0;" \
244 " bnei %1, 1b;" \
245 : "=&r" (__val), \
246 "=&r" (test), \
247 "=m" (*mem) \
248 : "r" (mem), \
249 "m" (*mem) \
250 : "cc", "memory"); \
251 __val; \
252 })
253
254#define __arch_atomic_decrement_val_64(mem) \
255 (abort (), (__typeof (*mem)) 0)
256
257#define atomic_decrement_val(mem) \
258 ({ \
259 __typeof (*(mem)) __result; \
260 if (sizeof (*(mem)) == 4) \
261 __result = __arch_atomic_decrement_val_32 (mem); \
262 else if (sizeof (*(mem)) == 8) \
263 __result = __arch_atomic_decrement_val_64 (mem); \
264 else \
265 abort (); \
266 __result; \
267 })
268
269#define atomic_decrement(mem) ({ atomic_decrement_val (mem); (void) 0; })
270

Warning: That file was not part of the compilation database. It may have many parsing errors.